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GET /api/patches/126846/?format=api
{ "id": 126846, "url": "http://patches.dpdk.org/api/patches/126846/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20230515064700.624054-3-miao.li@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20230515064700.624054-3-miao.li@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20230515064700.624054-3-miao.li@intel.com", "date": "2023-05-15T06:46:58", "name": "[v1,2/4] bus/pci: avoid depending on private value in kernel source", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "2a21e14deaa00154455a51550107e083ed17ef5c", "submitter": { "id": 2220, "url": "http://patches.dpdk.org/api/people/2220/?format=api", "name": "Li, Miao", "email": "miao.li@intel.com" }, "delegate": { "id": 1, "url": "http://patches.dpdk.org/api/users/1/?format=api", "username": "tmonjalo", "first_name": "Thomas", "last_name": "Monjalon", "email": "thomas@monjalon.net" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20230515064700.624054-3-miao.li@intel.com/mbox/", "series": [ { "id": 27992, "url": "http://patches.dpdk.org/api/series/27992/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=27992", "date": "2023-05-15T06:46:56", "name": "Support VFIO sparse mmap in PCI bus", "version": 1, "mbox": "http://patches.dpdk.org/series/27992/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/126846/comments/", "check": "warning", "checks": "http://patches.dpdk.org/api/patches/126846/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 588AC42B0E;\n\tMon, 15 May 2023 08:47:35 +0200 (CEST)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 75AD2410EE;\n\tMon, 15 May 2023 08:47:30 +0200 (CEST)", "from mga06.intel.com (mga06b.intel.com [134.134.136.31])\n by mails.dpdk.org (Postfix) with ESMTP id 85A2241101\n for <dev@dpdk.org>; Mon, 15 May 2023 08:47:28 +0200 (CEST)", "from orsmga003.jf.intel.com ([10.7.209.27])\n by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 14 May 2023 23:47:27 -0700", "from dpdk-limiao-icelake.sh.intel.com ([10.67.111.26])\n by orsmga003.jf.intel.com with ESMTP; 14 May 2023 23:47:24 -0700" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1684133248; x=1715669248;\n h=from:to:cc:subject:date:message-id:in-reply-to:\n references:mime-version:content-transfer-encoding;\n bh=gcPmzOlfNKITxvRoy204CarbdVCeNunaibCoIEeHHVM=;\n b=V/faWc3wXVD0pRQ8S9JJXXVaf19Zxsd6VRugbZdUSf0lMf3u7TFTv8iF\n rhHUZxl/0GsPrZIbxqutUX/g7cRf9PDJHuF0KTa3Cm0ji5cpW9KpXcx+S\n 8+GuuRzGrHRhzdvMNZNS6abJ2WfNqiitahuDhk3y2Kj5nC4gB/V5TWDvF\n 7th2AtZzLSRN5rVfy8uToA/nJ/B2jI7xSSy/7rB4S63kgc+bKEgcSpV0G\n JptCAjZK9esg4xt00lleN3QyrhNuBl57cSCI2BvxKaICCilgKVUgtRqfB\n vxkrDAQ4dA5gZGqHo15WY+JLLnT2zY4bPD1EWlZsPuDReVByuDirVZQhX A==;", "X-IronPort-AV": [ "E=McAfee;i=\"6600,9927,10710\"; a=\"414520129\"", "E=Sophos;i=\"5.99,275,1677571200\"; d=\"scan'208\";a=\"414520129\"", "E=McAfee;i=\"6600,9927,10710\"; a=\"651306335\"", "E=Sophos;i=\"5.99,275,1677571200\"; d=\"scan'208\";a=\"651306335\"" ], "X-ExtLoop1": "1", "From": "Miao Li <miao.li@intel.com>", "To": "dev@dpdk.org", "Cc": "skori@marvell.com, thomas@monjalon.net, david.marchand@redhat.com,\n ferruh.yigit@amd.com, chenbo.xia@intel.com, yahui.cao@intel.com,\n Anatoly Burakov <anatoly.burakov@intel.com>", "Subject": "[PATCH v1 2/4] bus/pci: avoid depending on private value in kernel\n source", "Date": "Mon, 15 May 2023 06:46:58 +0000", "Message-Id": "<20230515064700.624054-3-miao.li@intel.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20230515064700.624054-1-miao.li@intel.com>", "References": "<20230418053012.10667-1-chenbo.xia@intel.com>\n <20230515064700.624054-1-miao.li@intel.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "From: Chenbo Xia <chenbo.xia@intel.com>\n\nThe value 40 used in VFIO_GET_REGION_ADDR() is a private value\n(VFIO_PCI_OFFSET_SHIFT) defined in Linux kernel source [1]. It\nis not part of VFIO API, and we should not depend on it.\n\n[1] https://github.com/torvalds/linux/blob/v6.2/include/linux/vfio_pci_core.h\n\nSigned-off-by: Chenbo Xia <chenbo.xia@intel.com>\n---\n drivers/bus/pci/linux/pci.c | 4 +-\n drivers/bus/pci/linux/pci_init.h | 4 +-\n drivers/bus/pci/linux/pci_vfio.c | 195 +++++++++++++++++++++++--------\n drivers/bus/pci/private.h | 9 ++\n lib/eal/include/rte_vfio.h | 1 -\n 5 files changed, 158 insertions(+), 55 deletions(-)", "diff": "diff --git a/drivers/bus/pci/linux/pci.c b/drivers/bus/pci/linux/pci.c\nindex 4c2c5ba382..04e21ae20f 100644\n--- a/drivers/bus/pci/linux/pci.c\n+++ b/drivers/bus/pci/linux/pci.c\n@@ -645,7 +645,7 @@ int rte_pci_read_config(const struct rte_pci_device *device,\n \t\treturn pci_uio_read_config(intr_handle, buf, len, offset);\n #ifdef VFIO_PRESENT\n \tcase RTE_PCI_KDRV_VFIO:\n-\t\treturn pci_vfio_read_config(intr_handle, buf, len, offset);\n+\t\treturn pci_vfio_read_config(device, buf, len, offset);\n #endif\n \tdefault:\n \t\trte_pci_device_name(&device->addr, devname,\n@@ -669,7 +669,7 @@ int rte_pci_write_config(const struct rte_pci_device *device,\n \t\treturn pci_uio_write_config(intr_handle, buf, len, offset);\n #ifdef VFIO_PRESENT\n \tcase RTE_PCI_KDRV_VFIO:\n-\t\treturn pci_vfio_write_config(intr_handle, buf, len, offset);\n+\t\treturn pci_vfio_write_config(device, buf, len, offset);\n #endif\n \tdefault:\n \t\trte_pci_device_name(&device->addr, devname,\ndiff --git a/drivers/bus/pci/linux/pci_init.h b/drivers/bus/pci/linux/pci_init.h\nindex dcea726186..9f6659ba6e 100644\n--- a/drivers/bus/pci/linux/pci_init.h\n+++ b/drivers/bus/pci/linux/pci_init.h\n@@ -66,9 +66,9 @@ int pci_uio_ioport_unmap(struct rte_pci_ioport *p);\n #endif\n \n /* access config space */\n-int pci_vfio_read_config(const struct rte_intr_handle *intr_handle,\n+int pci_vfio_read_config(const struct rte_pci_device *dev,\n \t\t\t void *buf, size_t len, off_t offs);\n-int pci_vfio_write_config(const struct rte_intr_handle *intr_handle,\n+int pci_vfio_write_config(const struct rte_pci_device *dev,\n \t\t\t const void *buf, size_t len, off_t offs);\n \n int pci_vfio_ioport_map(struct rte_pci_device *dev, int bar,\ndiff --git a/drivers/bus/pci/linux/pci_vfio.c b/drivers/bus/pci/linux/pci_vfio.c\nindex fab3483d9f..1748ad2ae0 100644\n--- a/drivers/bus/pci/linux/pci_vfio.c\n+++ b/drivers/bus/pci/linux/pci_vfio.c\n@@ -43,45 +43,82 @@ static struct rte_tailq_elem rte_vfio_tailq = {\n };\n EAL_REGISTER_TAILQ(rte_vfio_tailq)\n \n+static int\n+pci_vfio_get_region(const struct rte_pci_device *dev, int index,\n+\t\t uint64_t *size, uint64_t *offset)\n+{\n+\tconst struct rte_pci_device_internal *pdev =\n+\t\tRTE_PCI_DEVICE_INTERNAL_CONST(dev);\n+\n+\tif (index >= VFIO_PCI_NUM_REGIONS || index >= RTE_MAX_PCI_REGIONS)\n+\t\treturn -1;\n+\n+\tif (pdev->region[index].size == 0 && pdev->region[index].offset == 0)\n+\t\treturn -1;\n+\n+\t*size = pdev->region[index].size;\n+\t*offset = pdev->region[index].offset;\n+\n+\treturn 0;\n+}\n+\n int\n-pci_vfio_read_config(const struct rte_intr_handle *intr_handle,\n+pci_vfio_read_config(const struct rte_pci_device *dev,\n \t\t void *buf, size_t len, off_t offs)\n {\n-\tint vfio_dev_fd = rte_intr_dev_fd_get(intr_handle);\n+\tuint64_t size, offset;\n+\tint fd;\n \n-\tif (vfio_dev_fd < 0)\n+\tfd = rte_intr_dev_fd_get(dev->intr_handle);\n+\n+\tif (pci_vfio_get_region(dev, VFIO_PCI_CONFIG_REGION_INDEX,\n+\t\t\t\t&size, &offset) != 0)\n+\t\treturn -1;\n+\n+\tif ((uint64_t)len + offs > size)\n \t\treturn -1;\n \n-\treturn pread64(vfio_dev_fd, buf, len,\n-\t VFIO_GET_REGION_ADDR(VFIO_PCI_CONFIG_REGION_INDEX) + offs);\n+\treturn pread64(fd, buf, len, offset + offs);\n }\n \n int\n-pci_vfio_write_config(const struct rte_intr_handle *intr_handle,\n+pci_vfio_write_config(const struct rte_pci_device *dev,\n \t\t const void *buf, size_t len, off_t offs)\n {\n-\tint vfio_dev_fd = rte_intr_dev_fd_get(intr_handle);\n+\tuint64_t size, offset;\n+\tint fd;\n \n-\tif (vfio_dev_fd < 0)\n+\tfd = rte_intr_dev_fd_get(dev->intr_handle);\n+\n+\tif (pci_vfio_get_region(dev, VFIO_PCI_CONFIG_REGION_INDEX,\n+\t\t\t\t&size, &offset) != 0)\n \t\treturn -1;\n \n-\treturn pwrite64(vfio_dev_fd, buf, len,\n-\t VFIO_GET_REGION_ADDR(VFIO_PCI_CONFIG_REGION_INDEX) + offs);\n+\tif ((uint64_t)len + offs > size)\n+\t\treturn -1;\n+\n+\treturn pwrite64(fd, buf, len, offset + offs);\n }\n \n /* get PCI BAR number where MSI-X interrupts are */\n static int\n-pci_vfio_get_msix_bar(int fd, struct pci_msix_table *msix_table)\n+pci_vfio_get_msix_bar(const struct rte_pci_device *dev, int fd,\n+\tstruct pci_msix_table *msix_table)\n {\n \tint ret;\n \tuint32_t reg;\n \tuint16_t flags;\n \tuint8_t cap_id, cap_offset;\n+\tuint64_t size, offset;\n+\n+\tif (pci_vfio_get_region(dev, VFIO_PCI_CONFIG_REGION_INDEX,\n+\t\t&size, &offset) != 0) {\n+\t\tRTE_LOG(ERR, EAL, \"Cannot get offset of CONFIG region.\\n\");\n+\t\treturn -1;\n+\t}\n \n \t/* read PCI capability pointer from config space */\n-\tret = pread64(fd, ®, sizeof(reg),\n-\t\t\tVFIO_GET_REGION_ADDR(VFIO_PCI_CONFIG_REGION_INDEX) +\n-\t\t\tPCI_CAPABILITY_LIST);\n+\tret = pread64(fd, ®, sizeof(reg), offset + PCI_CAPABILITY_LIST);\n \tif (ret != sizeof(reg)) {\n \t\tRTE_LOG(ERR, EAL,\n \t\t\t\"Cannot read capability pointer from PCI config space!\\n\");\n@@ -94,9 +131,7 @@ pci_vfio_get_msix_bar(int fd, struct pci_msix_table *msix_table)\n \twhile (cap_offset) {\n \n \t\t/* read PCI capability ID */\n-\t\tret = pread64(fd, ®, sizeof(reg),\n-\t\t\t\tVFIO_GET_REGION_ADDR(VFIO_PCI_CONFIG_REGION_INDEX) +\n-\t\t\t\tcap_offset);\n+\t\tret = pread64(fd, ®, sizeof(reg), offset + cap_offset);\n \t\tif (ret != sizeof(reg)) {\n \t\t\tRTE_LOG(ERR, EAL,\n \t\t\t\t\"Cannot read capability ID from PCI config space!\\n\");\n@@ -108,9 +143,7 @@ pci_vfio_get_msix_bar(int fd, struct pci_msix_table *msix_table)\n \n \t\t/* if we haven't reached MSI-X, check next capability */\n \t\tif (cap_id != PCI_CAP_ID_MSIX) {\n-\t\t\tret = pread64(fd, ®, sizeof(reg),\n-\t\t\t\t\tVFIO_GET_REGION_ADDR(VFIO_PCI_CONFIG_REGION_INDEX) +\n-\t\t\t\t\tcap_offset);\n+\t\t\tret = pread64(fd, ®, sizeof(reg), offset + cap_offset);\n \t\t\tif (ret != sizeof(reg)) {\n \t\t\t\tRTE_LOG(ERR, EAL,\n \t\t\t\t\t\"Cannot read capability pointer from PCI config space!\\n\");\n@@ -125,18 +158,14 @@ pci_vfio_get_msix_bar(int fd, struct pci_msix_table *msix_table)\n \t\t/* else, read table offset */\n \t\telse {\n \t\t\t/* table offset resides in the next 4 bytes */\n-\t\t\tret = pread64(fd, ®, sizeof(reg),\n-\t\t\t\t\tVFIO_GET_REGION_ADDR(VFIO_PCI_CONFIG_REGION_INDEX) +\n-\t\t\t\t\tcap_offset + 4);\n+\t\t\tret = pread64(fd, ®, sizeof(reg), offset + cap_offset + 4);\n \t\t\tif (ret != sizeof(reg)) {\n \t\t\t\tRTE_LOG(ERR, EAL,\n \t\t\t\t\t\"Cannot read table offset from PCI config space!\\n\");\n \t\t\t\treturn -1;\n \t\t\t}\n \n-\t\t\tret = pread64(fd, &flags, sizeof(flags),\n-\t\t\t\t\tVFIO_GET_REGION_ADDR(VFIO_PCI_CONFIG_REGION_INDEX) +\n-\t\t\t\t\tcap_offset + 2);\n+\t\t\tret = pread64(fd, &flags, sizeof(flags), offset + cap_offset + 2);\n \t\t\tif (ret != sizeof(flags)) {\n \t\t\t\tRTE_LOG(ERR, EAL,\n \t\t\t\t\t\"Cannot read table flags from PCI config space!\\n\");\n@@ -156,14 +185,19 @@ pci_vfio_get_msix_bar(int fd, struct pci_msix_table *msix_table)\n \n /* enable PCI bus memory space */\n static int\n-pci_vfio_enable_bus_memory(int dev_fd)\n+pci_vfio_enable_bus_memory(struct rte_pci_device *dev, int dev_fd)\n {\n+\tuint64_t size, offset;\n \tuint16_t cmd;\n \tint ret;\n \n-\tret = pread64(dev_fd, &cmd, sizeof(cmd),\n-\t\t VFIO_GET_REGION_ADDR(VFIO_PCI_CONFIG_REGION_INDEX) +\n-\t\t PCI_COMMAND);\n+\tif (pci_vfio_get_region(dev, VFIO_PCI_CONFIG_REGION_INDEX,\n+\t\t&size, &offset) != 0) {\n+\t\tRTE_LOG(ERR, EAL, \"Cannot get offset of CONFIG region.\\n\");\n+\t\treturn -1;\n+\t}\n+\n+\tret = pread64(dev_fd, &cmd, sizeof(cmd), offset + PCI_COMMAND);\n \n \tif (ret != sizeof(cmd)) {\n \t\tRTE_LOG(ERR, EAL, \"Cannot read command from PCI config space!\\n\");\n@@ -174,9 +208,7 @@ pci_vfio_enable_bus_memory(int dev_fd)\n \t\treturn 0;\n \n \tcmd |= PCI_COMMAND_MEMORY;\n-\tret = pwrite64(dev_fd, &cmd, sizeof(cmd),\n-\t\t VFIO_GET_REGION_ADDR(VFIO_PCI_CONFIG_REGION_INDEX) +\n-\t\t PCI_COMMAND);\n+\tret = pwrite64(dev_fd, &cmd, sizeof(cmd), offset + PCI_COMMAND);\n \n \tif (ret != sizeof(cmd)) {\n \t\tRTE_LOG(ERR, EAL, \"Cannot write command to PCI config space!\\n\");\n@@ -188,14 +220,19 @@ pci_vfio_enable_bus_memory(int dev_fd)\n \n /* set PCI bus mastering */\n static int\n-pci_vfio_set_bus_master(int dev_fd, bool op)\n+pci_vfio_set_bus_master(const struct rte_pci_device *dev, int dev_fd, bool op)\n {\n+\tuint64_t size, offset;\n \tuint16_t reg;\n \tint ret;\n \n-\tret = pread64(dev_fd, ®, sizeof(reg),\n-\t\t\tVFIO_GET_REGION_ADDR(VFIO_PCI_CONFIG_REGION_INDEX) +\n-\t\t\tPCI_COMMAND);\n+\tif (pci_vfio_get_region(dev, VFIO_PCI_CONFIG_REGION_INDEX,\n+\t\t&size, &offset) != 0) {\n+\t\tRTE_LOG(ERR, EAL, \"Cannot get offset of CONFIG region.\\n\");\n+\t\treturn -1;\n+\t}\n+\n+\tret = pread64(dev_fd, ®, sizeof(reg), offset + PCI_COMMAND);\n \tif (ret != sizeof(reg)) {\n \t\tRTE_LOG(ERR, EAL, \"Cannot read command from PCI config space!\\n\");\n \t\treturn -1;\n@@ -207,9 +244,7 @@ pci_vfio_set_bus_master(int dev_fd, bool op)\n \telse\n \t\treg &= ~(PCI_COMMAND_MASTER);\n \n-\tret = pwrite64(dev_fd, ®, sizeof(reg),\n-\t\t\tVFIO_GET_REGION_ADDR(VFIO_PCI_CONFIG_REGION_INDEX) +\n-\t\t\tPCI_COMMAND);\n+\tret = pwrite64(dev_fd, ®, sizeof(reg), offset + PCI_COMMAND);\n \n \tif (ret != sizeof(reg)) {\n \t\tRTE_LOG(ERR, EAL, \"Cannot write command to PCI config space!\\n\");\n@@ -458,14 +493,21 @@ pci_vfio_disable_notifier(struct rte_pci_device *dev)\n #endif\n \n static int\n-pci_vfio_is_ioport_bar(int vfio_dev_fd, int bar_index)\n+pci_vfio_is_ioport_bar(const struct rte_pci_device *dev, int vfio_dev_fd,\n+\tint bar_index)\n {\n+\tuint64_t size, offset;\n \tuint32_t ioport_bar;\n \tint ret;\n \n+\tif (pci_vfio_get_region(dev, VFIO_PCI_CONFIG_REGION_INDEX,\n+\t\t&size, &offset) != 0) {\n+\t\tRTE_LOG(ERR, EAL, \"Cannot get offset of CONFIG region.\\n\");\n+\t\treturn -1;\n+\t}\n+\n \tret = pread64(vfio_dev_fd, &ioport_bar, sizeof(ioport_bar),\n-\t\t\t VFIO_GET_REGION_ADDR(VFIO_PCI_CONFIG_REGION_INDEX)\n-\t\t\t + PCI_BASE_ADDRESS_0 + bar_index*4);\n+\t\t\t offset + PCI_BASE_ADDRESS_0 + bar_index * 4);\n \tif (ret != sizeof(ioport_bar)) {\n \t\tRTE_LOG(ERR, EAL, \"Cannot read command (%x) from config space!\\n\",\n \t\t\tPCI_BASE_ADDRESS_0 + bar_index*4);\n@@ -483,13 +525,13 @@ pci_rte_vfio_setup_device(struct rte_pci_device *dev, int vfio_dev_fd)\n \t\treturn -1;\n \t}\n \n-\tif (pci_vfio_enable_bus_memory(vfio_dev_fd)) {\n+\tif (pci_vfio_enable_bus_memory(dev, vfio_dev_fd)) {\n \t\tRTE_LOG(ERR, EAL, \"Cannot enable bus memory!\\n\");\n \t\treturn -1;\n \t}\n \n \t/* set bus mastering for the device */\n-\tif (pci_vfio_set_bus_master(vfio_dev_fd, true)) {\n+\tif (pci_vfio_set_bus_master(dev, vfio_dev_fd, true)) {\n \t\tRTE_LOG(ERR, EAL, \"Cannot set up bus mastering!\\n\");\n \t\treturn -1;\n \t}\n@@ -719,11 +761,40 @@ pci_vfio_msix_is_mappable(int vfio_dev_fd, int msix_region)\n \treturn ret;\n }\n \n+static int\n+pci_vfio_fill_regions(struct rte_pci_device *dev, int vfio_dev_fd,\n+\t\t struct vfio_device_info *device_info)\n+{\n+\tstruct rte_pci_device_internal *pdev = RTE_PCI_DEVICE_INTERNAL(dev);\n+\tstruct vfio_region_info *reg = NULL;\n+\tint nb_maps, i, ret;\n+\n+\tnb_maps = RTE_MIN((int)device_info->num_regions,\n+\t\t\tVFIO_PCI_CONFIG_REGION_INDEX + 1);\n+\n+\tfor (i = 0; i < nb_maps; i++) {\n+\t\tret = pci_vfio_get_region_info(vfio_dev_fd, ®, i);\n+\t\tif (ret < 0) {\n+\t\t\tRTE_LOG(DEBUG, EAL, \"%s cannot get device region info error %i (%s)\\n\",\n+\t\t\t\tdev->name, errno, strerror(errno));\n+\t\t\treturn -1;\n+\t\t}\n+\n+\t\tpdev->region[i].size = reg->size;\n+\t\tpdev->region[i].offset = reg->offset;\n+\n+\t\tfree(reg);\n+\t}\n+\n+\treturn 0;\n+}\n \n static int\n pci_vfio_map_resource_primary(struct rte_pci_device *dev)\n {\n+\tstruct rte_pci_device_internal *pdev = RTE_PCI_DEVICE_INTERNAL(dev);\n \tstruct vfio_device_info device_info = { .argsz = sizeof(device_info) };\n+\tstruct vfio_region_info *reg = NULL;\n \tchar pci_addr[PATH_MAX] = {0};\n \tint vfio_dev_fd;\n \tstruct rte_pci_addr *loc = &dev->addr;\n@@ -767,11 +838,22 @@ pci_vfio_map_resource_primary(struct rte_pci_device *dev)\n \t/* map BARs */\n \tmaps = vfio_res->maps;\n \n+\tret = pci_vfio_get_region_info(vfio_dev_fd, ®,\n+\t\tVFIO_PCI_CONFIG_REGION_INDEX);\n+\tif (ret < 0) {\n+\t\tRTE_LOG(ERR, EAL, \"%s cannot get device region info error %i (%s)\\n\",\n+\t\t\tdev->name, errno, strerror(errno));\n+\t\tgoto err_vfio_res;\n+\t}\n+\tpdev->region[VFIO_PCI_CONFIG_REGION_INDEX].size = reg->size;\n+\tpdev->region[VFIO_PCI_CONFIG_REGION_INDEX].offset = reg->offset;\n+\tfree(reg);\n+\n \tvfio_res->msix_table.bar_index = -1;\n \t/* get MSI-X BAR, if any (we have to know where it is because we can't\n \t * easily mmap it when using VFIO)\n \t */\n-\tret = pci_vfio_get_msix_bar(vfio_dev_fd, &vfio_res->msix_table);\n+\tret = pci_vfio_get_msix_bar(dev, vfio_dev_fd, &vfio_res->msix_table);\n \tif (ret < 0) {\n \t\tRTE_LOG(ERR, EAL, \"%s cannot get MSI-X BAR number!\\n\",\n \t\t\t\tpci_addr);\n@@ -792,7 +874,6 @@ pci_vfio_map_resource_primary(struct rte_pci_device *dev)\n \t}\n \n \tfor (i = 0; i < vfio_res->nb_maps; i++) {\n-\t\tstruct vfio_region_info *reg = NULL;\n \t\tvoid *bar_addr;\n \n \t\tret = pci_vfio_get_region_info(vfio_dev_fd, ®, i);\n@@ -803,8 +884,11 @@ pci_vfio_map_resource_primary(struct rte_pci_device *dev)\n \t\t\tgoto err_vfio_res;\n \t\t}\n \n+\t\tpdev->region[i].size = reg->size;\n+\t\tpdev->region[i].offset = reg->offset;\n+\n \t\t/* chk for io port region */\n-\t\tret = pci_vfio_is_ioport_bar(vfio_dev_fd, i);\n+\t\tret = pci_vfio_is_ioport_bar(dev, vfio_dev_fd, i);\n \t\tif (ret < 0) {\n \t\t\tfree(reg);\n \t\t\tgoto err_vfio_res;\n@@ -916,6 +1000,10 @@ pci_vfio_map_resource_secondary(struct rte_pci_device *dev)\n \tif (ret)\n \t\treturn ret;\n \n+\tret = pci_vfio_fill_regions(dev, vfio_dev_fd, &device_info);\n+\tif (ret)\n+\t\treturn ret;\n+\n \t/* map BARs */\n \tmaps = vfio_res->maps;\n \n@@ -1031,7 +1119,7 @@ pci_vfio_unmap_resource_primary(struct rte_pci_device *dev)\n \tif (vfio_dev_fd < 0)\n \t\treturn -1;\n \n-\tif (pci_vfio_set_bus_master(vfio_dev_fd, false)) {\n+\tif (pci_vfio_set_bus_master(dev, vfio_dev_fd, false)) {\n \t\tRTE_LOG(ERR, EAL, \"%s cannot unset bus mastering for PCI device!\\n\",\n \t\t\t\tpci_addr);\n \t\treturn -1;\n@@ -1111,14 +1199,21 @@ int\n pci_vfio_ioport_map(struct rte_pci_device *dev, int bar,\n \t\t struct rte_pci_ioport *p)\n {\n+\tuint64_t size, offset;\n+\n \tif (bar < VFIO_PCI_BAR0_REGION_INDEX ||\n \t bar > VFIO_PCI_BAR5_REGION_INDEX) {\n \t\tRTE_LOG(ERR, EAL, \"invalid bar (%d)!\\n\", bar);\n \t\treturn -1;\n \t}\n \n+\tif (pci_vfio_get_region(dev, bar, &size, &offset) != 0) {\n+\t\tRTE_LOG(ERR, EAL, \"Cannot get offset of region %d.\\n\", bar);\n+\t\treturn -1;\n+\t}\n+\n \tp->dev = dev;\n-\tp->base = VFIO_GET_REGION_ADDR(bar);\n+\tp->base = offset;\n \treturn 0;\n }\n \ndiff --git a/drivers/bus/pci/private.h b/drivers/bus/pci/private.h\nindex b564646e03..2d6991ccb7 100644\n--- a/drivers/bus/pci/private.h\n+++ b/drivers/bus/pci/private.h\n@@ -13,6 +13,8 @@\n #include <rte_os_shim.h>\n #include <rte_pci.h>\n \n+#define RTE_MAX_PCI_REGIONS 9\n+\n /*\n * Convert struct rte_pci_device to struct rte_pci_device_internal\n */\n@@ -42,8 +44,15 @@ extern struct rte_pci_bus rte_pci_bus;\n struct rte_pci_driver;\n struct rte_pci_device;\n \n+struct rte_pci_region {\n+\tuint64_t size;\n+\tuint64_t offset;\n+};\n+\n struct rte_pci_device_internal {\n \tstruct rte_pci_device device;\n+\t/* PCI regions provided by e.g. VFIO. */\n+\tstruct rte_pci_region region[RTE_MAX_PCI_REGIONS];\n };\n \n /**\ndiff --git a/lib/eal/include/rte_vfio.h b/lib/eal/include/rte_vfio.h\nindex 7bdb8932b2..3487c4f2a2 100644\n--- a/lib/eal/include/rte_vfio.h\n+++ b/lib/eal/include/rte_vfio.h\n@@ -38,7 +38,6 @@ extern \"C\" {\n #define VFIO_CONTAINER_PATH \"/dev/vfio/vfio\"\n #define VFIO_GROUP_FMT \"/dev/vfio/%u\"\n #define VFIO_NOIOMMU_GROUP_FMT \"/dev/vfio/noiommu-%u\"\n-#define VFIO_GET_REGION_ADDR(x) ((uint64_t) x << 40ULL)\n #define VFIO_GET_REGION_IDX(x) (x >> 40)\n #define VFIO_NOIOMMU_MODE \\\n \t\"/sys/module/vfio/parameters/enable_unsafe_noiommu_mode\"\n", "prefixes": [ "v1", "2/4" ] }