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GET /api/patches/126833/?format=api
{ "id": 126833, "url": "http://patches.dpdk.org/api/patches/126833/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20230512125621.1131396-2-ktejasree@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20230512125621.1131396-2-ktejasree@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20230512125621.1131396-2-ktejasree@marvell.com", "date": "2023-05-12T12:56:20", "name": "[1/2] crypto/cnxk: add AES CCM support", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "c6afcedd0d1062590f9a8aa359b5d350bb5c9170", "submitter": { "id": 1789, "url": "http://patches.dpdk.org/api/people/1789/?format=api", "name": "Tejasree Kondoj", "email": "ktejasree@marvell.com" }, "delegate": { "id": 6690, "url": "http://patches.dpdk.org/api/users/6690/?format=api", "username": "akhil", "first_name": "akhil", "last_name": "goyal", "email": "gakhil@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20230512125621.1131396-2-ktejasree@marvell.com/mbox/", "series": [ { "id": 27985, "url": "http://patches.dpdk.org/api/series/27985/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=27985", "date": "2023-05-12T12:56:19", "name": "AES CCM support in CNXK crypto PMD", "version": 1, "mbox": "http://patches.dpdk.org/series/27985/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/126833/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/126833/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 2D2A642AE5;\n\tFri, 12 May 2023 14:56:34 +0200 (CEST)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 31D9E42F98;\n\tFri, 12 May 2023 14:56:32 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com\n [67.231.148.174])\n by mails.dpdk.org (Postfix) with ESMTP id 2363B42F94\n for <dev@dpdk.org>; Fri, 12 May 2023 14:56:29 +0200 (CEST)", "from pps.filterd (m0045849.ppops.net [127.0.0.1])\n by mx0a-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id\n 34C90ju3021725 for <dev@dpdk.org>; Fri, 12 May 2023 05:56:29 -0700", "from dc5-exch02.marvell.com ([199.233.59.182])\n by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3qh9tk2mh5-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Fri, 12 May 2023 05:56:29 -0700", "from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.48;\n Fri, 12 May 2023 05:56:27 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.48 via Frontend\n Transport; Fri, 12 May 2023 05:56:27 -0700", "from hyd1554.marvell.com (unknown [10.29.57.11])\n by maili.marvell.com (Postfix) with ESMTP id 32E283F706C;\n Fri, 12 May 2023 05:56:24 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-transfer-encoding : content-type; s=pfpt0220;\n bh=yN7WTXIfpbUR8qCC6IFneUoE2kDB20S74FRYQGULMQs=;\n b=C6nGtWc8Cs2fLGliBbwtRpGRisUGFur+8tvirJgsI3pbSuAgPazUM/mwkPQiYjvRFXuz\n KG4R4yoooxRTzSpCS7C8JYoe3EfBodY6LB05JJmYn2HCETUoaqqQ08KqDN9Imvr8kfH9\n Gev6jOZLwqYpPODdy/Nm8HIl6hWpteYAdh9U0b2/sQqB65uJUe3FNMYJnK6vrOiRCFON\n IQS3qcTLCvlocu+OOn3OTUA1IAV39JGtZQ88511cU+I2Vh+87wp174IWAbeUVFWAnOR+\n QkiVkPVSRkYIiXyST3w7AdARXaFnIHUATU7HxEmzqO2A3AmPJCbTysOnGOlHQHOlDcpd pQ==", "From": "Tejasree Kondoj <ktejasree@marvell.com>", "To": "Akhil Goyal <gakhil@marvell.com>", "CC": "Anoob Joseph <anoobj@marvell.com>, Jerin Jacob <jerinj@marvell.com>,\n Aakash Sasidharan <asasidharan@marvell.com>, Gowrishankar Muthukrishnan\n <gmuthukrishn@marvell.com>,\n Vidya Sagar Velumuri <vvelumuri@marvell.com>, <dev@dpdk.org>", "Subject": "[PATCH 1/2] crypto/cnxk: add AES CCM support", "Date": "Fri, 12 May 2023 18:26:20 +0530", "Message-ID": "<20230512125621.1131396-2-ktejasree@marvell.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20230512125621.1131396-1-ktejasree@marvell.com>", "References": "<20230512125621.1131396-1-ktejasree@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-GUID": "UF3JnbgB5fRoj-CWi0rFWYjitOoy87Av", "X-Proofpoint-ORIG-GUID": "UF3JnbgB5fRoj-CWi0rFWYjitOoy87Av", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.254,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22\n definitions=2023-05-12_08,2023-05-05_01,2023-02-09_01", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Adding AES CCM support to lookaside crypto PMD.\n\nSigned-off-by: Tejasree Kondoj <ktejasree@marvell.com>\n---\n doc/guides/cryptodevs/cnxk.rst | 1 +\n doc/guides/cryptodevs/features/cn10k.ini | 3 ++\n doc/guides/cryptodevs/features/cn9k.ini | 3 ++\n drivers/common/cnxk/roc_se.c | 4 +-\n drivers/common/cnxk/roc_se.h | 1 +\n .../crypto/cnxk/cnxk_cryptodev_capabilities.c | 30 ++++++++++++\n drivers/crypto/cnxk/cnxk_cryptodev_ops.c | 2 +-\n drivers/crypto/cnxk/cnxk_se.h | 49 ++++++++++++++-----\n 8 files changed, 78 insertions(+), 15 deletions(-)", "diff": "diff --git a/doc/guides/cryptodevs/cnxk.rst b/doc/guides/cryptodevs/cnxk.rst\nindex 3c2e38fefd..2d3ceebcaa 100644\n--- a/doc/guides/cryptodevs/cnxk.rst\n+++ b/doc/guides/cryptodevs/cnxk.rst\n@@ -76,6 +76,7 @@ Hash algorithms:\n AEAD algorithms:\n \n * ``RTE_CRYPTO_AEAD_AES_GCM``\n+* ``RTE_CRYPTO_AEAD_AES_CCM``\n * ``RTE_CRYPTO_AEAD_CHACHA20_POLY1305``\n \n Asymmetric Crypto Algorithms\ndiff --git a/doc/guides/cryptodevs/features/cn10k.ini b/doc/guides/cryptodevs/features/cn10k.ini\nindex 162d1a25ca..bb5827eb82 100644\n--- a/doc/guides/cryptodevs/features/cn10k.ini\n+++ b/doc/guides/cryptodevs/features/cn10k.ini\n@@ -81,6 +81,9 @@ SHAKE_256 = Y\n AES GCM (128) = Y\n AES GCM (192) = Y\n AES GCM (256) = Y\n+AES CCM (128) = Y\n+AES CCM (192) = Y\n+AES CCM (256) = Y\n CHACHA20-POLY1305 = Y\n \n ;\ndiff --git a/doc/guides/cryptodevs/features/cn9k.ini b/doc/guides/cryptodevs/features/cn9k.ini\nindex bbed4b2e23..bf0e1a98b2 100644\n--- a/doc/guides/cryptodevs/features/cn9k.ini\n+++ b/doc/guides/cryptodevs/features/cn9k.ini\n@@ -82,6 +82,9 @@ SHAKE_256 = Y\n AES GCM (128) = Y\n AES GCM (192) = Y\n AES GCM (256) = Y\n+AES CCM (128) = Y\n+AES CCM (192) = Y\n+AES CCM (256) = Y\n CHACHA20-POLY1305 = Y\n \n ;\ndiff --git a/drivers/common/cnxk/roc_se.c b/drivers/common/cnxk/roc_se.c\nindex 5a894013a6..0c0ddaf6c3 100644\n--- a/drivers/common/cnxk/roc_se.c\n+++ b/drivers/common/cnxk/roc_se.c\n@@ -71,6 +71,7 @@ cpt_ciph_type_set(roc_se_cipher_type type, struct roc_se_ctx *ctx,\n \tcase ROC_SE_AES_CFB:\n \tcase ROC_SE_AES_CTR:\n \tcase ROC_SE_AES_GCM:\n+\tcase ROC_SE_AES_CCM:\n \tcase ROC_SE_AES_DOCSISBPI:\n \t\tif (unlikely(cpt_ciph_aes_key_validate(key_len) != 0))\n \t\t\treturn -1;\n@@ -520,7 +521,7 @@ roc_se_ciph_key_set(struct roc_se_ctx *se_ctx, roc_se_cipher_type type, const ui\n \t\tzuc_const = zs_ctx->zuc.otk_ctx.zuc_const;\n \t}\n \n-\tif (type == ROC_SE_AES_GCM)\n+\tif ((type == ROC_SE_AES_GCM) || (type == ROC_SE_AES_CCM))\n \t\tse_ctx->template_w4.s.opcode_minor = BIT(5);\n \n \tret = cpt_ciph_type_set(type, se_ctx, key_len);\n@@ -569,6 +570,7 @@ roc_se_ciph_key_set(struct roc_se_ctx *se_ctx, roc_se_cipher_type type, const ui\n \t\tcpt_ciph_aes_key_type_set(fctx, key_len);\n \t\tbreak;\n \tcase ROC_SE_AES_GCM:\n+\tcase ROC_SE_AES_CCM:\n \t\tcpt_ciph_aes_key_type_set(fctx, key_len);\n \t\tbreak;\n \tcase ROC_SE_AES_XTS:\ndiff --git a/drivers/common/cnxk/roc_se.h b/drivers/common/cnxk/roc_se.h\nindex a0c97b26c5..56f510f7a0 100644\n--- a/drivers/common/cnxk/roc_se.h\n+++ b/drivers/common/cnxk/roc_se.h\n@@ -112,6 +112,7 @@ typedef enum {\n \tROC_SE_AES_GCM = 0x7,\n \tROC_SE_AES_XTS = 0x8,\n \tROC_SE_CHACHA20 = 0x9,\n+\tROC_SE_AES_CCM = 0xA,\n \n \t/* These are only for software use */\n \tROC_SE_ZUC_EEA3 = 0x90,\ndiff --git a/drivers/crypto/cnxk/cnxk_cryptodev_capabilities.c b/drivers/crypto/cnxk/cnxk_cryptodev_capabilities.c\nindex 19956ffa07..91483ab693 100644\n--- a/drivers/crypto/cnxk/cnxk_cryptodev_capabilities.c\n+++ b/drivers/crypto/cnxk/cnxk_cryptodev_capabilities.c\n@@ -782,6 +782,36 @@ static const struct rte_cryptodev_capabilities caps_aes[] = {\n \t\t\t}, }\n \t\t}, }\n \t},\n+\t{\t/* AES CCM */\n+\t\t.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,\n+\t\t{.sym = {\n+\t\t\t.xform_type = RTE_CRYPTO_SYM_XFORM_AEAD,\n+\t\t\t{.aead = {\n+\t\t\t\t.algo = RTE_CRYPTO_AEAD_AES_CCM,\n+\t\t\t\t.block_size = 16,\n+\t\t\t\t.key_size = {\n+\t\t\t\t\t.min = 16,\n+\t\t\t\t\t.max = 32,\n+\t\t\t\t\t.increment = 8\n+\t\t\t\t},\n+\t\t\t\t.digest_size = {\n+\t\t\t\t\t.min = 4,\n+\t\t\t\t\t.max = 16,\n+\t\t\t\t\t.increment = 1\n+\t\t\t\t},\n+\t\t\t\t.aad_size = {\n+\t\t\t\t\t.min = 0,\n+\t\t\t\t\t.max = 1024,\n+\t\t\t\t\t.increment = 1\n+\t\t\t\t},\n+\t\t\t\t.iv_size = {\n+\t\t\t\t\t.min = 11,\n+\t\t\t\t\t.max = 13,\n+\t\t\t\t\t.increment = 1\n+\t\t\t\t}\n+\t\t\t}, }\n+\t\t}, }\n+\t},\n \t{\t/* AES CMAC */\n \t\t.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,\n \t\t{.sym = {\ndiff --git a/drivers/crypto/cnxk/cnxk_cryptodev_ops.c b/drivers/crypto/cnxk/cnxk_cryptodev_ops.c\nindex 86efe75cc3..453adbfd10 100644\n--- a/drivers/crypto/cnxk/cnxk_cryptodev_ops.c\n+++ b/drivers/crypto/cnxk/cnxk_cryptodev_ops.c\n@@ -671,7 +671,7 @@ sym_session_configure(struct roc_cpt *roc_cpt, struct rte_crypto_sym_xform *xfor\n \tif (sess_priv->cpt_op & ROC_SE_OP_CIPHER_MASK) {\n \t\tswitch (sess_priv->roc_se_ctx.fc_type) {\n \t\tcase ROC_SE_FC_GEN:\n-\t\t\tif (sess_priv->aes_gcm || sess_priv->chacha_poly)\n+\t\t\tif (sess_priv->aes_gcm || sess_priv->aes_ccm || sess_priv->chacha_poly)\n \t\t\t\tthr_type = CPT_DP_THREAD_TYPE_FC_AEAD;\n \t\t\telse\n \t\t\t\tthr_type = CPT_DP_THREAD_TYPE_FC_CHAIN;\ndiff --git a/drivers/crypto/cnxk/cnxk_se.h b/drivers/crypto/cnxk/cnxk_se.h\nindex 69cd343eea..d5a131acb5 100644\n--- a/drivers/crypto/cnxk/cnxk_se.h\n+++ b/drivers/crypto/cnxk/cnxk_se.h\n@@ -31,6 +31,7 @@ struct cnxk_se_sess {\n \tuint16_t cpt_op : 4;\n \tuint16_t zsk_flag : 4;\n \tuint16_t aes_gcm : 1;\n+\tuint16_t aes_ccm : 1;\n \tuint16_t aes_ctr : 1;\n \tuint16_t chacha_poly : 1;\n \tuint16_t is_null : 1;\n@@ -1655,10 +1656,10 @@ static __rte_always_inline int\n fill_sess_aead(struct rte_crypto_sym_xform *xform, struct cnxk_se_sess *sess)\n {\n \tstruct rte_crypto_aead_xform *aead_form;\n+\tuint8_t aes_gcm = 0, aes_ccm = 0;\n \troc_se_cipher_type enc_type = 0; /* NULL Cipher type */\n \troc_se_auth_type auth_type = 0;\t /* NULL Auth type */\n \tuint32_t cipher_key_len = 0;\n-\tuint8_t aes_gcm = 0;\n \taead_form = &xform->aead;\n \n \tif (aead_form->op == RTE_CRYPTO_AEAD_OP_ENCRYPT) {\n@@ -1678,9 +1679,10 @@ fill_sess_aead(struct rte_crypto_sym_xform *xform, struct cnxk_se_sess *sess)\n \t\taes_gcm = 1;\n \t\tbreak;\n \tcase RTE_CRYPTO_AEAD_AES_CCM:\n-\t\tplt_dp_err(\"Crypto: Unsupported cipher algo %u\",\n-\t\t\t aead_form->algo);\n-\t\treturn -1;\n+\t\tenc_type = ROC_SE_AES_CCM;\n+\t\tcipher_key_len = 16;\n+\t\taes_ccm = 1;\n+\t\tbreak;\n \tcase RTE_CRYPTO_AEAD_CHACHA20_POLY1305:\n \t\tenc_type = ROC_SE_CHACHA20;\n \t\tauth_type = ROC_SE_POLY1305;\n@@ -1699,19 +1701,27 @@ fill_sess_aead(struct rte_crypto_sym_xform *xform, struct cnxk_se_sess *sess)\n \t}\n \tsess->zsk_flag = 0;\n \tsess->aes_gcm = aes_gcm;\n+\tsess->aes_ccm = aes_ccm;\n \tsess->mac_len = aead_form->digest_length;\n \tsess->iv_offset = aead_form->iv.offset;\n \tsess->iv_length = aead_form->iv.length;\n \tsess->aad_length = aead_form->aad_length;\n \n-\tswitch (sess->iv_length) {\n-\tcase 12:\n-\t\tsess->short_iv = 1;\n-\tcase 16:\n-\t\tbreak;\n-\tdefault:\n-\t\tplt_dp_err(\"Crypto: Unsupported IV length %u\", sess->iv_length);\n-\t\treturn -1;\n+\tif (aes_ccm) {\n+\t\tif ((sess->iv_length < 11) || (sess->iv_length > 13)) {\n+\t\t\tplt_dp_err(\"Crypto: Unsupported IV length %u\", sess->iv_length);\n+\t\t\treturn -1;\n+\t\t}\n+\t} else {\n+\t\tswitch (sess->iv_length) {\n+\t\tcase 12:\n+\t\t\tsess->short_iv = 1;\n+\t\tcase 16:\n+\t\t\tbreak;\n+\t\tdefault:\n+\t\t\tplt_dp_err(\"Crypto: Unsupported IV length %u\", sess->iv_length);\n+\t\t\treturn -1;\n+\t\t}\n \t}\n \n \tif (unlikely(roc_se_ciph_key_set(&sess->roc_se_ctx, enc_type, aead_form->key.data,\n@@ -1856,6 +1866,7 @@ fill_sess_cipher(struct rte_crypto_sym_xform *xform, struct cnxk_se_sess *sess)\n \tsess->zsk_flag = zsk_flag;\n \tsess->zs_cipher = zs_cipher;\n \tsess->aes_gcm = 0;\n+\tsess->aes_ccm = 0;\n \tsess->aes_ctr = aes_ctr;\n \tsess->iv_offset = c_form->iv.offset;\n \tsess->iv_length = c_form->iv.length;\n@@ -2218,6 +2229,7 @@ fill_fc_params(struct rte_crypto_op *cop, struct cnxk_se_sess *sess,\n \tstruct roc_se_fc_params fc_params;\n \tchar src[SRC_IOV_SIZE];\n \tchar dst[SRC_IOV_SIZE];\n+\tuint8_t ccm_iv_buf[16];\n \tuint32_t iv_buf[4];\n \tint ret;\n \n@@ -2237,6 +2249,13 @@ fill_fc_params(struct rte_crypto_op *cop, struct cnxk_se_sess *sess,\n \t\t\tiv_buf[3] = rte_cpu_to_be_32(0x1);\n \t\t\tfc_params.iv_buf = iv_buf;\n \t\t}\n+\t\tif (sess->aes_ccm) {\n+\t\t\tmemcpy((uint8_t *)ccm_iv_buf,\n+\t\t\t rte_crypto_op_ctod_offset(cop, uint8_t *, sess->iv_offset),\n+\t\t\t sess->iv_length + 1);\n+\t\t\tccm_iv_buf[0] = 14 - sess->iv_length;\n+\t\t\tfc_params.iv_buf = ccm_iv_buf;\n+\t\t}\n \t}\n \n \t/* Kasumi would need SG mode */\n@@ -2264,7 +2283,11 @@ fill_fc_params(struct rte_crypto_op *cop, struct cnxk_se_sess *sess,\n \t\t\td_offs = (d_offs - aad_len) | (d_offs << 16);\n \t\t\td_lens = (d_lens + aad_len) | (d_lens << 32);\n \t\t} else {\n-\t\t\tfc_params.aad_buf.vaddr = sym_op->aead.aad.data;\n+\t\t\t/* For AES CCM, AAD is written 18B after aad.data as per API */\n+\t\t\tif (sess->aes_ccm)\n+\t\t\t\tfc_params.aad_buf.vaddr = PLT_PTR_ADD(sym_op->aead.aad.data, 18);\n+\t\t\telse\n+\t\t\t\tfc_params.aad_buf.vaddr = sym_op->aead.aad.data;\n \t\t\tfc_params.aad_buf.size = aad_len;\n \t\t\tflags |= ROC_SE_VALID_AAD_BUF;\n \t\t\tinplace = 0;\n", "prefixes": [ "1/2" ] }