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GET /api/patches/126593/?format=api
{ "id": 126593, "url": "http://patches.dpdk.org/api/patches/126593/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20230427062001.478032-27-qiming.yang@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20230427062001.478032-27-qiming.yang@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20230427062001.478032-27-qiming.yang@intel.com", "date": "2023-04-27T06:19:57", "name": "[26/30] net/ice/base: remove bypass mode", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "aa8769a5c788a0b476c2bd56813e2f3b1b8bec46", "submitter": { "id": 522, "url": "http://patches.dpdk.org/api/people/522/?format=api", "name": "Qiming Yang", "email": "qiming.yang@intel.com" }, "delegate": { "id": 1540, "url": "http://patches.dpdk.org/api/users/1540/?format=api", "username": "qzhan15", "first_name": "Qi", "last_name": "Zhang", "email": "qi.z.zhang@intel.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20230427062001.478032-27-qiming.yang@intel.com/mbox/", "series": [ { "id": 27885, "url": "http://patches.dpdk.org/api/series/27885/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=27885", "date": "2023-04-27T06:19:31", "name": "net/ice/base: share code update", "version": 1, "mbox": "http://patches.dpdk.org/series/27885/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/126593/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/126593/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 688FB42A08;\n\tThu, 27 Apr 2023 08:40:45 +0200 (CEST)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 02B1542D8E;\n\tThu, 27 Apr 2023 08:38:35 +0200 (CEST)", "from mga01.intel.com (mga01.intel.com [192.55.52.88])\n by mails.dpdk.org (Postfix) with ESMTP id D407942FCA\n for <dev@dpdk.org>; Thu, 27 Apr 2023 08:38:31 +0200 (CEST)", "from fmsmga002.fm.intel.com ([10.253.24.26])\n by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 26 Apr 2023 23:38:31 -0700", "from dpdk-qiming3.sh.intel.com ([10.67.111.4])\n by fmsmga002.fm.intel.com with ESMTP; 26 Apr 2023 23:38:29 -0700" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1682577512; x=1714113512;\n h=from:to:cc:subject:date:message-id:in-reply-to:\n references:mime-version:content-transfer-encoding;\n bh=dF97cSmz6+9STeAizzXertFrp/4FZ8ZNquUReSv4bb8=;\n b=Kvjl1yL9CJnmEbgIY+WId3WD4MJcfadAGVwqRI6vpBTx+nt3a9i37pRV\n cx2oO0FlPmwjTf9dV3Ow3iRcSdAp1cdzhl94Q2PrJ2k6o48akctkTfsso\n fwSUs4jtOp52fR8EqRwp1laPYAIA0ZBFQzO/UyO7wx6Z8kDOstD19D5br\n Xn+WEn5I5HoX5ID5itQ1BDUk8LmXnk1BqVwhfq+gHaou5hg1h2mHIl+ws\n fec5SfP/r9ZWJgox1aMW00Mu+PMh6io7IbWLT1Ir9JN8Ww+u2IeF3jB5S\n 2zi1ei6Ds+xx+dcnNzjBFcoBNjLqeLKrR0GqLrmAsrmY/TQ1kVWxo405/ w==;", "X-IronPort-AV": [ "E=McAfee;i=\"6600,9927,10692\"; a=\"375324403\"", "E=Sophos;i=\"5.99,230,1677571200\"; d=\"scan'208\";a=\"375324403\"", "E=McAfee;i=\"6600,9927,10692\"; a=\"805845880\"", "E=Sophos;i=\"5.99,230,1677571200\"; d=\"scan'208\";a=\"805845880\"" ], "X-ExtLoop1": "1", "From": "Qiming Yang <qiming.yang@intel.com>", "To": "dev@dpdk.org", "Cc": "qi.z.zhang@intel.com, Qiming Yang <qiming.yang@intel.com>,\n Milena Olech <milena.olech@intel.com>", "Subject": "[PATCH 26/30] net/ice/base: remove bypass mode", "Date": "Thu, 27 Apr 2023 06:19:57 +0000", "Message-Id": "<20230427062001.478032-27-qiming.yang@intel.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20230427062001.478032-1-qiming.yang@intel.com>", "References": "<20230427062001.478032-1-qiming.yang@intel.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Previous implementation switches between bypass and Vernier mode\ndynamically. However bypass mode should be removed due to low\nprecision.\n\nSigned-off-by: Milena Olech <milena.olech@intel.com>\nSigned-off-by: Qiming Yang <qiming.yang@intel.com>\n---\n drivers/net/ice/base/ice_ptp_hw.c | 46 ++++++++++++++++++++++++++-----\n drivers/net/ice/base/ice_ptp_hw.h | 5 ++--\n drivers/net/ice/ice_ethdev.c | 2 +-\n 3 files changed, 43 insertions(+), 10 deletions(-)", "diff": "diff --git a/drivers/net/ice/base/ice_ptp_hw.c b/drivers/net/ice/base/ice_ptp_hw.c\nindex e559d4907f..f67e0b0c34 100644\n--- a/drivers/net/ice/base/ice_ptp_hw.c\n+++ b/drivers/net/ice/base/ice_ptp_hw.c\n@@ -2584,20 +2584,15 @@ ice_stop_phy_timer_e822(struct ice_hw *hw, u8 port, bool soft_reset)\n * ice_start_phy_timer_e822 - Start the PHY clock timer\n * @hw: pointer to the HW struct\n * @port: the PHY port to start\n- * @bypass: if true, start the PHY in bypass mode\n *\n * Start the clock of a PHY port. This must be done as part of the flow to\n * re-calibrate Tx and Rx timestamping offsets whenever the clock time is\n * initialized or when link speed changes.\n *\n- * Bypass mode enables timestamps immediately without waiting for Vernier\n- * calibration to complete. Hardware will still continue taking Vernier\n- * measurements on Tx or Rx of packets, but they will not be applied to\n- * timestamps. Use ice_phy_exit_bypass_e822 to exit bypass mode once hardware\n- * has completed offset calculation.\n+ * Hardware will take Vernier measurements on Tx or Rx of packets.\n */\n enum ice_status\n-ice_start_phy_timer_e822(struct ice_hw *hw, u8 port, bool bypass)\n+ice_start_phy_timer_e822(struct ice_hw *hw, u8 port)\n {\n \tenum ice_status status;\n \tu32 lo, hi, val;\n@@ -2721,6 +2716,43 @@ ice_get_phy_tx_tstamp_ready_e822(struct ice_hw *hw, u8 quad, u64 *tstamp_ready)\n \treturn ICE_SUCCESS;\n }\n \n+/**\n+ * ice_phy_cfg_intr_e822 - Configure TX timestamp interrupt\n+ * @hw: pointer to the HW struct\n+ * @quad: the timestamp quad\n+ * @ena: enable or disable interrupt\n+ * @threshold: interrupt threshold\n+ *\n+ * Configure TX timestamp interrupt for the specified quad\n+ */\n+\n+enum ice_status\n+ice_phy_cfg_intr_e822(struct ice_hw *hw, u8 quad, bool ena, u8 threshold)\n+{\n+\tenum ice_status err;\n+\tu32 val;\n+\n+\terr = ice_read_quad_reg_e822(hw, quad,\n+\t\t\t\t Q_REG_TX_MEM_GBL_CFG,\n+\t\t\t\t &val);\n+\tif (err)\n+\t\treturn err;\n+\n+\tif (ena) {\n+\t\tval |= Q_REG_TX_MEM_GBL_CFG_INTR_ENA_M;\n+\t\tval &= ~Q_REG_TX_MEM_GBL_CFG_INTR_THR_M;\n+\t\tval |= ((threshold << Q_REG_TX_MEM_GBL_CFG_INTR_THR_S) &\n+\t\t\tQ_REG_TX_MEM_GBL_CFG_INTR_THR_M);\n+\t} else {\n+\t\tval &= ~Q_REG_TX_MEM_GBL_CFG_INTR_ENA_M;\n+\t}\n+\n+\terr = ice_write_quad_reg_e822(hw, quad,\n+\t\t\t\t Q_REG_TX_MEM_GBL_CFG,\n+\t\t\t\t val);\n+\n+\treturn err;\n+}\n \n /* E810 functions\n *\ndiff --git a/drivers/net/ice/base/ice_ptp_hw.h b/drivers/net/ice/base/ice_ptp_hw.h\nindex 4d5d728e26..0a7c6d052c 100644\n--- a/drivers/net/ice/base/ice_ptp_hw.h\n+++ b/drivers/net/ice/base/ice_ptp_hw.h\n@@ -237,10 +237,11 @@ void ice_phy_cfg_lane_e822(struct ice_hw *hw, u8 port);\n enum ice_status\n ice_stop_phy_timer_e822(struct ice_hw *hw, u8 port, bool soft_reset);\n enum ice_status\n-ice_start_phy_timer_e822(struct ice_hw *hw, u8 port, bool bypass);\n+ice_start_phy_timer_e822(struct ice_hw *hw, u8 port);\n enum ice_status ice_phy_cfg_tx_offset_e822(struct ice_hw *hw, u8 port);\n enum ice_status ice_phy_cfg_rx_offset_e822(struct ice_hw *hw, u8 port);\n-enum ice_status ice_phy_exit_bypass_e822(struct ice_hw *hw, u8 port);\n+enum ice_status\n+ice_phy_cfg_intr_e822(struct ice_hw *hw, u8 quad, bool ena, u8 threshold);\n \n /* E810 family functions */\n bool ice_is_gps_present_e810t(struct ice_hw *hw);\ndiff --git a/drivers/net/ice/ice_ethdev.c b/drivers/net/ice/ice_ethdev.c\nindex 2a4073c4d1..8b41753b83 100644\n--- a/drivers/net/ice/ice_ethdev.c\n+++ b/drivers/net/ice/ice_ethdev.c\n@@ -2418,7 +2418,7 @@ ice_dev_init(struct rte_eth_dev *dev)\n \t\thw->phy_model = ICE_PHY_E822;\n \n \tif (hw->phy_model == ICE_PHY_E822) {\n-\t\tret = ice_start_phy_timer_e822(hw, hw->pf_id, true);\n+\t\tret = ice_start_phy_timer_e822(hw, hw->pf_id);\n \t\tif (ret)\n \t\t\tPMD_INIT_LOG(ERR, \"Failed to start phy timer\\n\");\n \t}\n", "prefixes": [ "26/30" ] }