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GET /api/patches/126590/?format=api
{ "id": 126590, "url": "http://patches.dpdk.org/api/patches/126590/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20230427062001.478032-24-qiming.yang@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20230427062001.478032-24-qiming.yang@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20230427062001.478032-24-qiming.yang@intel.com", "date": "2023-04-27T06:19:54", "name": "[23/30] net/ice/base: change method to get pca9575 handle", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "0e19b1c7e45ff400a8850fc5387d108afe40e4f5", "submitter": { "id": 522, "url": "http://patches.dpdk.org/api/people/522/?format=api", "name": "Qiming Yang", "email": "qiming.yang@intel.com" }, "delegate": { "id": 1540, "url": "http://patches.dpdk.org/api/users/1540/?format=api", "username": "qzhan15", "first_name": "Qi", "last_name": "Zhang", "email": "qi.z.zhang@intel.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20230427062001.478032-24-qiming.yang@intel.com/mbox/", "series": [ { "id": 27885, "url": "http://patches.dpdk.org/api/series/27885/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=27885", "date": "2023-04-27T06:19:31", "name": "net/ice/base: share code update", "version": 1, "mbox": "http://patches.dpdk.org/series/27885/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/126590/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/126590/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 85AA542A08;\n\tThu, 27 Apr 2023 08:40:28 +0200 (CEST)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 2DCCC42FD8;\n\tThu, 27 Apr 2023 08:38:28 +0200 (CEST)", "from mga01.intel.com (mga01.intel.com [192.55.52.88])\n by mails.dpdk.org (Postfix) with ESMTP id 878C742FDE\n for <dev@dpdk.org>; Thu, 27 Apr 2023 08:38:26 +0200 (CEST)", "from fmsmga002.fm.intel.com ([10.253.24.26])\n by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 26 Apr 2023 23:38:26 -0700", "from dpdk-qiming3.sh.intel.com ([10.67.111.4])\n by fmsmga002.fm.intel.com with ESMTP; 26 Apr 2023 23:38:23 -0700" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1682577506; x=1714113506;\n h=from:to:cc:subject:date:message-id:in-reply-to:\n references:mime-version:content-transfer-encoding;\n bh=vZ9ro9fQXZYR2KiMMVikLsShm4W8AQDL0FQ/tzd0psU=;\n b=HZayea0csAvFhtCRupgYT2WsNdLVmQXTgQbXdz+WIE88Yp1wPcxnoCwA\n OqtngIhjrktqw335TmXGFn1pke1HTVD/aMYhTb8cxPs6pQb5eXe4wR+z8\n XtC/4mRC5Rb0UXxzYoSOtxghRXuHBMskHWbZfVqjAptclF2L8hJLJTEUS\n wlFbcGipGS0SWG/UfpLZFYD71MMBzH0NcYoxQ52am0MEP0EvONcnwfgmn\n XVkPeyvy7HGJMQqE6nBmnHHCBsVt9dKv4+eF1wW5iRTDC6WvhiRGeil+U\n ODKQcsgJMh3G1EbDcjBw+8d4TQg/Wt/x7oGjfvSHdgxw0zUaAGEYO0MLC g==;", "X-IronPort-AV": [ "E=McAfee;i=\"6600,9927,10692\"; a=\"375324388\"", "E=Sophos;i=\"5.99,230,1677571200\"; d=\"scan'208\";a=\"375324388\"", "E=McAfee;i=\"6600,9927,10692\"; a=\"805845867\"", "E=Sophos;i=\"5.99,230,1677571200\"; d=\"scan'208\";a=\"805845867\"" ], "X-ExtLoop1": "1", "From": "Qiming Yang <qiming.yang@intel.com>", "To": "dev@dpdk.org", "Cc": "qi.z.zhang@intel.com, Qiming Yang <qiming.yang@intel.com>,\n Milena Olech <milena.olech@intel.com>", "Subject": "[PATCH 23/30] net/ice/base: change method to get pca9575 handle", "Date": "Thu, 27 Apr 2023 06:19:54 +0000", "Message-Id": "<20230427062001.478032-24-qiming.yang@intel.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20230427062001.478032-1-qiming.yang@intel.com>", "References": "<20230427062001.478032-1-qiming.yang@intel.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "More universal method for getting pca9575 handle is introduced.\nThe first step is to look for CLK_MUX handle. Having that it is\npossible to find CLK_MUX GPIO pin. Provided data let check what is\ndriving the pin - the expectation is that pca9575 node part number\nis returned.\n\nSigned-off-by: Milena Olech <milena.olech@intel.com>\nSigned-off-by: Qiming Yang <qiming.yang@intel.com>\n---\n drivers/net/ice/base/ice_adminq_cmd.h | 12 ++-\n drivers/net/ice/base/ice_ptp_hw.c | 125 ++++++++++++++++++++++----\n 2 files changed, 120 insertions(+), 17 deletions(-)", "diff": "diff --git a/drivers/net/ice/base/ice_adminq_cmd.h b/drivers/net/ice/base/ice_adminq_cmd.h\nindex c51054ecc1..29b123d900 100644\n--- a/drivers/net/ice/base/ice_adminq_cmd.h\n+++ b/drivers/net/ice/base/ice_adminq_cmd.h\n@@ -1723,6 +1723,8 @@ struct ice_aqc_link_topo_params {\n #define ICE_AQC_LINK_TOPO_NODE_TYPE_CAGE\t6\n #define ICE_AQC_LINK_TOPO_NODE_TYPE_MEZZ\t7\n #define ICE_AQC_LINK_TOPO_NODE_TYPE_ID_EEPROM\t8\n+#define ICE_AQC_LINK_TOPO_NODE_TYPE_CLK_CTRL\t9\n+#define ICE_AQC_LINK_TOPO_NODE_TYPE_CLK_MUX\t10\n #define ICE_AQC_LINK_TOPO_NODE_TYPE_GPS\t\t11\n #define ICE_AQC_LINK_TOPO_NODE_CTX_S\t\t4\n #define ICE_AQC_LINK_TOPO_NODE_CTX_M\t\t\\\n@@ -1760,8 +1762,13 @@ struct ice_aqc_link_topo_addr {\n struct ice_aqc_get_link_topo {\n \tstruct ice_aqc_link_topo_addr addr;\n \tu8 node_part_num;\n-#define ICE_ACQ_GET_LINK_TOPO_NODE_NR_PCA9575\t0x21\n-#define ICE_ACQ_GET_LINK_TOPO_NODE_NR_GEN_GPS\t0x48\n+#define ICE_ACQ_GET_LINK_TOPO_NODE_NR_PCA9575\t\t\t0x21\n+#define ICE_ACQ_GET_LINK_TOPO_NODE_NR_ZL30632_80032\t\t0x24\n+#define ICE_ACQ_GET_LINK_TOPO_NODE_NR_SI5383_5384\t\t0x25\n+#define ICE_ACQ_GET_LINK_TOPO_NODE_NR_E822_PHY\t\t\t0x30\n+#define ICE_ACQ_GET_LINK_TOPO_NODE_NR_C827\t\t\t0x31\n+#define ICE_ACQ_GET_LINK_TOPO_NODE_NR_GEN_CLK_MUX\t\t0x47\n+#define ICE_ACQ_GET_LINK_TOPO_NODE_NR_GEN_GPS\t\t\t0x48\n \tu8 rsvd[9];\n };\n \n@@ -1789,6 +1796,7 @@ struct ice_aqc_get_link_topo_pin {\n #define ICE_AQC_LINK_TOPO_IO_FUNC_RED_LED\t12\n #define ICE_AQC_LINK_TOPO_IO_FUNC_GREEN_LED\t13\n #define ICE_AQC_LINK_TOPO_IO_FUNC_BLUE_LED\t14\n+#define ICE_AQC_LINK_TOPO_IO_FUNC_CLK_IN\t20\n #define ICE_AQC_LINK_TOPO_INPUT_IO_TYPE_S\t5\n #define ICE_AQC_LINK_TOPO_INPUT_IO_TYPE_M\t\\\n \t\t\t(0x7 << ICE_AQC_LINK_TOPO_INPUT_IO_TYPE_S)\ndiff --git a/drivers/net/ice/base/ice_ptp_hw.c b/drivers/net/ice/base/ice_ptp_hw.c\nindex cc6c1f3152..29840b2b91 100644\n--- a/drivers/net/ice/base/ice_ptp_hw.c\n+++ b/drivers/net/ice/base/ice_ptp_hw.c\n@@ -1962,14 +1962,19 @@ ice_calc_fixed_tx_offset_e822(struct ice_hw *hw, enum ice_ptp_link_spd link_spd)\n * adjust Tx timestamps by. This is calculated by combining some known static\n * latency along with the Vernier offset computations done by hardware.\n *\n- * This function must be called only after the offset registers are valid,\n- * i.e. after the Vernier calibration wait has passed, to ensure that the PHY\n- * has measured the offset.\n+ * This function will not return successfully until the Tx offset calculations\n+ * have been completed, which requires waiting until at least one packet has\n+ * been transmitted by the device. It is safe to call this function\n+ * periodically until calibration succeeds, as it will only program the offset\n+ * once.\n *\n * To avoid overflow, when calculating the offset based on the known static\n * latency values, we use measurements in 1/100th of a nanosecond, and divide\n * the TUs per second up front. This avoids overflow while allowing\n * calculation of the adjustment using integer arithmetic.\n+ *\n+ * Returns zero on success, ICE_ERR_NOT_READY if the hardware vernier offset\n+ * calibration has not completed, or another error code on failure.\n */\n enum ice_status ice_phy_cfg_tx_offset_e822(struct ice_hw *hw, u8 port)\n {\n@@ -1977,6 +1982,28 @@ enum ice_status ice_phy_cfg_tx_offset_e822(struct ice_hw *hw, u8 port)\n \tenum ice_ptp_fec_mode fec_mode;\n \tenum ice_status status;\n \tu64 total_offset, val;\n+\tu32 reg;\n+\n+\t/* Nothing to do if we've already programmed the offset */\n+\tstatus = ice_read_phy_reg_e822(hw, port, P_REG_TX_OR, ®);\n+\tif (status) {\n+\t\tice_debug(hw, ICE_DBG_PTP, \"Failed to read TX_OR for port %u, status %d\\n\",\n+\t\t\t port, status);\n+\t\treturn status;\n+\t}\n+\n+\tif (reg)\n+\t\treturn ICE_SUCCESS;\n+\n+\tstatus = ice_read_phy_reg_e822(hw, port, P_REG_TX_OV_STATUS, ®);\n+\tif (status) {\n+\t\tice_debug(hw, ICE_DBG_PTP, \"Failed to read TX_OV_STATUS for port %u, status %d\\n\",\n+\t\t\t port, status);\n+\t\treturn status;\n+\t}\n+\n+\tif (!(reg & P_REG_TX_OV_STATUS_OV_M))\n+\t\treturn ICE_ERR_NOT_READY;\n \n \tstatus = ice_phy_get_speed_and_fec_e822(hw, port, &link_spd, &fec_mode);\n \tif (status)\n@@ -2030,6 +2057,7 @@ enum ice_status ice_phy_cfg_tx_offset_e822(struct ice_hw *hw, u8 port)\n \tif (status)\n \t\treturn status;\n \n+\tice_info(hw, \"Port=%d Tx vernier offset calibration complete\\n\", port);\n \n \treturn ICE_SUCCESS;\n }\n@@ -2236,6 +2264,11 @@ ice_calc_fixed_rx_offset_e822(struct ice_hw *hw, enum ice_ptp_link_spd link_spd)\n * measurements taken in hardware with some data about known fixed delay as\n * well as adjusting for multi-lane alignment delay.\n *\n+ * This function will not return successfully until the Rx offset calculations\n+ * have been completed, which requires waiting until at least one packet has\n+ * been received by the device. It is safe to call this function periodically\n+ * until calibration succeeds, as it will only program the offset once.\n+ *\n * This function must be called only after the offset registers are valid,\n * i.e. after the Vernier calibration wait has passed, to ensure that the PHY\n * has measured the offset.\n@@ -2244,6 +2277,9 @@ ice_calc_fixed_rx_offset_e822(struct ice_hw *hw, enum ice_ptp_link_spd link_spd)\n * latency values, we use measurements in 1/100th of a nanosecond, and divide\n * the TUs per second up front. This avoids overflow while allowing\n * calculation of the adjustment using integer arithmetic.\n+ *\n+ * Returns zero on success, ICE_ERR_NOT_READY if the hardware vernier offset\n+ * calibration has not completed, or another error code on failure.\n */\n enum ice_status ice_phy_cfg_rx_offset_e822(struct ice_hw *hw, u8 port)\n {\n@@ -2251,6 +2287,28 @@ enum ice_status ice_phy_cfg_rx_offset_e822(struct ice_hw *hw, u8 port)\n \tenum ice_ptp_fec_mode fec_mode;\n \tu64 total_offset, pmd, val;\n \tenum ice_status status;\n+\tu32 reg;\n+\n+\t/* Nothing to do if we've already programmed the offset */\n+\tstatus = ice_read_phy_reg_e822(hw, port, P_REG_RX_OR, ®);\n+\tif (status) {\n+\t\tice_debug(hw, ICE_DBG_PTP, \"Failed to read RX_OR for port %u, status %d\\n\",\n+\t\t\t port, status);\n+\t\treturn status;\n+\t}\n+\n+\tif (reg)\n+\t\treturn ICE_SUCCESS;\n+\n+\tstatus = ice_read_phy_reg_e822(hw, port, P_REG_RX_OV_STATUS, ®);\n+\tif (status) {\n+\t\tice_debug(hw, ICE_DBG_PTP, \"Failed to read RX_OV_STATUS for port %u, status %d\\n\",\n+\t\t\t port, status);\n+\t\treturn status;\n+\t}\n+\n+\tif (!(reg & P_REG_RX_OV_STATUS_OV_M))\n+\t\treturn ICE_ERR_NOT_READY;\n \n \tstatus = ice_phy_get_speed_and_fec_e822(hw, port, &link_spd, &fec_mode);\n \tif (status)\n@@ -2311,10 +2369,11 @@ enum ice_status ice_phy_cfg_rx_offset_e822(struct ice_hw *hw, u8 port)\n \tif (status)\n \t\treturn status;\n \n+\tice_info(hw, \"Port=%d Rx vernier offset calibration complete\\n\", port);\n+\n \treturn ICE_SUCCESS;\n }\n \n-\n /**\n * ice_ptp_clear_phy_offset_ready_e822 - Clear PHY TX_/RX_OFFSET_READY registers\n * @hw: pointer to the HW struct\n@@ -2424,7 +2483,8 @@ static enum ice_status ice_sync_phy_timer_e822(struct ice_hw *hw, u8 port)\n \t\treturn ICE_ERR_NOT_READY;\n \t}\n \n-\tstatus = ice_read_phy_and_phc_time_e822(hw, port, &phy_time, &phc_time);\n+\tstatus = ice_read_phy_and_phc_time_e822(hw, port, &phy_time,\n+\t\t\t\t\t\t&phc_time);\n \tif (status)\n \t\tgoto err_unlock;\n \n@@ -3175,17 +3235,18 @@ ice_get_phy_tx_tstamp_ready_e810(struct ice_hw *hw, u8 port, u64 *tstamp_ready)\n * @hw: pointer to the hw struct\n * @pca9575_handle: GPIO controller's handle\n *\n- * Find and return the GPIO controller's handle in the netlist.\n- * When found - the value will be cached in the hw structure and following calls\n- * will return cached value\n+ * Find and return the GPIO controller's handle by checking what drives clock\n+ * mux pin. When found - the value will be cached in the hw structure and\n+ * following calls will return cached value.\n */\n static enum ice_status\n ice_get_pca9575_handle(struct ice_hw *hw, u16 *pca9575_handle)\n {\n+\tu8 node_part_number, idx, node_type_ctx_clk_mux, node_part_num_clk_mux;\n+\tstruct ice_aqc_get_link_topo_pin cmd_pin;\n+\tu16 node_handle, clock_mux_handle;\n \tstruct ice_aqc_get_link_topo cmd;\n-\tu8 node_part_number, idx;\n \tenum ice_status status;\n-\tu16 node_handle;\n \n \tif (!hw || !pca9575_handle)\n \t\treturn ICE_ERR_PARAM;\n@@ -3197,11 +3258,46 @@ ice_get_pca9575_handle(struct ice_hw *hw, u16 *pca9575_handle)\n \t}\n \n \tmemset(&cmd, 0, sizeof(cmd));\n+\tmemset(&cmd_pin, 0, sizeof(cmd_pin));\n+\n+\tnode_type_ctx_clk_mux = (ICE_AQC_LINK_TOPO_NODE_TYPE_CLK_MUX <<\n+\t\t\t\t ICE_AQC_LINK_TOPO_NODE_TYPE_S);\n+\tnode_type_ctx_clk_mux |= (ICE_AQC_LINK_TOPO_NODE_CTX_GLOBAL <<\n+\t\t\t\t ICE_AQC_LINK_TOPO_NODE_CTX_S);\n+\tnode_part_num_clk_mux = ICE_ACQ_GET_LINK_TOPO_NODE_NR_GEN_CLK_MUX;\n \n-\t/* Set node type to GPIO controller */\n+\t/* Look for CLOCK MUX handle in the netlist */\n+\tstatus = ice_find_netlist_node(hw, node_type_ctx_clk_mux,\n+\t\t\t\t node_part_num_clk_mux,\n+\t\t\t\t &clock_mux_handle);\n+\tif (status)\n+\t\treturn ICE_ERR_NOT_SUPPORTED;\n+\n+\t/* Take CLOCK MUX GPIO pin */\n+\tcmd_pin.input_io_params = (ICE_AQC_LINK_TOPO_INPUT_IO_TYPE_GPIO <<\n+\t\t\t\t ICE_AQC_LINK_TOPO_INPUT_IO_TYPE_S);\n+\tcmd_pin.input_io_params |= (ICE_AQC_LINK_TOPO_IO_FUNC_CLK_IN <<\n+\t\t\t\t ICE_AQC_LINK_TOPO_INPUT_IO_FUNC_S);\n+\tcmd_pin.addr.handle = CPU_TO_LE16(clock_mux_handle);\n+\tcmd_pin.addr.topo_params.node_type_ctx =\n+\t\t(ICE_AQC_LINK_TOPO_NODE_TYPE_CLK_MUX <<\n+\t\t ICE_AQC_LINK_TOPO_NODE_TYPE_S);\n+\tcmd_pin.addr.topo_params.node_type_ctx |=\n+\t\t(ICE_AQC_LINK_TOPO_NODE_CTX_PROVIDED <<\n+\t\t ICE_AQC_LINK_TOPO_NODE_CTX_S);\n+\n+\tstatus = ice_aq_get_netlist_node_pin(hw, &cmd_pin, &node_handle);\n+\tif (status)\n+\t\treturn ICE_ERR_NOT_SUPPORTED;\n+\n+\t/* Check what is driving the pin */\n \tcmd.addr.topo_params.node_type_ctx =\n-\t\t(ICE_AQC_LINK_TOPO_NODE_TYPE_M &\n-\t\t ICE_AQC_LINK_TOPO_NODE_TYPE_GPIO_CTRL);\n+\t\t(ICE_AQC_LINK_TOPO_NODE_TYPE_GPIO_CTRL <<\n+\t\t ICE_AQC_LINK_TOPO_NODE_TYPE_S);\n+\tcmd.addr.topo_params.node_type_ctx |=\n+\t\t(ICE_AQC_LINK_TOPO_NODE_CTX_GLOBAL <<\n+\t\t ICE_AQC_LINK_TOPO_NODE_CTX_S);\n+\tcmd.addr.handle = CPU_TO_LE16(node_handle);\n \n #define SW_PCA9575_SFP_TOPO_IDX\t\t2\n #define SW_PCA9575_QSFP_TOPO_IDX\t1\n@@ -3215,13 +3311,12 @@ ice_get_pca9575_handle(struct ice_hw *hw, u16 *pca9575_handle)\n \t\treturn ICE_ERR_NOT_SUPPORTED;\n \n \tcmd.addr.topo_params.index = idx;\n-\n \tstatus = ice_aq_get_netlist_node(hw, &cmd, &node_part_number,\n \t\t\t\t\t &node_handle);\n \tif (status)\n \t\treturn ICE_ERR_NOT_SUPPORTED;\n \n-\t/* Verify if we found the right IO expander type */\n+\t/* Verify if PCA9575 drives the pin */\n \tif (node_part_number != ICE_ACQ_GET_LINK_TOPO_NODE_NR_PCA9575)\n \t\treturn ICE_ERR_NOT_SUPPORTED;\n \n", "prefixes": [ "23/30" ] }