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{
    "id": 126588,
    "url": "http://patches.dpdk.org/api/patches/126588/?format=api",
    "web_url": "http://patches.dpdk.org/project/dpdk/patch/20230427062001.478032-22-qiming.yang@intel.com/",
    "project": {
        "id": 1,
        "url": "http://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<20230427062001.478032-22-qiming.yang@intel.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/20230427062001.478032-22-qiming.yang@intel.com",
    "date": "2023-04-27T06:19:52",
    "name": "[21/30] net/ice/base: add PHY OFFSET READY register clear",
    "commit_ref": null,
    "pull_url": null,
    "state": "superseded",
    "archived": true,
    "hash": "21f02859a35d54430b0ec5925f319fd95576f23e",
    "submitter": {
        "id": 522,
        "url": "http://patches.dpdk.org/api/people/522/?format=api",
        "name": "Qiming Yang",
        "email": "qiming.yang@intel.com"
    },
    "delegate": {
        "id": 1540,
        "url": "http://patches.dpdk.org/api/users/1540/?format=api",
        "username": "qzhan15",
        "first_name": "Qi",
        "last_name": "Zhang",
        "email": "qi.z.zhang@intel.com"
    },
    "mbox": "http://patches.dpdk.org/project/dpdk/patch/20230427062001.478032-22-qiming.yang@intel.com/mbox/",
    "series": [
        {
            "id": 27885,
            "url": "http://patches.dpdk.org/api/series/27885/?format=api",
            "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=27885",
            "date": "2023-04-27T06:19:31",
            "name": "net/ice/base: share code update",
            "version": 1,
            "mbox": "http://patches.dpdk.org/series/27885/mbox/"
        }
    ],
    "comments": "http://patches.dpdk.org/api/patches/126588/comments/",
    "check": "success",
    "checks": "http://patches.dpdk.org/api/patches/126588/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
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            "E=McAfee;i=\"6600,9927,10692\"; a=\"375324374\"",
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        ],
        "X-ExtLoop1": "1",
        "From": "Qiming Yang <qiming.yang@intel.com>",
        "To": "dev@dpdk.org",
        "Cc": "qi.z.zhang@intel.com, Qiming Yang <qiming.yang@intel.com>,\n Karol Kolacinski <karol.kolacinski@intel.com>",
        "Subject": "[PATCH 21/30] net/ice/base: add PHY OFFSET READY register clear",
        "Date": "Thu, 27 Apr 2023 06:19:52 +0000",
        "Message-Id": "<20230427062001.478032-22-qiming.yang@intel.com>",
        "X-Mailer": "git-send-email 2.25.1",
        "In-Reply-To": "<20230427062001.478032-1-qiming.yang@intel.com>",
        "References": "<20230427062001.478032-1-qiming.yang@intel.com>",
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        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
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    },
    "content": "Add a possibility to mark all transmitted/received timestamps as invalid\nby clearing PHY OFFSET_READY registers.\n\nSigned-off-by: Karol Kolacinski <karol.kolacinski@intel.com>\nSigned-off-by: Qiming Yang <qiming.yang@intel.com>\n---\n drivers/net/ice/base/ice_adminq_cmd.h |   4 +\n drivers/net/ice/base/ice_ptp_hw.c     | 126 ++++++++------------------\n drivers/net/ice/base/ice_ptp_hw.h     |   1 +\n 3 files changed, 43 insertions(+), 88 deletions(-)",
    "diff": "diff --git a/drivers/net/ice/base/ice_adminq_cmd.h b/drivers/net/ice/base/ice_adminq_cmd.h\nindex cd4a6ffddf..c51054ecc1 100644\n--- a/drivers/net/ice/base/ice_adminq_cmd.h\n+++ b/drivers/net/ice/base/ice_adminq_cmd.h\n@@ -2897,6 +2897,10 @@ enum ice_aqc_driver_params {\n \tICE_AQC_DRIVER_PARAM_CLK_IDX_TMR0 = 0,\n \t/* OS clock index for PTP timer Domain 1 */\n \tICE_AQC_DRIVER_PARAM_CLK_IDX_TMR1,\n+\t/* Request ID to recalibrate PHC logic */\n+\tICE_AQC_DRIVER_PARAM_PHC_RECALC,\n+\t/* Indicates that PTP clock controller failed */\n+\tICE_AQC_DRIVER_PARAM_PTP_CC_FAILED,\n \n \t/* Add new parameters above */\n \tICE_AQC_DRIVER_PARAM_MAX = 16,\ndiff --git a/drivers/net/ice/base/ice_ptp_hw.c b/drivers/net/ice/base/ice_ptp_hw.c\nindex a638bb114c..f27131efcc 100644\n--- a/drivers/net/ice/base/ice_ptp_hw.c\n+++ b/drivers/net/ice/base/ice_ptp_hw.c\n@@ -2027,47 +2027,6 @@ enum ice_status ice_phy_cfg_tx_offset_e822(struct ice_hw *hw, u8 port)\n \treturn ICE_SUCCESS;\n }\n \n-/**\n- * ice_phy_cfg_fixed_tx_offset_e822 - Configure Tx offset for bypass mode\n- * @hw: pointer to the HW struct\n- * @port: the PHY port to configure\n- *\n- * Calculate and program the fixed Tx offset, and indicate that the offset is\n- * ready. This can be used when operating in bypass mode.\n- */\n-static enum ice_status\n-ice_phy_cfg_fixed_tx_offset_e822(struct ice_hw *hw, u8 port)\n-{\n-\tenum ice_ptp_link_spd link_spd;\n-\tenum ice_ptp_fec_mode fec_mode;\n-\tenum ice_status status;\n-\tu64 total_offset;\n-\n-\tstatus = ice_phy_get_speed_and_fec_e822(hw, port, &link_spd, &fec_mode);\n-\tif (status)\n-\t\treturn status;\n-\n-\ttotal_offset = ice_calc_fixed_tx_offset_e822(hw, link_spd);\n-\n-\t/* Program the fixed Tx offset into the P_REG_TOTAL_TX_OFFSET_L\n-\t * register, then indicate that the Tx offset is ready. After this,\n-\t * timestamps will be enabled.\n-\t *\n-\t * Note that this skips including the more precise offsets generated\n-\t * by the Vernier calibration.\n-\t */\n-\tstatus = ice_write_64b_phy_reg_e822(hw, port, P_REG_TOTAL_TX_OFFSET_L,\n-\t\t\t\t\t    total_offset);\n-\tif (status)\n-\t\treturn status;\n-\n-\tstatus = ice_write_phy_reg_e822(hw, port, P_REG_TX_OR, 1);\n-\tif (status)\n-\t\treturn status;\n-\n-\treturn ICE_SUCCESS;\n-}\n-\n /**\n  * ice_phy_calc_pmd_adj_e822 - Calculate PMD adjustment for Rx\n  * @hw: pointer to the HW struct\n@@ -2348,43 +2307,33 @@ enum ice_status ice_phy_cfg_rx_offset_e822(struct ice_hw *hw, u8 port)\n \treturn ICE_SUCCESS;\n }\n \n+\n /**\n- * ice_phy_cfg_fixed_rx_offset_e822 - Configure fixed Rx offset for bypass mode\n+ * ice_ptp_clear_phy_offset_ready_e822 - Clear PHY TX_/RX_OFFSET_READY registers\n  * @hw: pointer to the HW struct\n- * @port: the PHY port to configure\n  *\n- * Calculate and program the fixed Rx offset, and indicate that the offset is\n- * ready. This can be used when operating in bypass mode.\n+ * Clear PHY TX_/RX_OFFSET_READY registers, effectively marking all transmitted\n+ * and received timestamps as invalid.\n  */\n-static enum ice_status\n-ice_phy_cfg_fixed_rx_offset_e822(struct ice_hw *hw, u8 port)\n+static enum ice_status ice_ptp_clear_phy_offset_ready_e822(struct ice_hw *hw)\n {\n-\tenum ice_ptp_link_spd link_spd;\n-\tenum ice_ptp_fec_mode fec_mode;\n-\tenum ice_status status;\n-\tu64 total_offset;\n-\n-\tstatus = ice_phy_get_speed_and_fec_e822(hw, port, &link_spd, &fec_mode);\n-\tif (status)\n-\t\treturn status;\n+\tu8 port;\n \n-\ttotal_offset = ice_calc_fixed_rx_offset_e822(hw, link_spd);\n+\tfor (port = 0; port < hw->phy_ports; port++) {\n+\t\tenum ice_status status;\n \n-\t/* Program the fixed Rx offset into the P_REG_TOTAL_RX_OFFSET_L\n-\t * register, then indicate that the Rx offset is ready. After this,\n-\t * timestamps will be enabled.\n-\t *\n-\t * Note that this skips including the more precise offsets generated\n-\t * by Vernier calibration.\n-\t */\n-\tstatus = ice_write_64b_phy_reg_e822(hw, port, P_REG_TOTAL_RX_OFFSET_L,\n-\t\t\t\t\t    total_offset);\n-\tif (status)\n-\t\treturn status;\n+\t\tstatus = ice_write_phy_reg_e822(hw, port, P_REG_TX_OR, 0);\n+\t\tif (status) {\n+\t\t\tice_warn(hw, \"Failed to clear PHY TX_OFFSET_READY register\\n\");\n+\t\t\treturn status;\n+\t\t}\n \n-\tstatus = ice_write_phy_reg_e822(hw, port, P_REG_RX_OR, 1);\n-\tif (status)\n-\t\treturn status;\n+\t\tstatus = ice_write_phy_reg_e822(hw, port, P_REG_RX_OR, 0);\n+\t\tif (status) {\n+\t\t\tice_warn(hw, \"Failed to clear PHY RX_OFFSET_READY register\\n\");\n+\t\t\treturn status;\n+\t\t}\n+\t}\n \n \treturn ICE_SUCCESS;\n }\n@@ -2666,24 +2615,6 @@ ice_start_phy_timer_e822(struct ice_hw *hw, u8 port, bool bypass)\n \tif (status)\n \t\treturn status;\n \n-\tif (bypass) {\n-\t\tval |= P_REG_PS_BYPASS_MODE_M;\n-\t\t/* Enter BYPASS mode, enabling timestamps immediately. */\n-\t\tstatus = ice_write_phy_reg_e822(hw, port, P_REG_PS, val);\n-\t\tif (status)\n-\t\t\treturn status;\n-\n-\t\t/* Program the fixed Tx offset */\n-\t\tstatus = ice_phy_cfg_fixed_tx_offset_e822(hw, port);\n-\t\tif (status)\n-\t\t\treturn status;\n-\n-\t\t/* Program the fixed Rx offset */\n-\t\tstatus = ice_phy_cfg_fixed_rx_offset_e822(hw, port);\n-\t\tif (status)\n-\t\t\treturn status;\n-\t}\n-\n \tice_debug(hw, ICE_DBG_PTP, \"Enabled clock on PHY port %u\\n\", port);\n \n \treturn ICE_SUCCESS;\n@@ -3841,6 +3772,25 @@ ice_ptp_adj_clock_at_time(struct ice_hw *hw, u64 at_time, s32 adj)\n \treturn ice_ptp_tmr_cmd(hw, ICE_PTP_ADJ_TIME_AT_TIME, true);\n }\n \n+/**\n+ * ice_ptp_clear_phy_offset_ready - Clear PHY TX_/RX_OFFSET_READY registers\n+ * @hw: pointer to the HW struct\n+ *\n+ * Clear PHY TX_/RX_OFFSET_READY registers, effectively marking all transmitted\n+ * and received timestamps as invalid.\n+ */\n+enum ice_status ice_ptp_clear_phy_offset_ready(struct ice_hw *hw)\n+{\n+\tswitch (hw->phy_model) {\n+\tcase ICE_PHY_E810:\n+\t\treturn ICE_SUCCESS;\n+\tcase ICE_PHY_E822:\n+\t\treturn ice_ptp_clear_phy_offset_ready_e822(hw);\n+\tdefault:\n+\t\treturn ICE_ERR_NOT_SUPPORTED;\n+\t}\n+}\n+\n /**\n  * ice_read_phy_tstamp - Read a PHY timestamp from the timestamp block\n  * @hw: pointer to the HW struct\ndiff --git a/drivers/net/ice/base/ice_ptp_hw.h b/drivers/net/ice/base/ice_ptp_hw.h\nindex e25018a68f..f4d64ea02b 100644\n--- a/drivers/net/ice/base/ice_ptp_hw.h\n+++ b/drivers/net/ice/base/ice_ptp_hw.h\n@@ -151,6 +151,7 @@ enum ice_status ice_ptp_write_incval_locked(struct ice_hw *hw, u64 incval,\n enum ice_status ice_ptp_adj_clock(struct ice_hw *hw, s32 adj, bool lock_sbq);\n enum ice_status\n ice_ptp_adj_clock_at_time(struct ice_hw *hw, u64 at_time, s32 adj);\n+enum ice_status ice_ptp_clear_phy_offset_ready(struct ice_hw *hw);\n enum ice_status\n ice_read_phy_tstamp(struct ice_hw *hw, u8 block, u8 idx, u64 *tstamp);\n enum ice_status\n",
    "prefixes": [
        "21/30"
    ]
}