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{
    "id": 126576,
    "url": "http://patches.dpdk.org/api/patches/126576/?format=api",
    "web_url": "http://patches.dpdk.org/project/dpdk/patch/20230427062001.478032-10-qiming.yang@intel.com/",
    "project": {
        "id": 1,
        "url": "http://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<20230427062001.478032-10-qiming.yang@intel.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/20230427062001.478032-10-qiming.yang@intel.com",
    "date": "2023-04-27T06:19:40",
    "name": "[09/30] net/ice/base: add pre-allocate memory argument",
    "commit_ref": null,
    "pull_url": null,
    "state": "superseded",
    "archived": true,
    "hash": "e500360a03ea9f49334b50890f8fec67e9add397",
    "submitter": {
        "id": 522,
        "url": "http://patches.dpdk.org/api/people/522/?format=api",
        "name": "Qiming Yang",
        "email": "qiming.yang@intel.com"
    },
    "delegate": {
        "id": 1540,
        "url": "http://patches.dpdk.org/api/users/1540/?format=api",
        "username": "qzhan15",
        "first_name": "Qi",
        "last_name": "Zhang",
        "email": "qi.z.zhang@intel.com"
    },
    "mbox": "http://patches.dpdk.org/project/dpdk/patch/20230427062001.478032-10-qiming.yang@intel.com/mbox/",
    "series": [
        {
            "id": 27885,
            "url": "http://patches.dpdk.org/api/series/27885/?format=api",
            "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=27885",
            "date": "2023-04-27T06:19:31",
            "name": "net/ice/base: share code update",
            "version": 1,
            "mbox": "http://patches.dpdk.org/series/27885/mbox/"
        }
    ],
    "comments": "http://patches.dpdk.org/api/patches/126576/comments/",
    "check": "warning",
    "checks": "http://patches.dpdk.org/api/patches/126576/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
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        "X-IronPort-AV": [
            "E=McAfee;i=\"6600,9927,10692\"; a=\"375324300\"",
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            "E=Sophos;i=\"5.99,230,1677571200\"; d=\"scan'208\";a=\"805845712\""
        ],
        "X-ExtLoop1": "1",
        "From": "Qiming Yang <qiming.yang@intel.com>",
        "To": "dev@dpdk.org",
        "Cc": "qi.z.zhang@intel.com, Qiming Yang <qiming.yang@intel.com>,\n Michal Wilczynski <michal.wilczynski@intel.com>",
        "Subject": "[PATCH 09/30] net/ice/base: add pre-allocate memory argument",
        "Date": "Thu, 27 Apr 2023 06:19:40 +0000",
        "Message-Id": "<20230427062001.478032-10-qiming.yang@intel.com>",
        "X-Mailer": "git-send-email 2.25.1",
        "In-Reply-To": "<20230427062001.478032-1-qiming.yang@intel.com>",
        "References": "<20230427062001.478032-1-qiming.yang@intel.com>",
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        "Content-Transfer-Encoding": "8bit",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.29",
        "Precedence": "list",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
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        "Errors-To": "dev-bounces@dpdk.org"
    },
    "content": "Add an option to pre-allocate memory for ice_sched_node struct. Add\nnew arguments to ice_sched_add() and ice_sched_add_elems() that allow\nfor pre-allocation of memory for ice_sched_node struct\n\nSigned-off-by: Michal Wilczynski <michal.wilczynski@intel.com>\nSigned-off-by: Qiming Yang <qiming.yang@intel.com>\n---\n drivers/net/ice/base/ice_adminq_cmd.h |   4 +-\n drivers/net/ice/base/ice_common.c     |   2 +-\n drivers/net/ice/base/ice_dcb.c        |   4 +-\n drivers/net/ice/base/ice_sched.c      | 411 ++++++++++++++++++++++++--\n drivers/net/ice/base/ice_sched.h      |  71 ++++-\n drivers/net/ice/base/ice_type.h       |   3 +\n 6 files changed, 466 insertions(+), 29 deletions(-)",
    "diff": "diff --git a/drivers/net/ice/base/ice_adminq_cmd.h b/drivers/net/ice/base/ice_adminq_cmd.h\nindex 5a44ebbdc0..cd4a6ffddf 100644\n--- a/drivers/net/ice/base/ice_adminq_cmd.h\n+++ b/drivers/net/ice/base/ice_adminq_cmd.h\n@@ -1120,9 +1120,9 @@ struct ice_aqc_txsched_elem {\n \tu8 generic;\n #define ICE_AQC_ELEM_GENERIC_MODE_M\t\t0x1\n #define ICE_AQC_ELEM_GENERIC_PRIO_S\t\t0x1\n-#define ICE_AQC_ELEM_GENERIC_PRIO_M\t(0x7 << ICE_AQC_ELEM_GENERIC_PRIO_S)\n+#define ICE_AQC_ELEM_GENERIC_PRIO_M\t\t(0x7 << ICE_AQC_ELEM_GENERIC_PRIO_S)\n #define ICE_AQC_ELEM_GENERIC_SP_S\t\t0x4\n-#define ICE_AQC_ELEM_GENERIC_SP_M\t(0x1 << ICE_AQC_ELEM_GENERIC_SP_S)\n+#define ICE_AQC_ELEM_GENERIC_SP_M\t\t(0x1 << ICE_AQC_ELEM_GENERIC_SP_S)\n #define ICE_AQC_ELEM_GENERIC_ADJUST_VAL_S\t0x5\n #define ICE_AQC_ELEM_GENERIC_ADJUST_VAL_M\t\\\n \t(0x3 << ICE_AQC_ELEM_GENERIC_ADJUST_VAL_S)\ndiff --git a/drivers/net/ice/base/ice_common.c b/drivers/net/ice/base/ice_common.c\nindex ed811e406d..984830ea37 100644\n--- a/drivers/net/ice/base/ice_common.c\n+++ b/drivers/net/ice/base/ice_common.c\n@@ -5129,7 +5129,7 @@ ice_ena_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u16 q_handle,\n \tq_ctx->q_teid = LE32_TO_CPU(node.node_teid);\n \n \t/* add a leaf node into scheduler tree queue layer */\n-\tstatus = ice_sched_add_node(pi, hw->num_tx_sched_layers - 1, &node);\n+\tstatus = ice_sched_add_node(pi, hw->num_tx_sched_layers - 1, &node, NULL);\n \tif (!status)\n \t\tstatus = ice_sched_replay_q_bw(pi, q_ctx);\n \ndiff --git a/drivers/net/ice/base/ice_dcb.c b/drivers/net/ice/base/ice_dcb.c\nindex 2a308b02bf..ca418090bc 100644\n--- a/drivers/net/ice/base/ice_dcb.c\n+++ b/drivers/net/ice/base/ice_dcb.c\n@@ -1370,7 +1370,7 @@ ice_add_dscp_tc_bw_tlv(struct ice_lldp_org_tlv *tlv,\n \t\t\t   ICE_DSCP_SUBTYPE_TCBW);\n \ttlv->ouisubtype = HTONL(ouisubtype);\n \n-\t/* First Octet after subtype\n+\t/* First Octect after subtype\n \t * ----------------------------\n \t * | RSV | CBS | RSV | Max TCs |\n \t * | 1b  | 1b  | 3b  | 3b      |\n@@ -1624,7 +1624,7 @@ ice_update_port_tc_tree_cfg(struct ice_port_info *pi,\n \t\t/* new TC */\n \t\tstatus = ice_sched_query_elem(pi->hw, teid2, &elem);\n \t\tif (!status)\n-\t\t\tstatus = ice_sched_add_node(pi, 1, &elem);\n+\t\t\tstatus = ice_sched_add_node(pi, 1, &elem, NULL);\n \t\tif (status)\n \t\t\tbreak;\n \t\t/* update the TC number */\ndiff --git a/drivers/net/ice/base/ice_sched.c b/drivers/net/ice/base/ice_sched.c\nindex e3a638dcdd..421a0085d6 100644\n--- a/drivers/net/ice/base/ice_sched.c\n+++ b/drivers/net/ice/base/ice_sched.c\n@@ -143,12 +143,14 @@ ice_aq_query_sched_elems(struct ice_hw *hw, u16 elems_req,\n  * @pi: port information structure\n  * @layer: Scheduler layer of the node\n  * @info: Scheduler element information from firmware\n+ * @prealloc_node: preallocated ice_sched_node struct for SW DB\n  *\n  * This function inserts a scheduler node to the SW DB.\n  */\n enum ice_status\n ice_sched_add_node(struct ice_port_info *pi, u8 layer,\n-\t\t   struct ice_aqc_txsched_elem_data *info)\n+\t\t   struct ice_aqc_txsched_elem_data *info,\n+\t\t   struct ice_sched_node *prealloc_node)\n {\n \tstruct ice_aqc_txsched_elem_data elem;\n \tstruct ice_sched_node *parent;\n@@ -176,7 +178,11 @@ ice_sched_add_node(struct ice_port_info *pi, u8 layer,\n \tstatus = ice_sched_query_elem(hw, LE32_TO_CPU(info->node_teid), &elem);\n \tif (status)\n \t\treturn status;\n-\tnode = (struct ice_sched_node *)ice_malloc(hw, sizeof(*node));\n+\n+\tif (prealloc_node)\n+\t\tnode = prealloc_node;\n+\telse\n+\t\tnode = (struct ice_sched_node *)ice_malloc(hw, sizeof(*node));\n \tif (!node)\n \t\treturn ICE_ERR_NO_MEMORY;\n \tif (hw->max_children[layer]) {\n@@ -901,13 +907,15 @@ ice_aq_cfg_l2_node_cgd(struct ice_hw *hw, u16 num_l2_nodes,\n  * @num_nodes: number of nodes\n  * @num_nodes_added: pointer to num nodes added\n  * @first_node_teid: if new nodes are added then return the TEID of first node\n+ * @prealloc_nodes: preallocated nodes struct for software DB\n  *\n  * This function add nodes to HW as well as to SW DB for a given layer\n  */\n-static enum ice_status\n+enum ice_status\n ice_sched_add_elems(struct ice_port_info *pi, struct ice_sched_node *tc_node,\n \t\t    struct ice_sched_node *parent, u8 layer, u16 num_nodes,\n-\t\t    u16 *num_nodes_added, u32 *first_node_teid)\n+\t\t    u16 *num_nodes_added, u32 *first_node_teid,\n+\t\t    struct ice_sched_node **prealloc_nodes)\n {\n \tstruct ice_sched_node *prev, *new_node;\n \tstruct ice_aqc_add_elem *buf;\n@@ -953,7 +961,11 @@ ice_sched_add_elems(struct ice_port_info *pi, struct ice_sched_node *tc_node,\n \t*num_nodes_added = num_nodes;\n \t/* add nodes to the SW DB */\n \tfor (i = 0; i < num_nodes; i++) {\n-\t\tstatus = ice_sched_add_node(pi, layer, &buf->generic[i]);\n+\t\tif (prealloc_nodes)\n+\t\t\tstatus = ice_sched_add_node(pi, layer, &buf->generic[i], prealloc_nodes[i]);\n+\t\telse\n+\t\t\tstatus = ice_sched_add_node(pi, layer, &buf->generic[i], NULL);\n+\n \t\tif (status != ICE_SUCCESS) {\n \t\t\tice_debug(hw, ICE_DBG_SCHED, \"add nodes in SW DB failed status =%d\\n\",\n \t\t\t\t  status);\n@@ -1032,7 +1044,7 @@ ice_sched_add_nodes_to_hw_layer(struct ice_port_info *pi,\n \t}\n \n \treturn ice_sched_add_elems(pi, tc_node, parent, layer, num_nodes,\n-\t\t\t\t   num_nodes_added, first_node_teid);\n+\t\t\t\t   num_nodes_added, first_node_teid, NULL);\n }\n \n /**\n@@ -1156,6 +1168,240 @@ static u8 ice_sched_get_agg_layer(struct ice_hw *hw)\n \treturn hw->sw_entry_point_layer;\n }\n \n+/**\n+ * ice_sched_set_l2_node_aq_elem - AQ element setup for L2 node creation\n+ * @pi: port information structure\n+ * @elem: admin queue command element\n+ *\n+ * Setup Admin Queue Command element to default values for L2 Tx node creation\n+ */\n+static enum ice_status\n+ice_sched_set_l2_node_aq_elem(struct ice_port_info *pi,\n+\t\t\t      struct ice_aqc_txsched_elem_data *elem)\n+{\n+\tif (!pi || !pi->root || !elem)\n+\t\treturn ICE_ERR_PARAM;\n+\n+\telem->parent_teid = pi->root->info.node_teid;\n+\telem->data.elem_type = ICE_AQC_ELEM_TYPE_TC;\n+\telem->data.valid_sections =\n+\t\tICE_AQC_ELEM_VALID_GENERIC | ICE_AQC_ELEM_VALID_CIR |\n+\t\tICE_AQC_ELEM_VALID_EIR;\n+\telem->data.generic = 0;\n+\telem->data.cir_bw.bw_profile_idx =\n+\t\tCPU_TO_LE16(ICE_SCHED_DFLT_RL_PROF_ID);\n+\telem->data.cir_bw.bw_alloc =\n+\t\tCPU_TO_LE16(ICE_SCHED_DFLT_BW_WT);\n+\telem->data.eir_bw.bw_profile_idx =\n+\t\tCPU_TO_LE16(ICE_SCHED_DFLT_RL_PROF_ID);\n+\telem->data.eir_bw.bw_alloc =\n+\t\tCPU_TO_LE16(ICE_SCHED_DFLT_BW_WT);\n+\n+\treturn ICE_SUCCESS;\n+}\n+\n+/**\n+ * ice_sched_add_dflt_l2_nodes - add default L2 TC nodes into Tx tree\n+ * @pi: port information structure\n+ *\n+ * Function creates default L2 nodes configuration. FW provide TC0 node,\n+ * here remaining TCs are added.\n+ */\n+enum ice_status ice_sched_add_dflt_l2_nodes(struct ice_port_info *pi)\n+{\n+\t/* One node is already created by FW */\n+\tconst u16 num_nodes = ICE_MAX_CGD_PER_PORT - 1;\n+\tu16 i, buf_size, num_groups_added;\n+\tstruct ice_aqc_add_elem *buf;\n+\tstruct ice_sched_node *node;\n+\tenum ice_status status;\n+\tstruct ice_hw *hw;\n+\tu32 teid;\n+\n+\tif (!pi || !pi->root)\n+\t\treturn ICE_ERR_PARAM;\n+\n+\thw = pi->hw;\n+\n+\tbuf_size = ice_struct_size(buf, generic, num_nodes);\n+\tbuf = (struct ice_aqc_add_elem *)ice_malloc(hw, buf_size);\n+\tif (!buf)\n+\t\treturn ICE_ERR_NO_MEMORY;\n+\n+\tice_acquire_lock(&pi->sched_lock);\n+\n+\tbuf->hdr.parent_teid = pi->root->info.node_teid;\n+\tbuf->hdr.num_elems = CPU_TO_LE16(num_nodes);\n+\n+\tfor (i = 0; i < num_nodes; i++) {\n+\t\tstatus = ice_sched_set_l2_node_aq_elem(pi, &buf->generic[i]);\n+\t\tif (status)\n+\t\t\tgoto exit_add_dflt_l2_nodes;\n+\t}\n+\n+\tstatus = ice_aq_add_sched_elems(hw, 1, buf, buf_size,\n+\t\t\t\t\t&num_groups_added, NULL);\n+\tif (status != ICE_SUCCESS || num_groups_added != 1) {\n+\t\tice_debug(hw, ICE_DBG_SCHED, \"add node failed FW Error %d\\n\",\n+\t\t\t  hw->adminq.sq_last_status);\n+\t\tstatus = ICE_ERR_CFG;\n+\t\tgoto exit_add_dflt_l2_nodes;\n+\t}\n+\n+\tfor (i = 0; i < num_nodes; i++) {\n+\t\tstatus = ice_sched_add_node(pi, 1, &buf->generic[i], NULL);\n+\t\tif (status != ICE_SUCCESS) {\n+\t\t\tice_debug(hw, ICE_DBG_SCHED, \"add nodes in SW DB failed status =%d\\n\",\n+\t\t\t\t  status);\n+\t\t\tbreak;\n+\t\t}\n+\n+\t\tteid = LE32_TO_CPU(buf->generic[i].node_teid);\n+\t\tnode = ice_sched_find_node_by_teid(pi->root, teid);\n+\t\tif (!node) {\n+\t\t\tice_debug(hw, ICE_DBG_SCHED, \"Node is missing for teid =%d\\n\", teid);\n+\t\t\tbreak;\n+\t\t}\n+\t\tnode->sibling = NULL;\n+\t\tnode->tc_num = i + 1;\n+\t}\n+\n+exit_add_dflt_l2_nodes:\n+\tice_release_lock(&pi->sched_lock);\n+\tice_free(hw, buf);\n+\treturn status;\n+}\n+\n+/**\n+ * ice_sched_clear_l2_nodes - remove all L2 TC nodes from port except for default TC0\n+ * @pi: port information structure\n+ *\n+ * Remove non-default L2 nodes configuration created by SW leaving only one TC0 L2 default node\n+ */\n+enum ice_status ice_sched_clear_l2_nodes(struct ice_port_info *pi)\n+{\n+\tenum ice_status status = ICE_SUCCESS;\n+\tu32 teid;\n+\tu8 i;\n+\n+\tif (!pi || !pi->root)\n+\t\treturn ICE_ERR_PARAM;\n+\n+\tice_acquire_lock(&pi->sched_lock);\n+\n+\t/* iterate backwards and do not remove child at index 0 */\n+\tfor (i = pi->root->num_children - 1; i; i--) {\n+\t\tstruct ice_sched_node *node = pi->root->children[i];\n+\n+\t\tteid = LE32_TO_CPU(node->info.node_teid);\n+\t\tice_free_sched_node(pi, node);\n+\t\t/* ice_free_sched_node does not remove L2 nodes from HW, removing explicitly */\n+\t\tstatus = ice_sched_remove_elems(pi->hw, pi->root, 1, &teid);\n+\t\tif (status)\n+\t\t\tbreak;\n+\t}\n+\n+\tice_release_lock(&pi->sched_lock);\n+\treturn status;\n+}\n+\n+/**\n+ * ice_sched_set_dflt_cgd_to_tc_map - setup default CGD to TC mapping\n+ * @pi: port information structure\n+ *\n+ * Function creates default CGD to L2 nodes mapping\n+ */\n+enum ice_status ice_sched_set_dflt_cgd_to_tc_map(struct ice_port_info *pi)\n+{\n+\tstruct ice_aqc_cfg_l2_node_cgd_elem *buf;\n+\tstruct ice_sched_node *root;\n+\tenum ice_status status;\n+\tu16 i, buf_size;\n+\tu8 cgd;\n+\n+\tif (!pi || !pi->root)\n+\t\treturn ICE_ERR_PARAM;\n+\n+\tbuf_size = sizeof(*buf) * ICE_MAX_CGD_PER_PORT;\n+\tbuf = (struct ice_aqc_cfg_l2_node_cgd_elem *)\n+\t\tice_malloc(pi->hw, buf_size);\n+\tif (!buf)\n+\t\treturn ICE_ERR_NO_MEMORY;\n+\n+\tice_acquire_lock(&pi->sched_lock);\n+\troot = pi->root;\n+\n+\tfor (i = 0; i < root->num_children; i++) {\n+\t\tbuf[i].node_teid = root->children[i]->info.node_teid;\n+\t\tcgd = i + pi->lport * ICE_MAX_CGD_PER_PORT;\n+\t\tbuf[i].cgd = cgd;\n+\t\troot->children[i]->cgd = cgd;\n+\t}\n+\n+\tstatus = ice_aq_cfg_l2_node_cgd(pi->hw, root->num_children, buf,\n+\t\t\t\t\tbuf_size, NULL);\n+\n+\tice_release_lock(&pi->sched_lock);\n+\tice_free(pi->hw, buf);\n+\treturn status;\n+}\n+\n+/**\n+ * ice_sched_copy_cgd - copy congestion domain mapping between ports\n+ * @src: pointer to source port_info struct\n+ * @dst: pointer to destination port_info struct\n+ * @num_cgd: CGD count\n+ *\n+ * Copy first num_cgd congestion domain to TC node mappings from src port to dst port.\n+ * Src port mapping does not change.\n+ */\n+enum ice_status\n+ice_sched_copy_cgd(struct ice_port_info *src, struct ice_port_info *dst, u8 num_cgd)\n+{\n+\tstruct ice_aqc_cfg_l2_node_cgd_elem *buf = NULL;\n+\tenum ice_status status;\n+\tu16 buf_size;\n+\tu8 cgd, i;\n+\n+\tif (!src || !dst || !num_cgd)\n+\t\treturn ICE_ERR_PARAM;\n+\n+\tice_acquire_lock(&src->sched_lock);\n+\tice_acquire_lock(&dst->sched_lock);\n+\n+\tif (!src->root || src->root->num_children < num_cgd ||\n+\t    !dst->root || dst->root->num_children < num_cgd) {\n+\t\tstatus =  ICE_ERR_PARAM;\n+\t\tgoto err_copy_cgd;\n+\t}\n+\n+\tbuf_size = sizeof(*buf) * num_cgd;\n+\tbuf = (struct ice_aqc_cfg_l2_node_cgd_elem *)ice_malloc(src->hw, buf_size);\n+\n+\tif (!buf) {\n+\t\tstatus = ICE_ERR_NO_MEMORY;\n+\t\tgoto err_copy_cgd;\n+\t}\n+\n+\tfor (i = 0; i < num_cgd; i++) {\n+\t\tbuf[i].node_teid = dst->root->children[i]->info.node_teid;\n+\t\tcgd = src->root->children[i]->cgd;\n+\t\tbuf[i].cgd = cgd;\n+\t\tdst->root->children[i]->cgd = cgd;\n+\t}\n+\n+\tstatus = ice_aq_cfg_l2_node_cgd(src->hw, num_cgd, buf, buf_size, NULL);\n+\n+err_copy_cgd:\n+\tice_release_lock(&dst->sched_lock);\n+\tice_release_lock(&src->sched_lock);\n+\n+\tif (buf)\n+\t\tice_free(src->hw, buf);\n+\n+\treturn status;\n+}\n+\n /**\n  * ice_rm_dflt_leaf_node - remove the default leaf node in the tree\n  * @pi: port information structure\n@@ -1292,7 +1538,7 @@ enum ice_status ice_sched_init_port(struct ice_port_info *pi)\n \t\t\t    ICE_AQC_ELEM_TYPE_ENTRY_POINT)\n \t\t\t\thw->sw_entry_point_layer = j;\n \n-\t\t\tstatus = ice_sched_add_node(pi, j, &buf[i].generic[j]);\n+\t\t\tstatus = ice_sched_add_node(pi, j, &buf[i].generic[j], NULL);\n \t\t\tif (status)\n \t\t\t\tgoto err_init_port;\n \t\t}\n@@ -1417,11 +1663,6 @@ void ice_sched_get_psm_clk_freq(struct ice_hw *hw)\n \tclk_src = (val & GLGEN_CLKSTAT_SRC_PSM_CLK_SRC_M) >>\n \t\tGLGEN_CLKSTAT_SRC_PSM_CLK_SRC_S;\n \n-#define PSM_CLK_SRC_367_MHZ 0x0\n-#define PSM_CLK_SRC_416_MHZ 0x1\n-#define PSM_CLK_SRC_446_MHZ 0x2\n-#define PSM_CLK_SRC_390_MHZ 0x3\n-\n \tswitch (clk_src) {\n \tcase PSM_CLK_SRC_367_MHZ:\n \t\thw->psm_clk_freq = ICE_PSM_CLK_367MHZ_IN_HZ;\n@@ -1435,11 +1676,12 @@ void ice_sched_get_psm_clk_freq(struct ice_hw *hw)\n \tcase PSM_CLK_SRC_390_MHZ:\n \t\thw->psm_clk_freq = ICE_PSM_CLK_390MHZ_IN_HZ;\n \t\tbreak;\n-\tdefault:\n-\t\tice_debug(hw, ICE_DBG_SCHED, \"PSM clk_src unexpected %u\\n\",\n-\t\t\t  clk_src);\n-\t\t/* fall back to a safe default */\n-\t\thw->psm_clk_freq = ICE_PSM_CLK_446MHZ_IN_HZ;\n+\n+\t/* default condition is not required as clk_src is restricted\n+\t * to a 2-bit value from GLGEN_CLKSTAT_SRC_PSM_CLK_SRC_M mask.\n+\t * The above switch statements cover the possible values of\n+\t * this variable.\n+\t */\n \t}\n }\n \n@@ -2267,7 +2509,7 @@ ice_sched_get_free_vsi_parent(struct ice_hw *hw, struct ice_sched_node *node,\n  * This function removes the child from the old parent and adds it to a new\n  * parent\n  */\n-static void\n+void\n ice_sched_update_parent(struct ice_sched_node *new_parent,\n \t\t\tstruct ice_sched_node *node)\n {\n@@ -2301,7 +2543,7 @@ ice_sched_update_parent(struct ice_sched_node *new_parent,\n  *\n  * This function move the child nodes to a given parent.\n  */\n-static enum ice_status\n+enum ice_status\n ice_sched_move_nodes(struct ice_port_info *pi, struct ice_sched_node *parent,\n \t\t     u16 num_items, u32 *list)\n {\n@@ -4372,7 +4614,7 @@ ice_sched_set_node_bw_dflt(struct ice_port_info *pi,\n  * node's RL profile ID of type CIR, EIR, or SRL, and removes old profile\n  * ID from local database. The caller needs to hold scheduler lock.\n  */\n-static enum ice_status\n+enum ice_status\n ice_sched_set_node_bw(struct ice_port_info *pi, struct ice_sched_node *node,\n \t\t      enum ice_rl_type rl_type, u32 bw, u8 layer_num)\n {\n@@ -4408,6 +4650,58 @@ ice_sched_set_node_bw(struct ice_port_info *pi, struct ice_sched_node *node,\n \t\t\t\t       ICE_AQC_RL_PROFILE_TYPE_M, old_id);\n }\n \n+/**\n+ * ice_sched_set_node_priority - set node's priority\n+ * @pi: port information structure\n+ * @node: tree node\n+ * @priority: number 0-7 representing priority among siblings\n+ *\n+ * This function sets priority of a node among it's siblings.\n+ */\n+enum ice_status\n+ice_sched_set_node_priority(struct ice_port_info *pi, struct ice_sched_node *node,\n+\t\t\t    u16 priority)\n+{\n+\tstruct ice_aqc_txsched_elem_data buf;\n+\tstruct ice_aqc_txsched_elem *data;\n+\n+\tbuf = node->info;\n+\tdata = &buf.data;\n+\n+\tdata->valid_sections |= ICE_AQC_ELEM_VALID_GENERIC;\n+\tdata->generic |= ICE_AQC_ELEM_GENERIC_PRIO_M &\n+\t\t\t (priority << ICE_AQC_ELEM_GENERIC_PRIO_S);\n+\n+\treturn ice_sched_update_elem(pi->hw, node, &buf);\n+}\n+\n+/**\n+ * ice_sched_set_node_weight - set node's weight\n+ * @pi: port information structure\n+ * @node: tree node\n+ * @weight: number 1-200 representing weight for WFQ\n+ *\n+ * This function sets weight of the node for WFQ algorithm.\n+ */\n+enum ice_status\n+ice_sched_set_node_weight(struct ice_port_info *pi, struct ice_sched_node *node, u16 weight)\n+{\n+\tstruct ice_aqc_txsched_elem_data buf;\n+\tstruct ice_aqc_txsched_elem *data;\n+\n+\tbuf = node->info;\n+\tdata = &buf.data;\n+\n+\tdata->valid_sections = ICE_AQC_ELEM_VALID_CIR | ICE_AQC_ELEM_VALID_EIR |\n+\t\t\t       ICE_AQC_ELEM_VALID_GENERIC;\n+\tdata->cir_bw.bw_alloc = CPU_TO_LE16(weight);\n+\tdata->eir_bw.bw_alloc = CPU_TO_LE16(weight);\n+\tdata->generic |= ICE_AQC_ELEM_GENERIC_SP_M &\n+\t\t\t (0x0 << ICE_AQC_ELEM_GENERIC_SP_S);\n+\n+\treturn ice_sched_update_elem(pi->hw, node, &buf);\n+}\n+\n /**\n  * ice_sched_set_node_bw_lmt - set node's BW limit\n  * @pi: port information structure\n@@ -4421,7 +4715,7 @@ ice_sched_set_node_bw(struct ice_port_info *pi, struct ice_sched_node *node,\n  * NOTE: Caller provides the correct SRL node in case of shared profile\n  * settings.\n  */\n-static enum ice_status\n+enum ice_status\n ice_sched_set_node_bw_lmt(struct ice_port_info *pi, struct ice_sched_node *node,\n \t\t\t  enum ice_rl_type rl_type, u32 bw)\n {\n@@ -4444,6 +4738,81 @@ ice_sched_set_node_bw_lmt(struct ice_port_info *pi, struct ice_sched_node *node,\n \treturn ice_sched_set_node_bw(pi, node, rl_type, bw, layer_num);\n }\n \n+/**\n+ * ice_sched_save_root_node_bw - save root node BW limit\n+ * @pi: port information structure\n+ * @rl_type: min or max\n+ * @bw: bandwidth in Kbps\n+ *\n+ * This function saves the modified values of bandwidth settings for later\n+ * replay purpose (restore) after tree recreation.\n+ */\n+static enum ice_status\n+ice_sched_save_root_node_bw(struct ice_port_info *pi,\n+\t\t\t    enum ice_rl_type rl_type, u32 bw)\n+{\n+\tswitch (rl_type) {\n+\tcase ICE_MIN_BW:\n+\t\tice_set_clear_cir_bw(&pi->root_node_bw_t_info, bw);\n+\t\tbreak;\n+\tcase ICE_MAX_BW:\n+\t\tice_set_clear_eir_bw(&pi->root_node_bw_t_info, bw);\n+\t\tbreak;\n+\tcase ICE_SHARED_BW:\n+\t\tice_set_clear_shared_bw(&pi->root_node_bw_t_info, bw);\n+\t\tbreak;\n+\tdefault:\n+\t\treturn ICE_ERR_PARAM;\n+\t}\n+\treturn ICE_SUCCESS;\n+}\n+\n+/**\n+ * ice_sched_set_root_node_bw_lmt - set root node's BW limit\n+ * @pi: port information structure\n+ * @rl_type: rate limit type min, max, or shared\n+ * @bw: bandwidth in Kbps\n+ *\n+ * It updates root node's BW limit parameters like BW RL profile ID of type\n+ * CIR, EIR, or SRL.\n+ */\n+static enum ice_status\n+ice_sched_set_root_node_bw_lmt(struct ice_port_info *pi,\n+\t\t\t       enum ice_rl_type rl_type, u32 bw)\n+{\n+\tenum ice_status status = ICE_ERR_PARAM;\n+\n+\tice_acquire_lock(&pi->sched_lock);\n+\tif (!pi->root)\n+\t\tgoto exit_set_root_node_bw;\n+\n+\tstatus = ice_sched_set_node_bw_lmt(pi, pi->root, rl_type, bw);\n+\tif (!status)\n+\t\tstatus = ice_sched_save_root_node_bw(pi, rl_type, bw);\n+\n+exit_set_root_node_bw:\n+\tice_release_lock(&pi->sched_lock);\n+\treturn status;\n+}\n+\n+/**\n+ * ice_cfg_root_node_bw_lmt - configure the root BW\n+ * @pi: port information structure\n+ * @bw: bandwidth in Kbps - Kilo bits per sec\n+ * @rl_type: rate limit type min, max, or shared\n+ *\n+ * This function configure the root node CIR, EIR or SRL BW limit\n+ */\n+enum ice_status\n+ice_cfg_root_node_bw_lmt(struct ice_port_info *pi, u32 bw,\n+\t\t\t enum ice_rl_type rl_type)\n+{\n+\tif (!pi->root)\n+\t\treturn ICE_ERR_PARAM;\n+\n+\treturn ice_sched_set_root_node_bw_lmt(pi, rl_type, bw);\n+}\n+\n /**\n  * ice_sched_set_node_bw_dflt_lmt - set node's BW limit to default\n  * @pi: port information structure\ndiff --git a/drivers/net/ice/base/ice_sched.h b/drivers/net/ice/base/ice_sched.h\nindex a71619ebf0..d7a548e0c4 100644\n--- a/drivers/net/ice/base/ice_sched.h\n+++ b/drivers/net/ice/base/ice_sched.h\n@@ -7,6 +7,8 @@\n \n #include \"ice_common.h\"\n \n+#define SCHED_NODE_NAME_MAX_LEN 32\n+\n #define ICE_SCHED_5_LAYERS\t5\n #define ICE_SCHED_9_LAYERS\t9\n \n@@ -38,6 +40,31 @@\n #define ICE_PSM_CLK_446MHZ_IN_HZ 446428571\n #define ICE_PSM_CLK_390MHZ_IN_HZ 390625000\n \n+/* bit definitions per recipe */\n+#define ICE_RECIPE_BIT_INCL_IPG_AND_PREAMBLE        BIT(4)\n+#define ICE_RECIPE_BIT_INCL_OFFSET                  BIT(3)\n+#define ICE_RECIPE_BIT_INCL_ESP_TRAILER             BIT(2)\n+#define ICE_RECIPE_BIT_INCL_L2_PADDING              BIT(1)\n+#define ICE_RECIPE_BIT_INCL_CRC                     BIT(0)\n+\n+/* protocol IDs from factory parsing program */\n+#define ICE_PROT_ID_MAC_OUTER_1             0x01\n+#define ICE_PROT_ID_MAC_OUTER_2             0x02\n+#define ICE_PROT_ID_MAC_INNER_LAST          0x04\n+#define ICE_PROT_ID_IPV4_OUTER_1            0x20\n+#define ICE_PROT_ID_IPV4_INNER_LAST         0x21\n+#define ICE_PROT_ID_IPV6_OUTER_1            0x28\n+#define ICE_PROT_ID_IPV6_INNER_LAST         0x29\n+\n+/* Packet adjustment profile ID */\n+#define ICE_ADJ_PROFILE_ID 0\n+#define ICE_DWORDS_PER_ADJ 8\n+\n+#define PSM_CLK_SRC_367_MHZ 0x0\n+#define PSM_CLK_SRC_416_MHZ 0x1\n+#define PSM_CLK_SRC_446_MHZ 0x2\n+#define PSM_CLK_SRC_390_MHZ 0x3\n+\n struct rl_profile_params {\n \tu32 bw;\t\t\t/* in Kbps */\n \tu16 rl_multiplier;\n@@ -96,7 +123,38 @@ enum ice_status\n ice_aq_query_sched_elems(struct ice_hw *hw, u16 elems_req,\n \t\t\t struct ice_aqc_txsched_elem_data *buf, u16 buf_size,\n \t\t\t u16 *elems_ret, struct ice_sq_cd *cd);\n+\n+enum ice_status\n+ice_sched_set_node_bw_lmt(struct ice_port_info *pi, struct ice_sched_node *node,\n+\t\t\t  enum ice_rl_type rl_type, u32 bw);\n+\n+enum ice_status\n+ice_sched_set_node_bw(struct ice_port_info *pi, struct ice_sched_node *node,\n+\t\t      enum ice_rl_type rl_type, u32 bw, u8 layer_num);\n+\n+enum ice_status\n+ice_sched_add_elems(struct ice_port_info *pi, struct ice_sched_node *tc_node,\n+\t\t    struct ice_sched_node *parent, u8 layer, u16 num_nodes,\n+\t\t    u16 *num_nodes_added, u32 *first_node_teid,\n+\t\t    struct ice_sched_node **prealloc_node);\n+\n+enum ice_status\n+ice_sched_move_nodes(struct ice_port_info *pi, struct ice_sched_node *parent,\n+\t\t     u16 num_items, u32 *list);\n+\n+enum ice_status\n+ice_sched_set_node_priority(struct ice_port_info *pi, struct ice_sched_node *node,\n+\t\t\t    u16 priority);\n+enum ice_status\n+ice_sched_set_node_weight(struct ice_port_info *pi, struct ice_sched_node *node,\n+\t\t\t  u16 weight);\n+\n enum ice_status ice_sched_init_port(struct ice_port_info *pi);\n+enum ice_status ice_sched_add_dflt_l2_nodes(struct ice_port_info *pi);\n+enum ice_status ice_sched_clear_l2_nodes(struct ice_port_info *pi);\n+enum ice_status ice_sched_set_dflt_cgd_to_tc_map(struct ice_port_info *pi);\n+enum ice_status\n+ice_sched_copy_cgd(struct ice_port_info *src, struct ice_port_info *dst, u8 num_cgd);\n enum ice_status ice_sched_query_res_alloc(struct ice_hw *hw);\n void ice_sched_get_psm_clk_freq(struct ice_hw *hw);\n \n@@ -112,7 +170,11 @@ ice_sched_find_node_by_teid(struct ice_sched_node *start_node, u32 teid);\n /* Add a scheduling node into SW DB for given info */\n enum ice_status\n ice_sched_add_node(struct ice_port_info *pi, u8 layer,\n-\t\t   struct ice_aqc_txsched_elem_data *info);\n+\t\t   struct ice_aqc_txsched_elem_data *info,\n+\t\t   struct ice_sched_node *prealloc_node);\n+void\n+ice_sched_update_parent(struct ice_sched_node *new_parent,\n+\t\t\tstruct ice_sched_node *node);\n void ice_free_sched_node(struct ice_port_info *pi, struct ice_sched_node *node);\n struct ice_sched_node *ice_sched_get_tc_node(struct ice_port_info *pi, u8 tc);\n struct ice_sched_node *\n@@ -221,6 +283,9 @@ enum ice_status\n ice_sched_cfg_sibl_node_prio(struct ice_port_info *pi,\n \t\t\t     struct ice_sched_node *node, u8 priority);\n enum ice_status\n+ice_cfg_root_node_bw_lmt(struct ice_port_info *pi, u32 bw,\n+\t\t\t enum ice_rl_type rl_type);\n+enum ice_status\n ice_cfg_tc_node_bw_alloc(struct ice_port_info *pi, u8 tc,\n \t\t\t enum ice_rl_type rl_type, u8 bw_alloc);\n enum ice_status ice_cfg_rl_burst_size(struct ice_hw *hw, u32 bytes);\n@@ -229,7 +294,7 @@ void ice_sched_replay_agg(struct ice_hw *hw);\n enum ice_status ice_sched_replay_tc_node_bw(struct ice_port_info *pi);\n enum ice_status ice_replay_vsi_agg(struct ice_hw *hw, u16 vsi_handle);\n enum ice_status ice_sched_replay_root_node_bw(struct ice_port_info *pi);\n-enum ice_status\n-ice_sched_replay_q_bw(struct ice_port_info *pi, struct ice_q_ctx *q_ctx);\n+enum ice_status ice_sched_replay_q_bw(struct ice_port_info *pi, struct ice_q_ctx *q_ctx);\n \n+void ice_cfg_pkt_len_adj_profiles(struct ice_hw *hw);\n #endif /* _ICE_SCHED_H_ */\ndiff --git a/drivers/net/ice/base/ice_type.h b/drivers/net/ice/base/ice_type.h\nindex 17383ae23f..ec4892179a 100644\n--- a/drivers/net/ice/base/ice_type.h\n+++ b/drivers/net/ice/base/ice_type.h\n@@ -992,9 +992,11 @@ struct ice_sched_node {\n \tu8 num_children;\n \tu8 tc_num;\n \tu8 owner;\n+\tu8 cgd;\t\t\t\t/* Valid only for Layer 2 */\n #define ICE_SCHED_NODE_OWNER_LAN\t0\n #define ICE_SCHED_NODE_OWNER_AE\t\t1\n #define ICE_SCHED_NODE_OWNER_RDMA\t2\n+#define ICE_MAX_CGD_PER_PORT\t\t4\n };\n \n /* Access Macros for Tx Sched Elements data */\n@@ -1213,6 +1215,7 @@ struct ice_port_info {\n \tstruct ice_bw_type_info tc_node_bw_t_info[ICE_MAX_TRAFFIC_CLASS];\n \tstruct ice_qos_cfg qos_cfg;\n \tu8 is_vf:1;\n+\tu8 is_custom_tx_enabled:1;\n };\n \n struct ice_switch_info {\n",
    "prefixes": [
        "09/30"
    ]
}