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GET /api/patches/126572/?format=api
{ "id": 126572, "url": "http://patches.dpdk.org/api/patches/126572/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20230427062001.478032-6-qiming.yang@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20230427062001.478032-6-qiming.yang@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20230427062001.478032-6-qiming.yang@intel.com", "date": "2023-04-27T06:19:36", "name": "[05/30] net/ice/base: clean up RSS LUT and fix media type", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "ba1e5aaad5d2a5e70e36ff78707d413322e0f755", "submitter": { "id": 522, "url": "http://patches.dpdk.org/api/people/522/?format=api", "name": "Qiming Yang", "email": "qiming.yang@intel.com" }, "delegate": { "id": 1540, "url": "http://patches.dpdk.org/api/users/1540/?format=api", "username": "qzhan15", "first_name": "Qi", "last_name": "Zhang", "email": "qi.z.zhang@intel.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20230427062001.478032-6-qiming.yang@intel.com/mbox/", "series": [ { "id": 27885, "url": "http://patches.dpdk.org/api/series/27885/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=27885", "date": "2023-04-27T06:19:31", "name": "net/ice/base: share code update", "version": 1, "mbox": "http://patches.dpdk.org/series/27885/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/126572/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/126572/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 85B3542A08;\n\tThu, 27 Apr 2023 08:38:29 +0200 (CEST)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id A011042D75;\n\tThu, 27 Apr 2023 08:37:57 +0200 (CEST)", "from mga01.intel.com (mga01.intel.com [192.55.52.88])\n by mails.dpdk.org (Postfix) with ESMTP id D002542D59\n for <dev@dpdk.org>; Thu, 27 Apr 2023 08:37:54 +0200 (CEST)", "from fmsmga002.fm.intel.com ([10.253.24.26])\n by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 26 Apr 2023 23:37:54 -0700", "from dpdk-qiming3.sh.intel.com ([10.67.111.4])\n by fmsmga002.fm.intel.com with ESMTP; 26 Apr 2023 23:37:51 -0700" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1682577475; x=1714113475;\n h=from:to:cc:subject:date:message-id:in-reply-to:\n references:mime-version:content-transfer-encoding;\n bh=uCTGDlcQsj3vl0XcKoIBX0oM0jE4InE+k7FZrga8oiA=;\n b=LegkXi2ovp0lN1peNNMVyt37+M6QaS0nr8OEK8gX1IeCxBvvtJMhlgv3\n 6g77MmH2tbuCuYKQEmLdTSEbuWyeD/gaK27iOgSg8ZM9m1oPlp/4vZcXm\n nSFe0Di9QO3guYcGlKFamiu56DhoUh9ApBjzAiNP6r8WeDRXQbHeGgyNb\n Sd7MobYZlkEZc55+WToCJoIBe/CjTvL0Q8pR7TXgt8csyrPuKZ76+nMS+\n /2MTfU6QlFQNX/mrDpCNAeW/PfM833v6k4Gbk9mAkc4kLvRtZJaj50vcy\n YVoVF6+njyqEWo7ELljYd2dN3QV5ljgh8pd1i06JVJfUc44/B4ESxjzx3 A==;", "X-IronPort-AV": [ "E=McAfee;i=\"6600,9927,10692\"; a=\"375324279\"", "E=Sophos;i=\"5.99,230,1677571200\"; d=\"scan'208\";a=\"375324279\"", "E=McAfee;i=\"6600,9927,10692\"; a=\"805845680\"", "E=Sophos;i=\"5.99,230,1677571200\"; d=\"scan'208\";a=\"805845680\"" ], "X-ExtLoop1": "1", "From": "Qiming Yang <qiming.yang@intel.com>", "To": "dev@dpdk.org", "Cc": "qi.z.zhang@intel.com, Qiming Yang <qiming.yang@intel.com>,\n Paul Greenwalt <paul.greenwalt@intel.com>,\n Przemek Kitszel <przemyslaw.kitszel@intel.com>", "Subject": "[PATCH 05/30] net/ice/base: clean up RSS LUT and fix media type", "Date": "Thu, 27 Apr 2023 06:19:36 +0000", "Message-Id": "<20230427062001.478032-6-qiming.yang@intel.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20230427062001.478032-1-qiming.yang@intel.com>", "References": "<20230427062001.478032-1-qiming.yang@intel.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Refactor __ice_aq_get_set_rss_lut():\n - get variant:\n - make use params->lut_size only as a size of params->lut;\n - return LUT size via params->lut_size;\n - set: remove option to set RSS LUT smaller than available\n (eg forbid PF LUT sized 512);\n - both: clean up code.\n - fix get media type and add the media type ICE_MEDIA_NONE.\n\nSigned-off-by: Paul Greenwalt <paul.greenwalt@intel.com>\nSigned-off-by: Przemek Kitszel <przemyslaw.kitszel@intel.com>\nSigned-off-by: Qiming Yang <qiming.yang@intel.com>\n---\n drivers/net/ice/base/ice_adminq_cmd.h | 30 ++-\n drivers/net/ice/base/ice_common.c | 366 +++++++++++---------------\n drivers/net/ice/base/ice_common.h | 1 +\n drivers/net/ice/base/ice_type.h | 94 ++++++-\n 4 files changed, 275 insertions(+), 216 deletions(-)", "diff": "diff --git a/drivers/net/ice/base/ice_adminq_cmd.h b/drivers/net/ice/base/ice_adminq_cmd.h\nindex 69e528a8c9..8731f35022 100644\n--- a/drivers/net/ice/base/ice_adminq_cmd.h\n+++ b/drivers/net/ice/base/ice_adminq_cmd.h\n@@ -1401,7 +1401,18 @@ struct ice_aqc_get_phy_caps {\n #define ICE_PHY_TYPE_HIGH_100G_CAUI2\t\tBIT_ULL(2)\n #define ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC\tBIT_ULL(3)\n #define ICE_PHY_TYPE_HIGH_100G_AUI2\t\tBIT_ULL(4)\n-#define ICE_PHY_TYPE_HIGH_MAX_INDEX\t\t4\n+#define ICE_PHY_TYPE_HIGH_200G_CR4_PAM4\t\tBIT_ULL(5)\n+#define ICE_PHY_TYPE_HIGH_200G_SR4\t\tBIT_ULL(6)\n+#define ICE_PHY_TYPE_HIGH_200G_FR4\t\tBIT_ULL(7)\n+#define ICE_PHY_TYPE_HIGH_200G_LR4\t\tBIT_ULL(8)\n+#define ICE_PHY_TYPE_HIGH_200G_DR4\t\tBIT_ULL(9)\n+#define ICE_PHY_TYPE_HIGH_200G_KR4_PAM4\t\tBIT_ULL(10)\n+#define ICE_PHY_TYPE_HIGH_200G_AUI4_AOC_ACC\tBIT_ULL(11)\n+#define ICE_PHY_TYPE_HIGH_200G_AUI4\t\tBIT_ULL(12)\n+#define ICE_PHY_TYPE_HIGH_200G_AUI8_AOC_ACC\tBIT_ULL(13)\n+#define ICE_PHY_TYPE_HIGH_200G_AUI8\t\tBIT_ULL(14)\n+#define ICE_PHY_TYPE_HIGH_400GBASE_FR8\t\tBIT_ULL(15)\n+#define ICE_PHY_TYPE_HIGH_MAX_INDEX\t\t15\n \n struct ice_aqc_get_phy_caps_data {\n \t__le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */\n@@ -2191,6 +2202,19 @@ struct ice_aqc_get_set_rss_keys {\n \tu8 extended_hash_key[ICE_AQC_GET_SET_RSS_KEY_DATA_HASH_KEY_SIZE];\n };\n \n+enum ice_lut_type {\n+\tICE_LUT_VSI = 0,\n+\tICE_LUT_PF = 1,\n+\tICE_LUT_GLOBAL = 2,\n+\tICE_LUT_TYPE_MASK = 3\n+};\n+\n+enum ice_lut_size {\n+\tICE_LUT_VSI_SIZE = 64,\n+\tICE_LUT_GLOBAL_SIZE = 512,\n+\tICE_LUT_PF_SIZE = 2048,\n+};\n+\n /* Get/Set RSS LUT (indirect 0x0B05/0x0B03) */\n struct ice_aqc_get_set_rss_lut {\n #define ICE_AQC_GSET_RSS_LUT_VSI_VALID\tBIT(15)\n@@ -2199,7 +2223,7 @@ struct ice_aqc_get_set_rss_lut {\n \t__le16 vsi_id;\n #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_S\t0\n #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_M\t\\\n-\t\t\t\t(0x3 << ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_S)\n+\t(ICE_LUT_TYPE_MASK << ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_S)\n \n #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_VSI\t 0\n #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF\t 1\n@@ -2207,7 +2231,7 @@ struct ice_aqc_get_set_rss_lut {\n \n #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S\t 2\n #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M\t \\\n-\t\t\t\t(0x3 << ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S)\n+\t(ICE_LUT_TYPE_MASK << ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S)\n \n #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128\t 128\n #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128_FLAG 0\ndiff --git a/drivers/net/ice/base/ice_common.c b/drivers/net/ice/base/ice_common.c\nindex fa30c50ca1..006ffa802c 100644\n--- a/drivers/net/ice/base/ice_common.c\n+++ b/drivers/net/ice/base/ice_common.c\n@@ -341,6 +341,93 @@ ice_aq_manage_mac_read(struct ice_hw *hw, void *buf, u16 buf_size,\n \treturn ICE_SUCCESS;\n }\n \n+/**\n+ * ice_phy_maps_to_media\n+ * @phy_type_low: PHY type low bits\n+ * @phy_type_high: PHY type high bits\n+ * @media_mask_low: media type PHY type low bitmask\n+ * @media_mask_high: media type PHY type high bitmask\n+ *\n+ * Return true if PHY type [low|high] bits are only of media type PHY types\n+ * [low|high] bitmask.\n+ */\n+static bool\n+ice_phy_maps_to_media(u64 phy_type_low, u64 phy_type_high,\n+\t\t u64 media_mask_low, u64 media_mask_high)\n+{\n+\t/* check if a PHY type exist for media type */\n+\tif (!(phy_type_low & media_mask_low ||\n+\t phy_type_high & media_mask_high))\n+\t\treturn false;\n+\n+\t/* check that PHY types are only of media type */\n+\tif (!(phy_type_low & ~media_mask_low) &&\n+\t !(phy_type_high & ~media_mask_high))\n+\t\treturn true;\n+\n+\treturn false;\n+}\n+\n+/**\n+ * ice_set_media_type - Sets media type\n+ * @pi: port information structure\n+ *\n+ * Set ice_port_info PHY media type based on PHY type. This should be called\n+ * from Get PHY caps with media.\n+ */\n+static void ice_set_media_type(struct ice_port_info *pi)\n+{\n+\tenum ice_media_type *media_type;\n+\tu64 phy_type_high, phy_type_low;\n+\n+\tphy_type_high = pi->phy.phy_type_high;\n+\tphy_type_low = pi->phy.phy_type_low;\n+\tmedia_type = &pi->phy.media_type;\n+\n+\t/* if no media, then media type is NONE */\n+\tif (!(pi->phy.link_info.link_info & ICE_AQ_MEDIA_AVAILABLE))\n+\t\t*media_type = ICE_MEDIA_NONE;\n+\t/* else if PHY types are only BASE-T, then media type is BASET */\n+\telse if (ice_phy_maps_to_media(phy_type_low, phy_type_high,\n+\t\t\t\t ICE_MEDIA_BASET_PHY_TYPE_LOW_M, 0))\n+\t\t*media_type = ICE_MEDIA_BASET;\n+\t/* else if any PHY type is BACKPLANE, then media type is BACKPLANE */\n+\telse if (phy_type_low & ICE_MEDIA_BP_PHY_TYPE_LOW_M ||\n+\t\t phy_type_high & ICE_MEDIA_BP_PHY_TYPE_HIGH_M)\n+\t\t*media_type = ICE_MEDIA_BACKPLANE;\n+\t/* else if PHY types are only optical, or optical and C2M, then media\n+\t * type is FIBER\n+\t */\n+\telse if (ice_phy_maps_to_media(phy_type_low, phy_type_high,\n+\t\t\t\t ICE_MEDIA_OPT_PHY_TYPE_LOW_M,\n+\t\t\t\t ICE_MEDIA_OPT_PHY_TYPE_HIGH_M) ||\n+\t\t ((phy_type_low & ICE_MEDIA_OPT_PHY_TYPE_LOW_M ||\n+\t\t phy_type_high & ICE_MEDIA_OPT_PHY_TYPE_HIGH_M) &&\n+\t\t (phy_type_low & ICE_MEDIA_C2M_PHY_TYPE_LOW_M ||\n+\t\t phy_type_high & ICE_MEDIA_C2C_PHY_TYPE_HIGH_M)))\n+\t\t*media_type = ICE_MEDIA_FIBER;\n+\t/* else if PHY types are only DA, or DA and C2C, then media type DA */\n+\telse if (ice_phy_maps_to_media(phy_type_low, phy_type_high,\n+\t\t\t\t ICE_MEDIA_DAC_PHY_TYPE_LOW_M,\n+\t\t\t\t ICE_MEDIA_DAC_PHY_TYPE_HIGH_M) ||\n+\t\t ((phy_type_low & ICE_MEDIA_DAC_PHY_TYPE_LOW_M ||\n+\t\t phy_type_high & ICE_MEDIA_DAC_PHY_TYPE_HIGH_M) &&\n+\t\t (phy_type_low & ICE_MEDIA_C2C_PHY_TYPE_LOW_M ||\n+\t\t phy_type_high & ICE_MEDIA_C2C_PHY_TYPE_HIGH_M)))\n+\t\t*media_type = ICE_MEDIA_DA;\n+\t/* else if PHY types are only C2M or only C2C, then media is AUI */\n+\telse if (ice_phy_maps_to_media(phy_type_low, phy_type_high,\n+\t\t\t\t ICE_MEDIA_C2M_PHY_TYPE_LOW_M,\n+\t\t\t\t ICE_MEDIA_C2M_PHY_TYPE_HIGH_M) ||\n+\t\t ice_phy_maps_to_media(phy_type_low, phy_type_high,\n+\t\t\t\t ICE_MEDIA_C2C_PHY_TYPE_LOW_M,\n+\t\t\t\t ICE_MEDIA_C2C_PHY_TYPE_HIGH_M))\n+\t\t*media_type = ICE_MEDIA_AUI;\n+\n+\telse\n+\t\t*media_type = ICE_MEDIA_UNKNOWN;\n+}\n+\n /**\n * ice_aq_get_phy_caps - returns PHY capabilities\n * @pi: port information structure\n@@ -425,6 +512,9 @@ ice_aq_get_phy_caps(struct ice_port_info *pi, bool qual_mods, u8 report_mode,\n \t\tice_memcpy(pi->phy.link_info.module_type, &pcaps->module_type,\n \t\t\t sizeof(pi->phy.link_info.module_type),\n \t\t\t ICE_NONDMA_TO_NONDMA);\n+\t\tice_set_media_type(pi);\n+\t\tice_debug(hw, ICE_DBG_LINK, \"%s: media_type = 0x%x\\n\", prefix,\n+\t\t\t pi->phy.media_type);\n \t}\n \n \treturn status;\n@@ -530,155 +620,6 @@ ice_find_netlist_node(struct ice_hw *hw, u8 node_type_ctx, u8 node_part_number,\n \treturn ICE_ERR_DOES_NOT_EXIST;\n }\n \n-/**\n- * ice_is_media_cage_present\n- * @pi: port information structure\n- *\n- * Returns true if media cage is present, else false. If no cage, then\n- * media type is backplane or BASE-T.\n- */\n-static bool ice_is_media_cage_present(struct ice_port_info *pi)\n-{\n-\tstruct ice_aqc_get_link_topo *cmd;\n-\tstruct ice_aq_desc desc;\n-\n-\tcmd = &desc.params.get_link_topo;\n-\n-\tice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_topo);\n-\n-\tcmd->addr.topo_params.node_type_ctx =\n-\t\t(ICE_AQC_LINK_TOPO_NODE_CTX_PORT <<\n-\t\t ICE_AQC_LINK_TOPO_NODE_CTX_S);\n-\n-\t/* set node type */\n-\tcmd->addr.topo_params.node_type_ctx |=\n-\t\t(ICE_AQC_LINK_TOPO_NODE_TYPE_M &\n-\t\t ICE_AQC_LINK_TOPO_NODE_TYPE_CAGE);\n-\n-\t/* Node type cage can be used to determine if cage is present. If AQC\n-\t * returns error (ENOENT), then no cage present. If no cage present then\n-\t * connection type is backplane or BASE-T.\n-\t */\n-\treturn ice_aq_get_netlist_node(pi->hw, cmd, NULL, NULL);\n-}\n-\n-/**\n- * ice_get_media_type - Gets media type\n- * @pi: port information structure\n- */\n-static enum ice_media_type ice_get_media_type(struct ice_port_info *pi)\n-{\n-\tstruct ice_link_status *hw_link_info;\n-\n-\tif (!pi)\n-\t\treturn ICE_MEDIA_UNKNOWN;\n-\n-\thw_link_info = &pi->phy.link_info;\n-\tif (hw_link_info->phy_type_low && hw_link_info->phy_type_high)\n-\t\t/* If more than one media type is selected, report unknown */\n-\t\treturn ICE_MEDIA_UNKNOWN;\n-\n-\tif (hw_link_info->phy_type_low) {\n-\t\t/* 1G SGMII is a special case where some DA cable PHYs\n-\t\t * may show this as an option when it really shouldn't\n-\t\t * be since SGMII is meant to be between a MAC and a PHY\n-\t\t * in a backplane. Try to detect this case and handle it\n-\t\t */\n-\t\tif (hw_link_info->phy_type_low == ICE_PHY_TYPE_LOW_1G_SGMII &&\n-\t\t (hw_link_info->module_type[ICE_AQC_MOD_TYPE_IDENT] ==\n-\t\t ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_ACTIVE ||\n-\t\t hw_link_info->module_type[ICE_AQC_MOD_TYPE_IDENT] ==\n-\t\t ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_PASSIVE))\n-\t\t\treturn ICE_MEDIA_DA;\n-\n-\t\tswitch (hw_link_info->phy_type_low) {\n-\t\tcase ICE_PHY_TYPE_LOW_1000BASE_SX:\n-\t\tcase ICE_PHY_TYPE_LOW_1000BASE_LX:\n-\t\tcase ICE_PHY_TYPE_LOW_10GBASE_SR:\n-\t\tcase ICE_PHY_TYPE_LOW_10GBASE_LR:\n-\t\tcase ICE_PHY_TYPE_LOW_25GBASE_SR:\n-\t\tcase ICE_PHY_TYPE_LOW_25GBASE_LR:\n-\t\tcase ICE_PHY_TYPE_LOW_40GBASE_SR4:\n-\t\tcase ICE_PHY_TYPE_LOW_40GBASE_LR4:\n-\t\tcase ICE_PHY_TYPE_LOW_50GBASE_SR2:\n-\t\tcase ICE_PHY_TYPE_LOW_50GBASE_LR2:\n-\t\tcase ICE_PHY_TYPE_LOW_50GBASE_SR:\n-\t\tcase ICE_PHY_TYPE_LOW_50GBASE_FR:\n-\t\tcase ICE_PHY_TYPE_LOW_50GBASE_LR:\n-\t\tcase ICE_PHY_TYPE_LOW_100GBASE_SR4:\n-\t\tcase ICE_PHY_TYPE_LOW_100GBASE_LR4:\n-\t\tcase ICE_PHY_TYPE_LOW_100GBASE_SR2:\n-\t\tcase ICE_PHY_TYPE_LOW_100GBASE_DR:\n-\t\t\treturn ICE_MEDIA_FIBER;\n-\t\tcase ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC:\n-\t\tcase ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC:\n-\t\tcase ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC:\n-\t\tcase ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC:\n-\t\tcase ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC:\n-\t\tcase ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC:\n-\t\tcase ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC:\n-\t\tcase ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC:\n-\t\t\treturn ICE_MEDIA_FIBER;\n-\t\tcase ICE_PHY_TYPE_LOW_100BASE_TX:\n-\t\tcase ICE_PHY_TYPE_LOW_1000BASE_T:\n-\t\tcase ICE_PHY_TYPE_LOW_2500BASE_T:\n-\t\tcase ICE_PHY_TYPE_LOW_5GBASE_T:\n-\t\tcase ICE_PHY_TYPE_LOW_10GBASE_T:\n-\t\tcase ICE_PHY_TYPE_LOW_25GBASE_T:\n-\t\t\treturn ICE_MEDIA_BASET;\n-\t\tcase ICE_PHY_TYPE_LOW_10G_SFI_DA:\n-\t\tcase ICE_PHY_TYPE_LOW_25GBASE_CR:\n-\t\tcase ICE_PHY_TYPE_LOW_25GBASE_CR_S:\n-\t\tcase ICE_PHY_TYPE_LOW_25GBASE_CR1:\n-\t\tcase ICE_PHY_TYPE_LOW_40GBASE_CR4:\n-\t\tcase ICE_PHY_TYPE_LOW_50GBASE_CR2:\n-\t\tcase ICE_PHY_TYPE_LOW_50GBASE_CP:\n-\t\tcase ICE_PHY_TYPE_LOW_100GBASE_CR4:\n-\t\tcase ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4:\n-\t\tcase ICE_PHY_TYPE_LOW_100GBASE_CP2:\n-\t\t\treturn ICE_MEDIA_DA;\n-\t\tcase ICE_PHY_TYPE_LOW_25G_AUI_C2C:\n-\t\tcase ICE_PHY_TYPE_LOW_40G_XLAUI:\n-\t\tcase ICE_PHY_TYPE_LOW_50G_LAUI2:\n-\t\tcase ICE_PHY_TYPE_LOW_50G_AUI2:\n-\t\tcase ICE_PHY_TYPE_LOW_50G_AUI1:\n-\t\tcase ICE_PHY_TYPE_LOW_100G_AUI4:\n-\t\tcase ICE_PHY_TYPE_LOW_100G_CAUI4:\n-\t\t\tif (ice_is_media_cage_present(pi))\n-\t\t\t\treturn ICE_MEDIA_AUI;\n-\t\t\t/* fall-through */\n-\t\tcase ICE_PHY_TYPE_LOW_1000BASE_KX:\n-\t\tcase ICE_PHY_TYPE_LOW_2500BASE_KX:\n-\t\tcase ICE_PHY_TYPE_LOW_2500BASE_X:\n-\t\tcase ICE_PHY_TYPE_LOW_5GBASE_KR:\n-\t\tcase ICE_PHY_TYPE_LOW_10GBASE_KR_CR1:\n-\t\tcase ICE_PHY_TYPE_LOW_10G_SFI_C2C:\n-\t\tcase ICE_PHY_TYPE_LOW_25GBASE_KR:\n-\t\tcase ICE_PHY_TYPE_LOW_25GBASE_KR1:\n-\t\tcase ICE_PHY_TYPE_LOW_25GBASE_KR_S:\n-\t\tcase ICE_PHY_TYPE_LOW_40GBASE_KR4:\n-\t\tcase ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4:\n-\t\tcase ICE_PHY_TYPE_LOW_50GBASE_KR2:\n-\t\tcase ICE_PHY_TYPE_LOW_100GBASE_KR4:\n-\t\tcase ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4:\n-\t\t\treturn ICE_MEDIA_BACKPLANE;\n-\t\t}\n-\t} else {\n-\t\tswitch (hw_link_info->phy_type_high) {\n-\t\tcase ICE_PHY_TYPE_HIGH_100G_AUI2:\n-\t\tcase ICE_PHY_TYPE_HIGH_100G_CAUI2:\n-\t\t\tif (ice_is_media_cage_present(pi))\n-\t\t\t\treturn ICE_MEDIA_AUI;\n-\t\t\t/* fall-through */\n-\t\tcase ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4:\n-\t\t\treturn ICE_MEDIA_BACKPLANE;\n-\t\tcase ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC:\n-\t\tcase ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC:\n-\t\t\treturn ICE_MEDIA_FIBER;\n-\t\t}\n-\t}\n-\treturn ICE_MEDIA_UNKNOWN;\n-}\n \n /**\n * ice_aq_get_link_info\n@@ -696,7 +637,6 @@ ice_aq_get_link_info(struct ice_port_info *pi, bool ena_lse,\n \tstruct ice_aqc_get_link_status_data link_data = { 0 };\n \tstruct ice_aqc_get_link_status *resp;\n \tstruct ice_link_status *li_old, *li;\n-\tenum ice_media_type *hw_media_type;\n \tstruct ice_fc_info *hw_fc_info;\n \tbool tx_pause, rx_pause;\n \tstruct ice_aq_desc desc;\n@@ -708,7 +648,6 @@ ice_aq_get_link_info(struct ice_port_info *pi, bool ena_lse,\n \t\treturn ICE_ERR_PARAM;\n \thw = pi->hw;\n \tli_old = &pi->phy.link_info_old;\n-\thw_media_type = &pi->phy.media_type;\n \tli = &pi->phy.link_info;\n \thw_fc_info = &pi->fc;\n \n@@ -730,7 +669,6 @@ ice_aq_get_link_info(struct ice_port_info *pi, bool ena_lse,\n \tli->link_speed = LE16_TO_CPU(link_data.link_speed);\n \tli->phy_type_low = LE64_TO_CPU(link_data.phy_type_low);\n \tli->phy_type_high = LE64_TO_CPU(link_data.phy_type_high);\n-\t*hw_media_type = ice_get_media_type(pi);\n \tli->link_info = link_data.link_info;\n \tli->link_cfg_err = link_data.link_cfg_err;\n \tli->an_info = link_data.an_info;\n@@ -761,7 +699,6 @@ ice_aq_get_link_info(struct ice_port_info *pi, bool ena_lse,\n \t\t (unsigned long long)li->phy_type_low);\n \tice_debug(hw, ICE_DBG_LINK, \"\tphy_type_high = 0x%llx\\n\",\n \t\t (unsigned long long)li->phy_type_high);\n-\tice_debug(hw, ICE_DBG_LINK, \"\tmedia_type = 0x%x\\n\", *hw_media_type);\n \tice_debug(hw, ICE_DBG_LINK, \"\tlink_info = 0x%x\\n\", li->link_info);\n \tice_debug(hw, ICE_DBG_LINK, \"\tlink_cfg_err = 0x%x\\n\", li->link_cfg_err);\n \tice_debug(hw, ICE_DBG_LINK, \"\tan_info = 0x%x\\n\", li->an_info);\n@@ -4087,6 +4024,51 @@ ice_aq_read_topo_dev_nvm(struct ice_hw *hw,\n \treturn ICE_SUCCESS;\n }\n \n+static u16 ice_lut_type_to_size(u16 lut_type)\n+{\n+\tswitch (lut_type) {\n+\tcase ICE_LUT_VSI:\n+\t\treturn ICE_LUT_VSI_SIZE;\n+\tcase ICE_LUT_GLOBAL:\n+\t\treturn ICE_LUT_GLOBAL_SIZE;\n+\tcase ICE_LUT_PF:\n+\t\treturn ICE_LUT_PF_SIZE;\n+\tdefault:\n+\t\treturn 0;\n+\t}\n+}\n+\n+static u16 ice_lut_size_to_flag(u16 lut_size)\n+{\n+\tu16 f = 0;\n+\n+\tswitch (lut_size) {\n+\tcase ICE_LUT_GLOBAL_SIZE:\n+\t\tf = ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512_FLAG;\n+\t\tbreak;\n+\tcase ICE_LUT_PF_SIZE:\n+\t\tf = ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K_FLAG;\n+\t\tbreak;\n+\tdefault:\n+\t\tbreak;\n+\t}\n+\treturn f << ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S;\n+}\n+\n+int ice_lut_size_to_type(int lut_size)\n+{\n+\tswitch (lut_size) {\n+\tcase ICE_LUT_VSI_SIZE:\n+\t\treturn ICE_LUT_VSI;\n+\tcase ICE_LUT_GLOBAL_SIZE:\n+\t\treturn ICE_LUT_GLOBAL;\n+\tcase ICE_LUT_PF_SIZE:\n+\t\treturn ICE_LUT_PF;\n+\tdefault:\n+\t\treturn -1;\n+\t}\n+}\n+\n /**\n * __ice_aq_get_set_rss_lut\n * @hw: pointer to the hardware structure\n@@ -4098,7 +4080,7 @@ ice_aq_read_topo_dev_nvm(struct ice_hw *hw,\n static enum ice_status\n __ice_aq_get_set_rss_lut(struct ice_hw *hw, struct ice_aq_get_set_rss_lut_params *params, bool set)\n {\n-\tu16 flags = 0, vsi_id, lut_type, lut_size, glob_lut_idx, vsi_handle;\n+\tu16 flags, vsi_id, lut_type, lut_size, glob_lut_idx = 0, vsi_handle;\n \tstruct ice_aqc_get_set_rss_lut *cmd_resp;\n \tstruct ice_aq_desc desc;\n \tenum ice_status status;\n@@ -4109,16 +4091,22 @@ __ice_aq_get_set_rss_lut(struct ice_hw *hw, struct ice_aq_get_set_rss_lut_params\n \n \tvsi_handle = params->vsi_handle;\n \tlut = params->lut;\n+\tlut_type = params->lut_type;\n+\tlut_size = ice_lut_type_to_size(lut_type);\n+\tcmd_resp = &desc.params.get_set_rss_lut;\n+\tif (lut_type == ICE_LUT_GLOBAL)\n+\t\tglob_lut_idx = params->global_lut_id;\n \n-\tif (!ice_is_vsi_valid(hw, vsi_handle) || !lut)\n+\tif (!lut || !lut_size || !ice_is_vsi_valid(hw, vsi_handle))\n \t\treturn ICE_ERR_PARAM;\n \n-\tlut_size = params->lut_size;\n-\tlut_type = params->lut_type;\n-\tglob_lut_idx = params->global_lut_id;\n-\tvsi_id = ice_get_hw_vsi_num(hw, vsi_handle);\n+\tif (lut_size > params->lut_size)\n+\t\treturn ICE_ERR_INVAL_SIZE;\n \n-\tcmd_resp = &desc.params.get_set_rss_lut;\n+\tif (set && lut_size != params->lut_size)\n+\t\treturn ICE_ERR_PARAM;\n+\n+\tvsi_id = ice_get_hw_vsi_num(hw, vsi_handle);\n \n \tif (set) {\n \t\tice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_rss_lut);\n@@ -4132,61 +4120,15 @@ __ice_aq_get_set_rss_lut(struct ice_hw *hw, struct ice_aq_get_set_rss_lut_params\n \t\t\t\t\tICE_AQC_GSET_RSS_LUT_VSI_ID_M) |\n \t\t\t\t ICE_AQC_GSET_RSS_LUT_VSI_VALID);\n \n-\tswitch (lut_type) {\n-\tcase ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_VSI:\n-\tcase ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF:\n-\tcase ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_GLOBAL:\n-\t\tflags |= ((lut_type << ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_S) &\n-\t\t\t ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_M);\n-\t\tbreak;\n-\tdefault:\n-\t\tstatus = ICE_ERR_PARAM;\n-\t\tgoto ice_aq_get_set_rss_lut_exit;\n-\t}\n-\n-\tif (lut_type == ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_GLOBAL) {\n-\t\tflags |= ((glob_lut_idx << ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_S) &\n-\t\t\t ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_M);\n-\n-\t\tif (!set)\n-\t\t\tgoto ice_aq_get_set_rss_lut_send;\n-\t} else if (lut_type == ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF) {\n-\t\tif (!set)\n-\t\t\tgoto ice_aq_get_set_rss_lut_send;\n-\t} else {\n-\t\tgoto ice_aq_get_set_rss_lut_send;\n-\t}\n-\n-\t/* LUT size is only valid for Global and PF table types */\n-\tswitch (lut_size) {\n-\tcase ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128:\n-\t\tflags |= (ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128_FLAG <<\n-\t\t\t ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S) &\n-\t\t\t ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M;\n-\t\tbreak;\n-\tcase ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512:\n-\t\tflags |= (ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512_FLAG <<\n-\t\t\t ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S) &\n-\t\t\t ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M;\n-\t\tbreak;\n-\tcase ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K:\n-\t\tif (lut_type == ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF) {\n-\t\t\tflags |= (ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K_FLAG <<\n-\t\t\t\t ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S) &\n-\t\t\t\t ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M;\n-\t\t\tbreak;\n-\t\t}\n-\t\t/* fall-through */\n-\tdefault:\n-\t\tstatus = ICE_ERR_PARAM;\n-\t\tgoto ice_aq_get_set_rss_lut_exit;\n-\t}\n+\tflags = ice_lut_size_to_flag(lut_size) |\n+\t\t ((lut_type << ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_S) &\n+\t\t ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_M) |\n+\t\t ((glob_lut_idx << ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_S) &\n+\t\t ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_M);\n \n-ice_aq_get_set_rss_lut_send:\n \tcmd_resp->flags = CPU_TO_LE16(flags);\n \tstatus = ice_aq_send_cmd(hw, &desc, lut, lut_size, NULL);\n-\n-ice_aq_get_set_rss_lut_exit:\n+\tparams->lut_size = LE16_TO_CPU(desc.datalen);\n \treturn status;\n }\n \ndiff --git a/drivers/net/ice/base/ice_common.h b/drivers/net/ice/base/ice_common.h\nindex e1febfb0c4..f612ce7c52 100644\n--- a/drivers/net/ice/base/ice_common.h\n+++ b/drivers/net/ice/base/ice_common.h\n@@ -100,6 +100,7 @@ ice_write_tx_drbell_q_ctx(struct ice_hw *hw,\n \t\t\t struct ice_tx_drbell_q_ctx *tx_drbell_q_ctx,\n \t\t\t u32 tx_drbell_q_index);\n \n+int ice_lut_size_to_type(int lut_size);\n enum ice_status\n ice_aq_get_rss_lut(struct ice_hw *hw, struct ice_aq_get_set_rss_lut_params *get_params);\n enum ice_status\ndiff --git a/drivers/net/ice/base/ice_type.h b/drivers/net/ice/base/ice_type.h\nindex da813c8307..3249e359de 100644\n--- a/drivers/net/ice/base/ice_type.h\n+++ b/drivers/net/ice/base/ice_type.h\n@@ -210,7 +210,8 @@ enum ice_mac_type {\n \n /* Media Types */\n enum ice_media_type {\n-\tICE_MEDIA_UNKNOWN = 0,\n+\tICE_MEDIA_NONE = 0,\n+\tICE_MEDIA_UNKNOWN,\n \tICE_MEDIA_FIBER,\n \tICE_MEDIA_BASET,\n \tICE_MEDIA_BACKPLANE,\n@@ -218,6 +219,97 @@ enum ice_media_type {\n \tICE_MEDIA_AUI,\n };\n \n+#define ICE_MEDIA_BASET_PHY_TYPE_LOW_M\t(ICE_PHY_TYPE_LOW_100BASE_TX | \\\n+\t\t\t\t\t ICE_PHY_TYPE_LOW_1000BASE_T | \\\n+\t\t\t\t\t ICE_PHY_TYPE_LOW_2500BASE_T | \\\n+\t\t\t\t\t ICE_PHY_TYPE_LOW_5GBASE_T | \\\n+\t\t\t\t\t ICE_PHY_TYPE_LOW_10GBASE_T | \\\n+\t\t\t\t\t ICE_PHY_TYPE_LOW_25GBASE_T)\n+\n+#define ICE_MEDIA_C2M_PHY_TYPE_LOW_M\t(ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC | \\\n+\t\t\t\t\t ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC | \\\n+\t\t\t\t\t ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC | \\\n+\t\t\t\t\t ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC | \\\n+\t\t\t\t\t ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC | \\\n+\t\t\t\t\t ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC | \\\n+\t\t\t\t\t ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC | \\\n+\t\t\t\t\t ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC)\n+\n+#define ICE_MEDIA_C2M_PHY_TYPE_HIGH_M (ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC | \\\n+\t\t\t\t ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC | \\\n+\t\t\t\t ICE_PHY_TYPE_HIGH_200G_AUI4_AOC_ACC | \\\n+\t\t\t\t ICE_PHY_TYPE_HIGH_200G_AUI8_AOC_ACC)\n+\n+#define ICE_MEDIA_OPT_PHY_TYPE_LOW_M\t(ICE_PHY_TYPE_LOW_1000BASE_SX | \\\n+\t\t\t\t\t ICE_PHY_TYPE_LOW_1000BASE_LX | \\\n+\t\t\t\t\t ICE_PHY_TYPE_LOW_10GBASE_SR | \\\n+\t\t\t\t\t ICE_PHY_TYPE_LOW_10GBASE_LR | \\\n+\t\t\t\t\t ICE_PHY_TYPE_LOW_25GBASE_SR | \\\n+\t\t\t\t\t ICE_PHY_TYPE_LOW_25GBASE_LR | \\\n+\t\t\t\t\t ICE_PHY_TYPE_LOW_40GBASE_SR4 | \\\n+\t\t\t\t\t ICE_PHY_TYPE_LOW_40GBASE_LR4 | \\\n+\t\t\t\t\t ICE_PHY_TYPE_LOW_50GBASE_SR2 | \\\n+\t\t\t\t\t ICE_PHY_TYPE_LOW_50GBASE_LR2 | \\\n+\t\t\t\t\t ICE_PHY_TYPE_LOW_50GBASE_SR | \\\n+\t\t\t\t\t ICE_PHY_TYPE_LOW_50GBASE_LR | \\\n+\t\t\t\t\t ICE_PHY_TYPE_LOW_100GBASE_SR4 | \\\n+\t\t\t\t\t ICE_PHY_TYPE_LOW_100GBASE_LR4 | \\\n+\t\t\t\t\t ICE_PHY_TYPE_LOW_100GBASE_SR2 | \\\n+\t\t\t\t\t ICE_PHY_TYPE_LOW_50GBASE_FR | \\\n+\t\t\t\t\t ICE_PHY_TYPE_LOW_100GBASE_DR)\n+\n+#define ICE_MEDIA_OPT_PHY_TYPE_HIGH_M\t(ICE_PHY_TYPE_HIGH_200G_SR4 | \\\n+\t\t\t\t\t ICE_PHY_TYPE_HIGH_200G_LR4 | \\\n+\t\t\t\t\t ICE_PHY_TYPE_HIGH_200G_FR4 | \\\n+\t\t\t\t\t ICE_PHY_TYPE_HIGH_200G_DR4 | \\\n+\t\t\t\t\t ICE_PHY_TYPE_HIGH_400GBASE_FR8)\n+\n+#define ICE_MEDIA_BP_PHY_TYPE_LOW_M\t(ICE_PHY_TYPE_LOW_1000BASE_KX | \\\n+\t\t\t\t\t ICE_PHY_TYPE_LOW_2500BASE_KX | \\\n+\t\t\t\t\t ICE_PHY_TYPE_LOW_5GBASE_KR | \\\n+\t\t\t\t\t ICE_PHY_TYPE_LOW_10GBASE_KR_CR1 | \\\n+\t\t\t\t\t ICE_PHY_TYPE_LOW_25GBASE_KR | \\\n+\t\t\t\t\t ICE_PHY_TYPE_LOW_25GBASE_KR_S | \\\n+\t\t\t\t\t ICE_PHY_TYPE_LOW_25GBASE_KR1 | \\\n+\t\t\t\t\t ICE_PHY_TYPE_LOW_40GBASE_KR4 | \\\n+\t\t\t\t\t ICE_PHY_TYPE_LOW_50GBASE_KR2 | \\\n+\t\t\t\t\t ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4 | \\\n+\t\t\t\t\t ICE_PHY_TYPE_LOW_100GBASE_KR4 | \\\n+\t\t\t\t\t ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4)\n+\n+#define ICE_MEDIA_BP_PHY_TYPE_HIGH_M\t(ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4 | \\\n+\t\t\t\t\t ICE_PHY_TYPE_HIGH_200G_KR4_PAM4)\n+\n+#define ICE_MEDIA_DAC_PHY_TYPE_LOW_M\t(ICE_PHY_TYPE_LOW_10G_SFI_DA | \\\n+\t\t\t\t\t ICE_PHY_TYPE_LOW_25GBASE_CR | \\\n+\t\t\t\t\t ICE_PHY_TYPE_LOW_25GBASE_CR_S | \\\n+\t\t\t\t\t ICE_PHY_TYPE_LOW_25GBASE_CR1 | \\\n+\t\t\t\t\t ICE_PHY_TYPE_LOW_40GBASE_CR4 | \\\n+\t\t\t\t\t ICE_PHY_TYPE_LOW_50GBASE_CR2 | \\\n+\t\t\t\t\t ICE_PHY_TYPE_LOW_100GBASE_CR4 | \\\n+\t\t\t\t\t ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4 | \\\n+\t\t\t\t\t ICE_PHY_TYPE_LOW_50GBASE_CP | \\\n+\t\t\t\t\t ICE_PHY_TYPE_LOW_100GBASE_CP2)\n+\n+#define ICE_MEDIA_DAC_PHY_TYPE_HIGH_M\tICE_PHY_TYPE_HIGH_200G_CR4_PAM4\n+\n+#define ICE_MEDIA_C2C_PHY_TYPE_LOW_M\t(ICE_PHY_TYPE_LOW_100M_SGMII | \\\n+\t\t\t\t\t ICE_PHY_TYPE_LOW_1G_SGMII | \\\n+\t\t\t\t\t ICE_PHY_TYPE_LOW_2500BASE_X | \\\n+\t\t\t\t\t ICE_PHY_TYPE_LOW_10G_SFI_C2C | \\\n+\t\t\t\t\t ICE_PHY_TYPE_LOW_25G_AUI_C2C | \\\n+\t\t\t\t\t ICE_PHY_TYPE_LOW_40G_XLAUI | \\\n+\t\t\t\t\t ICE_PHY_TYPE_LOW_50G_LAUI2 | \\\n+\t\t\t\t\t ICE_PHY_TYPE_LOW_50G_AUI2 | \\\n+\t\t\t\t\t ICE_PHY_TYPE_LOW_50G_AUI1 | \\\n+\t\t\t\t\t ICE_PHY_TYPE_LOW_100G_CAUI4 | \\\n+\t\t\t\t\t ICE_PHY_TYPE_LOW_100G_AUI4)\n+\n+#define ICE_MEDIA_C2C_PHY_TYPE_HIGH_M\t(ICE_PHY_TYPE_HIGH_100G_CAUI2 | \\\n+\t\t\t\t\t ICE_PHY_TYPE_HIGH_100G_AUI2 | \\\n+\t\t\t\t\t ICE_PHY_TYPE_HIGH_200G_AUI4 | \\\n+\t\t\t\t\t ICE_PHY_TYPE_HIGH_200G_AUI8)\n+\n /* Software VSI types. */\n enum ice_vsi_type {\n \tICE_VSI_PF = 0,\n", "prefixes": [ "05/30" ] }