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GET /api/patches/126570/?format=api
{ "id": 126570, "url": "http://patches.dpdk.org/api/patches/126570/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20230427062001.478032-4-qiming.yang@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20230427062001.478032-4-qiming.yang@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20230427062001.478032-4-qiming.yang@intel.com", "date": "2023-04-27T06:19:34", "name": "[03/30] net/ice/base: remove unnecessary control queue array", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "283533a55b8b16d2c2ed882184c34df941ebb40f", "submitter": { "id": 522, "url": "http://patches.dpdk.org/api/people/522/?format=api", "name": "Qiming Yang", "email": "qiming.yang@intel.com" }, "delegate": { "id": 1540, "url": "http://patches.dpdk.org/api/users/1540/?format=api", "username": "qzhan15", "first_name": "Qi", "last_name": "Zhang", "email": "qi.z.zhang@intel.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20230427062001.478032-4-qiming.yang@intel.com/mbox/", "series": [ { "id": 27885, "url": "http://patches.dpdk.org/api/series/27885/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=27885", "date": "2023-04-27T06:19:31", "name": "net/ice/base: share code update", "version": 1, "mbox": "http://patches.dpdk.org/series/27885/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/126570/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/126570/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 93B7942A08;\n\tThu, 27 Apr 2023 08:38:11 +0200 (CEST)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id CF1E142D53;\n\tThu, 27 Apr 2023 08:37:53 +0200 (CEST)", "from mga01.intel.com (mga01.intel.com [192.55.52.88])\n by mails.dpdk.org (Postfix) with ESMTP id 28C5A42D48\n for <dev@dpdk.org>; Thu, 27 Apr 2023 08:37:51 +0200 (CEST)", "from fmsmga002.fm.intel.com ([10.253.24.26])\n by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 26 Apr 2023 23:37:50 -0700", "from dpdk-qiming3.sh.intel.com ([10.67.111.4])\n by fmsmga002.fm.intel.com with ESMTP; 26 Apr 2023 23:37:47 -0700" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1682577471; x=1714113471;\n h=from:to:cc:subject:date:message-id:in-reply-to:\n references:mime-version:content-transfer-encoding;\n bh=kZiEtGOE2kAA0eZWGi0MeUpPXuvYwhLwQRD2HoTXCsM=;\n b=JvfY3pQ30EpKvd7V6baburgnfWcV5kycCsiIjNX2JNFJ7TxBG9mEnfRF\n /fIefv+3fqBpRndwhBE3OuWmkyhJo7fQYv49fdHOLZw9mCrSsZ2Uddfbc\n +r7MAENIy6osuEd52WwlbfRMCNygawyX+7XXhuE8slomvfXAlX7uNPfS5\n +DvjntzEKaAfl7JKSiQb9mgzN3cWM/NETaqWkPavCTajoKJMyLUthP7VE\n 5GASJZsGt62fglyXDFhvWcrIuTIwyE/QPqf/e/aRT4KtRI3ts6zWTd0R6\n SQ98s383kTaFb7dlzGDKbuQXgpSxzqOHOojJze6uWAtALZjTO/INuYKy7 A==;", "X-IronPort-AV": [ "E=McAfee;i=\"6600,9927,10692\"; a=\"375324260\"", "E=Sophos;i=\"5.99,230,1677571200\"; d=\"scan'208\";a=\"375324260\"", "E=McAfee;i=\"6600,9927,10692\"; a=\"805845665\"", "E=Sophos;i=\"5.99,230,1677571200\"; d=\"scan'208\";a=\"805845665\"" ], "X-ExtLoop1": "1", "From": "Qiming Yang <qiming.yang@intel.com>", "To": "dev@dpdk.org", "Cc": "qi.z.zhang@intel.com, Qiming Yang <qiming.yang@intel.com>,\n Jacob Keller <jacob.e.keller@intel.com>", "Subject": "[PATCH 03/30] net/ice/base: remove unnecessary control queue array", "Date": "Thu, 27 Apr 2023 06:19:34 +0000", "Message-Id": "<20230427062001.478032-4-qiming.yang@intel.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20230427062001.478032-1-qiming.yang@intel.com>", "References": "<20230427062001.478032-1-qiming.yang@intel.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "The driver allocates a cmd_buf array in addition to the desc_buf array.\nThis array stores an ice_sq_cd command details structure for each entry in\nthe control queue ring. And improve debug print for control queue messages.\n\nSigned-off-by: Jacob Keller <jacob.e.keller@intel.com>\nSigned-off-by: Qiming Yang <qiming.yang@intel.com>\n---\n drivers/net/ice/base/ice_controlq.c | 107 +++++++++++++++-------------\n drivers/net/ice/base/ice_controlq.h | 3 -\n 2 files changed, 56 insertions(+), 54 deletions(-)", "diff": "diff --git a/drivers/net/ice/base/ice_controlq.c b/drivers/net/ice/base/ice_controlq.c\nindex c34407b48c..acd6ad249b 100644\n--- a/drivers/net/ice/base/ice_controlq.c\n+++ b/drivers/net/ice/base/ice_controlq.c\n@@ -101,13 +101,6 @@ ice_alloc_ctrlq_sq_ring(struct ice_hw *hw, struct ice_ctl_q_info *cq)\n \tif (!cq->sq.desc_buf.va)\n \t\treturn ICE_ERR_NO_MEMORY;\n \n-\tcq->sq.cmd_buf = ice_calloc(hw, cq->num_sq_entries,\n-\t\t\t\t sizeof(struct ice_sq_cd));\n-\tif (!cq->sq.cmd_buf) {\n-\t\tice_free_dma_mem(hw, &cq->sq.desc_buf);\n-\t\treturn ICE_ERR_NO_MEMORY;\n-\t}\n-\n \treturn ICE_SUCCESS;\n }\n \n@@ -176,7 +169,7 @@ ice_alloc_rq_bufs(struct ice_hw *hw, struct ice_ctl_q_info *cq)\n \t\tif (cq->rq_buf_size > ICE_AQ_LG_BUF)\n \t\t\tdesc->flags |= CPU_TO_LE16(ICE_AQ_FLAG_LB);\n \t\tdesc->opcode = 0;\n-\t\t/* This is in accordance with Admin queue design, there is no\n+\t\t/* This is in accordance with control queue design, there is no\n \t\t * register for buffer size configuration\n \t\t */\n \t\tdesc->datalen = CPU_TO_LE16(bi->size);\n@@ -309,9 +302,6 @@ do {\t\t\t\t\t\t\t\t\t\\\n \t\t\t\tice_free_dma_mem((hw),\t\t\t\\\n \t\t\t\t\t&(qi)->ring.r.ring##_bi[i]);\t\\\n \t}\t\t\t\t\t\t\t\t\\\n-\t/* free the buffer info list */\t\t\t\t\t\\\n-\tif ((qi)->ring.cmd_buf)\t\t\t\t\t\t\\\n-\t\tice_free(hw, (qi)->ring.cmd_buf);\t\t\t\\\n \t/* free DMA head */\t\t\t\t\t\t\\\n \tice_free(hw, (qi)->ring.dma_head);\t\t\t\t\\\n } while (0)\n@@ -379,11 +369,11 @@ static enum ice_status ice_init_sq(struct ice_hw *hw, struct ice_ctl_q_info *cq)\n }\n \n /**\n- * ice_init_rq - initialize ARQ\n+ * ice_init_rq - initialize receive side of a control queue\n * @hw: pointer to the hardware structure\n * @cq: pointer to the specific Control queue\n *\n- * The main initialization routine for the Admin Receive (Event) Queue.\n+ * The main initialization routine for Receive side of a control queue.\n * Prior to calling this function, the driver *MUST* set the following fields\n * in the cq->structure:\n * - cq->num_rq_entries\n@@ -441,7 +431,7 @@ static enum ice_status ice_init_rq(struct ice_hw *hw, struct ice_ctl_q_info *cq)\n }\n \n /**\n- * ice_shutdown_sq - shutdown the Control ATQ\n+ * ice_shutdown_sq - shutdown the transmit side of a control queue\n * @hw: pointer to the hardware structure\n * @cq: pointer to the specific Control queue\n *\n@@ -461,7 +451,7 @@ ice_shutdown_sq(struct ice_hw *hw, struct ice_ctl_q_info *cq)\n \t\tgoto shutdown_sq_out;\n \t}\n \n-\t/* Stop firmware AdminQ processing */\n+\t/* Stop processing of the control queue */\n \twr32(hw, cq->sq.head, 0);\n \twr32(hw, cq->sq.tail, 0);\n \twr32(hw, cq->sq.len, 0);\n@@ -834,7 +824,7 @@ void ice_destroy_all_ctrlq(struct ice_hw *hw)\n }\n \n /**\n- * ice_clean_sq - cleans Admin send queue (ATQ)\n+ * ice_clean_sq - cleans send side of a control queue\n * @hw: pointer to the hardware structure\n * @cq: pointer to the specific Control queue\n *\n@@ -844,21 +834,17 @@ static u16 ice_clean_sq(struct ice_hw *hw, struct ice_ctl_q_info *cq)\n {\n \tstruct ice_ctl_q_ring *sq = &cq->sq;\n \tu16 ntc = sq->next_to_clean;\n-\tstruct ice_sq_cd *details;\n \tstruct ice_aq_desc *desc;\n \n \tdesc = ICE_CTL_Q_DESC(*sq, ntc);\n-\tdetails = ICE_CTL_Q_DETAILS(*sq, ntc);\n \n \twhile (rd32(hw, cq->sq.head) != ntc) {\n \t\tice_debug(hw, ICE_DBG_AQ_MSG, \"ntc %d head %d.\\n\", ntc, rd32(hw, cq->sq.head));\n \t\tice_memset(desc, 0, sizeof(*desc), ICE_DMA_MEM);\n-\t\tice_memset(details, 0, sizeof(*details), ICE_NONDMA_MEM);\n \t\tntc++;\n \t\tif (ntc == sq->count)\n \t\t\tntc = 0;\n \t\tdesc = ICE_CTL_Q_DESC(*sq, ntc);\n-\t\tdetails = ICE_CTL_Q_DETAILS(*sq, ntc);\n \t}\n \n \tsq->next_to_clean = ntc;\n@@ -866,16 +852,42 @@ static u16 ice_clean_sq(struct ice_hw *hw, struct ice_ctl_q_info *cq)\n \treturn ICE_CTL_Q_DESC_UNUSED(sq);\n }\n \n+/**\n+ * ice_ctl_q_str - Convert control queue type to string\n+ * @qtype: the control queue type\n+ *\n+ * Returns: A string name for the given control queue type.\n+ */\n+static const char *ice_ctl_q_str(enum ice_ctl_q qtype)\n+{\n+\tswitch (qtype) {\n+\tcase ICE_CTL_Q_UNKNOWN:\n+\t\treturn \"Unknown CQ\";\n+\tcase ICE_CTL_Q_ADMIN:\n+\t\treturn \"AQ\";\n+\tcase ICE_CTL_Q_MAILBOX:\n+\t\treturn \"MBXQ\";\n+\tcase ICE_CTL_Q_SB:\n+\t\treturn \"SBQ\";\n+\tdefault:\n+\t\treturn \"Unrecognized CQ\";\n+\t}\n+}\n+\n /**\n * ice_debug_cq\n * @hw: pointer to the hardware structure\n+ * @cq: pointer to the specific Control queue\n * @desc: pointer to control queue descriptor\n * @buf: pointer to command buffer\n * @buf_len: max length of buf\n+ * @response: true if this is the writeback response\n *\n * Dumps debug log about control command with descriptor contents.\n */\n-static void ice_debug_cq(struct ice_hw *hw, void *desc, void *buf, u16 buf_len)\n+static void\n+ice_debug_cq(struct ice_hw *hw, struct ice_ctl_q_info *cq,\n+\t void *desc, void *buf, u16 buf_len, bool response)\n {\n \tstruct ice_aq_desc *cq_desc = (struct ice_aq_desc *)desc;\n \tu16 datalen, flags;\n@@ -889,7 +901,8 @@ static void ice_debug_cq(struct ice_hw *hw, void *desc, void *buf, u16 buf_len)\n \tdatalen = LE16_TO_CPU(cq_desc->datalen);\n \tflags = LE16_TO_CPU(cq_desc->flags);\n \n-\tice_debug(hw, ICE_DBG_AQ_DESC, \"CQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\\n\",\n+\tice_debug(hw, ICE_DBG_AQ_DESC, \"%s %s: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\\n\",\n+\t\t ice_ctl_q_str(cq->qtype), response ? \"Response\" : \"Command\",\n \t\t LE16_TO_CPU(cq_desc->opcode), flags, datalen,\n \t\t LE16_TO_CPU(cq_desc->retval));\n \tice_debug(hw, ICE_DBG_AQ_DESC, \"\\tcookie (h,l) 0x%08X 0x%08X\\n\",\n@@ -914,23 +927,23 @@ static void ice_debug_cq(struct ice_hw *hw, void *desc, void *buf, u16 buf_len)\n }\n \n /**\n- * ice_sq_done - check if FW has processed the Admin Send Queue (ATQ)\n+ * ice_sq_done - check if the last send on a control queue has completed\n * @hw: pointer to the HW struct\n * @cq: pointer to the specific Control queue\n *\n- * Returns true if the firmware has processed all descriptors on the\n- * admin send queue. Returns false if there are still requests pending.\n+ * Returns: true if all the descriptors on the send side of a control queue\n+ * are finished processing, false otherwise.\n */\n static bool ice_sq_done(struct ice_hw *hw, struct ice_ctl_q_info *cq)\n {\n-\t/* AQ designers suggest use of head for better\n+\t/* control queue designers suggest use of head for better\n \t * timing reliability than DD bit\n \t */\n \treturn rd32(hw, cq->sq.head) == cq->sq.next_to_use;\n }\n \n /**\n- * ice_sq_send_cmd_nolock - send command to Control Queue (ATQ)\n+ * ice_sq_send_cmd_nolock - send command to a control queue\n * @hw: pointer to the HW struct\n * @cq: pointer to the specific Control queue\n * @desc: prefilled descriptor describing the command (non DMA mem)\n@@ -938,8 +951,9 @@ static bool ice_sq_done(struct ice_hw *hw, struct ice_ctl_q_info *cq)\n * @buf_size: size of buffer for indirect commands (or 0 for direct commands)\n * @cd: pointer to command details structure\n *\n- * This is the main send command routine for the ATQ. It runs the queue,\n- * cleans the queue, etc.\n+ * This is the main send command routine for a control queue. It prepares the\n+ * command into a descriptor, bumps the send queue tail, waits for the command\n+ * to complete, captures status and data for the command, etc.\n */\n enum ice_status\n ice_sq_send_cmd_nolock(struct ice_hw *hw, struct ice_ctl_q_info *cq,\n@@ -950,7 +964,6 @@ ice_sq_send_cmd_nolock(struct ice_hw *hw, struct ice_ctl_q_info *cq,\n \tstruct ice_aq_desc *desc_on_ring;\n \tbool cmd_completed = false;\n \tenum ice_status status = ICE_SUCCESS;\n-\tstruct ice_sq_cd *details;\n \tu32 total_delay = 0;\n \tu16 retval = 0;\n \tu32 val = 0;\n@@ -993,12 +1006,6 @@ ice_sq_send_cmd_nolock(struct ice_hw *hw, struct ice_ctl_q_info *cq,\n \t\tgoto sq_send_command_error;\n \t}\n \n-\tdetails = ICE_CTL_Q_DETAILS(cq->sq, cq->sq.next_to_use);\n-\tif (cd)\n-\t\t*details = *cd;\n-\telse\n-\t\tice_memset(details, 0, sizeof(*details), ICE_NONDMA_MEM);\n-\n \t/* Call clean and check queue available function to reclaim the\n \t * descriptors that were processed by FW/MBX; the function returns the\n \t * number of desc available. The clean function called here could be\n@@ -1035,8 +1042,7 @@ ice_sq_send_cmd_nolock(struct ice_hw *hw, struct ice_ctl_q_info *cq,\n \n \t/* Debug desc and buffer */\n \tice_debug(hw, ICE_DBG_AQ_DESC, \"ATQ: Control Send queue desc and buffer:\\n\");\n-\n-\tice_debug_cq(hw, (void *)desc_on_ring, buf, buf_size);\n+\tice_debug_cq(hw, cq, (void *)desc_on_ring, buf, buf_size, false);\n \n \t(cq->sq.next_to_use)++;\n \tif (cq->sq.next_to_use == cq->sq.count)\n@@ -1084,13 +1090,12 @@ ice_sq_send_cmd_nolock(struct ice_hw *hw, struct ice_ctl_q_info *cq,\n \t}\n \n \tice_debug(hw, ICE_DBG_AQ_MSG, \"ATQ: desc and buffer writeback:\\n\");\n-\n-\tice_debug_cq(hw, (void *)desc, buf, buf_size);\n+\tice_debug_cq(hw, cq, (void *)desc, buf, buf_size, true);\n \n \t/* save writeback AQ if requested */\n-\tif (details->wb_desc)\n-\t\tice_memcpy(details->wb_desc, desc_on_ring,\n-\t\t\t sizeof(*details->wb_desc), ICE_DMA_TO_NONDMA);\n+\tif (cd && cd->wb_desc)\n+\t\tice_memcpy(cd->wb_desc, desc_on_ring,\n+\t\t\t sizeof(*cd->wb_desc), ICE_DMA_TO_NONDMA);\n \n \t/* update the error if time out occurred */\n \tif (!cmd_completed) {\n@@ -1109,7 +1114,7 @@ ice_sq_send_cmd_nolock(struct ice_hw *hw, struct ice_ctl_q_info *cq,\n }\n \n /**\n- * ice_sq_send_cmd - send command to Control Queue (ATQ)\n+ * ice_sq_send_cmd - send command to a control queue\n * @hw: pointer to the HW struct\n * @cq: pointer to the specific Control queue\n * @desc: prefilled descriptor describing the command\n@@ -1117,8 +1122,9 @@ ice_sq_send_cmd_nolock(struct ice_hw *hw, struct ice_ctl_q_info *cq,\n * @buf_size: size of buffer for indirect commands (or 0 for direct commands)\n * @cd: pointer to command details structure\n *\n- * This is the main send command routine for the ATQ. It runs the queue,\n- * cleans the queue, etc.\n+ * Main command for the transmit side of a control queue. It puts the command\n+ * on the queue, bumps the tail, waits for processing of the command, captures\n+ * command status and results, etc.\n */\n enum ice_status\n ice_sq_send_cmd(struct ice_hw *hw, struct ice_ctl_q_info *cq,\n@@ -1160,9 +1166,9 @@ void ice_fill_dflt_direct_cmd_desc(struct ice_aq_desc *desc, u16 opcode)\n * @e: event info from the receive descriptor, includes any buffers\n * @pending: number of events that could be left to process\n *\n- * This function cleans one Admin Receive Queue element and returns\n- * the contents through e. It can also return how many events are\n- * left to process through 'pending'.\n+ * Clean one element from the receive side of a control queue. On return 'e'\n+ * contains contents of the message, and 'pending' contains the number of\n+ * events left to process.\n */\n enum ice_status\n ice_clean_rq_elem(struct ice_hw *hw, struct ice_ctl_q_info *cq,\n@@ -1218,8 +1224,7 @@ ice_clean_rq_elem(struct ice_hw *hw, struct ice_ctl_q_info *cq,\n \t\t\t e->msg_len, ICE_DMA_TO_NONDMA);\n \n \tice_debug(hw, ICE_DBG_AQ_DESC, \"ARQ: desc and buffer:\\n\");\n-\n-\tice_debug_cq(hw, (void *)desc, e->msg_buf, cq->rq_buf_size);\n+\tice_debug_cq(hw, cq, (void *)desc, e->msg_buf, cq->rq_buf_size, true);\n \n \t/* Restore the original datalen and buffer address in the desc,\n \t * FW updates datalen to indicate the event message size\ndiff --git a/drivers/net/ice/base/ice_controlq.h b/drivers/net/ice/base/ice_controlq.h\nindex 986604ec3c..5c60469693 100644\n--- a/drivers/net/ice/base/ice_controlq.h\n+++ b/drivers/net/ice/base/ice_controlq.h\n@@ -43,7 +43,6 @@ enum ice_ctl_q {\n struct ice_ctl_q_ring {\n \tvoid *dma_head;\t\t\t/* Virtual address to DMA head */\n \tstruct ice_dma_mem desc_buf;\t/* descriptor ring memory */\n-\tvoid *cmd_buf;\t\t\t/* command buffer memory */\n \n \tunion {\n \t\tstruct ice_dma_mem *sq_bi;\n@@ -73,8 +72,6 @@ struct ice_sq_cd {\n \tstruct ice_aq_desc *wb_desc;\n };\n \n-#define ICE_CTL_Q_DETAILS(R, i) (&(((struct ice_sq_cd *)((R).cmd_buf))[i]))\n-\n /* rq event information */\n struct ice_rq_event_info {\n \tstruct ice_aq_desc desc;\n", "prefixes": [ "03/30" ] }