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GET /api/patches/126465/?format=api
{ "id": 126465, "url": "http://patches.dpdk.org/api/patches/126465/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20230424122835.39493-10-sedara@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20230424122835.39493-10-sedara@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20230424122835.39493-10-sedara@marvell.com", "date": "2023-04-24T12:28:32", "name": "[v3,09/11] net/octeon_ep: support mailbox between VF and PF", "commit_ref": null, "pull_url": null, "state": "not-applicable", "archived": true, "hash": "c88f40740b5ace20606478b9a72ff2c50ceab007", "submitter": { "id": 2729, "url": "http://patches.dpdk.org/api/people/2729/?format=api", "name": "Sathesh B Edara", "email": "sedara@marvell.com" }, "delegate": { "id": 310, "url": "http://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20230424122835.39493-10-sedara@marvell.com/mbox/", "series": [ { "id": 27844, "url": "http://patches.dpdk.org/api/series/27844/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=27844", "date": "2023-04-24T12:28:24", "name": "extend octeon ep driver functionality", "version": 3, "mbox": "http://patches.dpdk.org/series/27844/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/126465/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/126465/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 7B9DA429DB;\n\tMon, 24 Apr 2023 14:29:23 +0200 (CEST)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id BB59442D33;\n\tMon, 24 Apr 2023 14:29:04 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n [67.231.156.173])\n by mails.dpdk.org (Postfix) with ESMTP id 1EA9042D0C\n for <dev@dpdk.org>; Mon, 24 Apr 2023 14:29:02 +0200 (CEST)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n by mx0b-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id\n 33OAB8Ys006457 for <dev@dpdk.org>; Mon, 24 Apr 2023 05:29:01 -0700", "from dc5-exch02.marvell.com ([199.233.59.182])\n by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3q4f3p622p-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Mon, 24 Apr 2023 05:29:01 -0700", "from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.48;\n Mon, 24 Apr 2023 05:28:58 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.48 via Frontend\n Transport; Mon, 24 Apr 2023 05:28:58 -0700", "from localhost.marvell.com (unknown [10.106.27.249])\n by maili.marvell.com (Postfix) with ESMTP id 758CF3F70A0;\n Mon, 24 Apr 2023 05:28:58 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-transfer-encoding : content-type; s=pfpt0220;\n bh=gd9daRroH1MK4nFamVueFGnik0ox0P61dT8IBHKmXjM=;\n b=O+ehuL8/tzLhtCrc4dhtHvYVt1p3/BqbDj92uYm9kZerkofDKpX/q2OJmq6bnT3qZdPD\n +sKSOXzfLFbVCUzrcVF1BKe+lFQX2rcO3vW6n7tFabBrQmxTFpJaCyrtXgzNmRWDtFsP\n 4YwcLlAZtJiSCvphdJsyGM6xas6pyatjGV1zGC/pdeLJubnlJpOj0R1b5qvTvOdojnBa\n tH9/Dm4iDVbh7y/4wS9Vj151BL4S5e4ZCvl+zem9iag33L/WDzfmKy0c+ipEEZxAAY+q\n cID7md31GSn6cbamDQjK1YX9Ld+/1oNziWGProtlVCGXxQVxsBg3uPwjy3gVVErjUWyY tQ==", "From": "Sathesh Edara <sedara@marvell.com>", "To": "<sburla@marvell.com>, <jerinj@marvell.com>, <sedara@marvell.com>, \"Radha\n Mohan Chintakuntla\" <radhac@marvell.com>, Veerasenareddy Burru\n <vburru@marvell.com>", "CC": "<dev@dpdk.org>", "Subject": "[PATCH v3 09/11] net/octeon_ep: support mailbox between VF and PF", "Date": "Mon, 24 Apr 2023 05:28:32 -0700", "Message-ID": "<20230424122835.39493-10-sedara@marvell.com>", "X-Mailer": "git-send-email 2.31.1", "In-Reply-To": "<20230424122835.39493-1-sedara@marvell.com>", "References": "<20230405142537.1899973-2-sedara@marvell.com>\n <20230424122835.39493-1-sedara@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-ORIG-GUID": "eM2csWKX35_-ty0RSdLPLPC2LnaTVdi_", "X-Proofpoint-GUID": "eM2csWKX35_-ty0RSdLPLPC2LnaTVdi_", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.254,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22\n definitions=2023-04-24_07,2023-04-21_01,2023-02-09_01", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Adds the mailbox communication between VF and\nPF and supports the following mailbox messages.\n- Get and set MAC address\n- Get link information\n- Get stats\n- Set and get MTU\n- Send notification to PF\n\nSigned-off-by: Sathesh Edara <sedara@marvell.com>\n---\n doc/guides/nics/features/octeon_ep.ini | 1 +\n drivers/net/octeon_ep/cnxk_ep_vf.c | 1 +\n drivers/net/octeon_ep/cnxk_ep_vf.h | 12 +-\n drivers/net/octeon_ep/meson.build | 1 +\n drivers/net/octeon_ep/otx_ep_common.h | 26 +++\n drivers/net/octeon_ep/otx_ep_ethdev.c | 143 +++++++++++-\n drivers/net/octeon_ep/otx_ep_mbox.c | 309 +++++++++++++++++++++++++\n drivers/net/octeon_ep/otx_ep_mbox.h | 163 +++++++++++++\n 8 files changed, 643 insertions(+), 13 deletions(-)\n create mode 100644 drivers/net/octeon_ep/otx_ep_mbox.c\n create mode 100644 drivers/net/octeon_ep/otx_ep_mbox.h", "diff": "diff --git a/doc/guides/nics/features/octeon_ep.ini b/doc/guides/nics/features/octeon_ep.ini\nindex 305e219262..f3b821c89e 100644\n--- a/doc/guides/nics/features/octeon_ep.ini\n+++ b/doc/guides/nics/features/octeon_ep.ini\n@@ -10,4 +10,5 @@ Linux = Y\n x86-64 = Y\n Basic stats = Y\n Link status = Y\n+MTU update = Y\n Usage doc = Y\ndiff --git a/drivers/net/octeon_ep/cnxk_ep_vf.c b/drivers/net/octeon_ep/cnxk_ep_vf.c\nindex a437ae68cb..cadb4ecbf9 100644\n--- a/drivers/net/octeon_ep/cnxk_ep_vf.c\n+++ b/drivers/net/octeon_ep/cnxk_ep_vf.c\n@@ -8,6 +8,7 @@\n #include <rte_common.h>\n #include <rte_cycles.h>\n #include <rte_memzone.h>\n+#include \"otx_ep_common.h\"\n #include \"cnxk_ep_vf.h\"\n \n static void\ndiff --git a/drivers/net/octeon_ep/cnxk_ep_vf.h b/drivers/net/octeon_ep/cnxk_ep_vf.h\nindex 072b38ea15..86277449ea 100644\n--- a/drivers/net/octeon_ep/cnxk_ep_vf.h\n+++ b/drivers/net/octeon_ep/cnxk_ep_vf.h\n@@ -5,7 +5,7 @@\n #define _CNXK_EP_VF_H_\n \n #include <rte_io.h>\n-#include \"otx_ep_common.h\"\n+\n #define CNXK_CONFIG_XPANSION_BAR 0x38\n #define CNXK_CONFIG_PCIE_CAP 0x70\n #define CNXK_CONFIG_PCIE_DEVCAP 0x74\n@@ -92,6 +92,10 @@\n #define CNXK_EP_R_OUT_BYTE_CNT_START 0x10190\n #define CNXK_EP_R_OUT_CNTS_ISM_START 0x10510\n \n+#define CNXK_EP_R_MBOX_PF_VF_DATA_START 0x10210\n+#define CNXK_EP_R_MBOX_VF_PF_DATA_START 0x10230\n+#define CNXK_EP_R_MBOX_PF_VF_INT_START 0x10220\n+\n #define CNXK_EP_R_OUT_CNTS(ring) \\\n \t(CNXK_EP_R_OUT_CNTS_START + ((ring) * CNXK_EP_RING_OFFSET))\n \n@@ -125,6 +129,12 @@\n #define CNXK_EP_R_OUT_CNTS_ISM(ring) \\\n \t(CNXK_EP_R_OUT_CNTS_ISM_START + ((ring) * CNXK_EP_RING_OFFSET))\n \n+#define CNXK_EP_R_MBOX_VF_PF_DATA(ring) \\\n+\t(CNXK_EP_R_MBOX_VF_PF_DATA_START + ((ring) * CNXK_EP_RING_OFFSET))\n+\n+#define CNXK_EP_R_MBOX_PF_VF_INT(ring) \\\n+\t(CNXK_EP_R_MBOX_PF_VF_INT_START + ((ring) * CNXK_EP_RING_OFFSET))\n+\n /*------------------ R_OUT Masks ----------------*/\n #define CNXK_EP_R_OUT_INT_LEVELS_BMODE (1ULL << 63)\n #define CNXK_EP_R_OUT_INT_LEVELS_TIMET (32)\ndiff --git a/drivers/net/octeon_ep/meson.build b/drivers/net/octeon_ep/meson.build\nindex a267b60290..e698bf9792 100644\n--- a/drivers/net/octeon_ep/meson.build\n+++ b/drivers/net/octeon_ep/meson.build\n@@ -8,4 +8,5 @@ sources = files(\n 'otx_ep_vf.c',\n 'otx2_ep_vf.c',\n 'cnxk_ep_vf.c',\n+ 'otx_ep_mbox.c',\n )\ndiff --git a/drivers/net/octeon_ep/otx_ep_common.h b/drivers/net/octeon_ep/otx_ep_common.h\nindex 3582f3087b..dadc8d1579 100644\n--- a/drivers/net/octeon_ep/otx_ep_common.h\n+++ b/drivers/net/octeon_ep/otx_ep_common.h\n@@ -4,6 +4,7 @@\n #ifndef _OTX_EP_COMMON_H_\n #define _OTX_EP_COMMON_H_\n \n+#include <rte_spinlock.h>\n \n #define OTX_EP_NW_PKT_OP 0x1220\n #define OTX_EP_NW_CMD_OP 0x1221\n@@ -67,6 +68,9 @@\n #define oct_ep_read64(addr) rte_read64_relaxed((void *)(addr))\n #define oct_ep_write64(val, addr) rte_write64_relaxed((val), (void *)(addr))\n \n+/* Mailbox maximum data size */\n+#define MBOX_MAX_DATA_BUF_SIZE 320\n+\n /* Input Request Header format */\n union otx_ep_instr_irh {\n \tuint64_t u64;\n@@ -488,6 +492,18 @@ struct otx_ep_device {\n \n \t/* DMA buffer for SDP ISM messages */\n \tconst struct rte_memzone *ism_buffer_mz;\n+\n+\t/* Mailbox lock */\n+\trte_spinlock_t mbox_lock;\n+\n+\t/* Mailbox data */\n+\tuint8_t mbox_data_buf[MBOX_MAX_DATA_BUF_SIZE];\n+\n+\t/* Mailbox data index */\n+\tint32_t mbox_data_index;\n+\n+\t/* Mailbox receive message length */\n+\tint32_t mbox_rcv_message_len;\n };\n \n int otx_ep_setup_iqs(struct otx_ep_device *otx_ep, uint32_t iq_no,\n@@ -541,6 +557,16 @@ struct otx_ep_buf_free_info {\n #define OTX_EP_CLEAR_SLIST_DBELL 0xFFFFFFFF\n #define OTX_EP_CLEAR_SDP_OUT_PKT_CNT 0xFFFFFFFFF\n \n+/* Max overhead includes\n+ * - Ethernet hdr\n+ * - CRC\n+ * - nested VLANs\n+ * - octeon rx info\n+ */\n+#define OTX_EP_ETH_OVERHEAD \\\n+\t(RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN + \\\n+\t (2 * RTE_VLAN_HLEN) + OTX_EP_DROQ_INFO_SIZE)\n+\n /* PCI IDs */\n #define PCI_VENDOR_ID_CAVIUM\t\t\t0x177D\n \ndiff --git a/drivers/net/octeon_ep/otx_ep_ethdev.c b/drivers/net/octeon_ep/otx_ep_ethdev.c\nindex 0f710b1ffa..885fbb475f 100644\n--- a/drivers/net/octeon_ep/otx_ep_ethdev.c\n+++ b/drivers/net/octeon_ep/otx_ep_ethdev.c\n@@ -10,6 +10,7 @@\n #include \"otx2_ep_vf.h\"\n #include \"cnxk_ep_vf.h\"\n #include \"otx_ep_rxtx.h\"\n+#include \"otx_ep_mbox.h\"\n \n #define OTX_EP_DEV(_eth_dev) \\\n \t((struct otx_ep_device *)(_eth_dev)->data->dev_private)\n@@ -31,15 +32,24 @@ otx_ep_dev_info_get(struct rte_eth_dev *eth_dev,\n \t\t struct rte_eth_dev_info *devinfo)\n {\n \tstruct otx_ep_device *otx_epvf;\n+\tint max_rx_pktlen;\n \n \totx_epvf = OTX_EP_DEV(eth_dev);\n \n+\tmax_rx_pktlen = otx_ep_mbox_get_max_pkt_len(eth_dev);\n+\tif (!max_rx_pktlen) {\n+\t\totx_ep_err(\"Failed to get Max Rx packet length\");\n+\t\treturn -EINVAL;\n+\t}\n+\n \tdevinfo->speed_capa = RTE_ETH_LINK_SPEED_10G;\n \tdevinfo->max_rx_queues = otx_epvf->max_rx_queues;\n \tdevinfo->max_tx_queues = otx_epvf->max_tx_queues;\n \n \tdevinfo->min_rx_bufsize = OTX_EP_MIN_RX_BUF_SIZE;\n-\tdevinfo->max_rx_pktlen = OTX_EP_MAX_PKT_SZ;\n+\tdevinfo->max_rx_pktlen = max_rx_pktlen;\n+\tdevinfo->max_mtu = devinfo->max_rx_pktlen - OTX_EP_ETH_OVERHEAD;\n+\tdevinfo->min_mtu = RTE_ETHER_MIN_LEN;\n \tdevinfo->rx_offload_capa = RTE_ETH_RX_OFFLOAD_SCATTER;\n \tdevinfo->tx_offload_capa = RTE_ETH_TX_OFFLOAD_MULTI_SEGS;\n \n@@ -54,6 +64,71 @@ otx_ep_dev_info_get(struct rte_eth_dev *eth_dev,\n \treturn 0;\n }\n \n+static int\n+otx_ep_dev_link_update(struct rte_eth_dev *eth_dev, int wait_to_complete)\n+{\n+\tRTE_SET_USED(wait_to_complete);\n+\n+\tif (!eth_dev->data->dev_started)\n+\t\treturn 0;\n+\tstruct rte_eth_link link;\n+\tint ret = 0;\n+\n+\tmemset(&link, 0, sizeof(link));\n+\tret = otx_ep_mbox_get_link_info(eth_dev, &link);\n+\tif (ret)\n+\t\treturn -EINVAL;\n+\totx_ep_dbg(\"link status resp link %d duplex %d autoneg %d link_speed %d\\n\",\n+\t\t link.link_status, link.link_duplex, link.link_autoneg, link.link_speed);\n+\treturn rte_eth_linkstatus_set(eth_dev, &link);\n+}\n+\n+static int\n+otx_ep_dev_mtu_set(struct rte_eth_dev *eth_dev, uint16_t mtu)\n+{\n+\tstruct rte_eth_dev_info devinfo;\n+\tint32_t ret = 0;\n+\n+\tif (otx_ep_dev_info_get(eth_dev, &devinfo)) {\n+\t\totx_ep_err(\"Cannot set MTU to %u: failed to get device info\", mtu);\n+\t\treturn -EPERM;\n+\t}\n+\n+\t/* Check if MTU is within the allowed range */\n+\tif (mtu < devinfo.min_mtu) {\n+\t\totx_ep_err(\"Invalid MTU %u: lower than minimum MTU %u\", mtu, devinfo.min_mtu);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tif (mtu > devinfo.max_mtu) {\n+\t\totx_ep_err(\"Invalid MTU %u; higher than maximum MTU %u\", mtu, devinfo.max_mtu);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tret = otx_ep_mbox_set_mtu(eth_dev, mtu);\n+\tif (ret)\n+\t\treturn -EINVAL;\n+\n+\totx_ep_dbg(\"MTU is set to %u\", mtu);\n+\n+\treturn 0;\n+}\n+\n+static int\n+otx_ep_dev_set_default_mac_addr(struct rte_eth_dev *eth_dev,\n+\t\t\t\tstruct rte_ether_addr *mac_addr)\n+{\n+\tint ret;\n+\n+\tret = otx_ep_mbox_set_mac_addr(eth_dev, mac_addr);\n+\tif (ret)\n+\t\treturn -EINVAL;\n+\totx_ep_dbg(\"Default MAC address \" RTE_ETHER_ADDR_PRT_FMT \"\\n\",\n+\t\t RTE_ETHER_ADDR_BYTES(mac_addr));\n+\trte_ether_addr_copy(mac_addr, eth_dev->data->mac_addrs);\n+\treturn 0;\n+}\n+\n static int\n otx_ep_dev_start(struct rte_eth_dev *eth_dev)\n {\n@@ -78,6 +153,7 @@ otx_ep_dev_start(struct rte_eth_dev *eth_dev)\n \t\trte_read32(otx_epvf->droq[q]->pkts_credit_reg));\n \t}\n \n+\totx_ep_dev_link_update(eth_dev, 0);\n \totx_ep_info(\"dev started\\n\");\n \n \treturn 0;\n@@ -454,6 +530,7 @@ otx_ep_dev_close(struct rte_eth_dev *eth_dev)\n \tstruct otx_ep_device *otx_epvf = OTX_EP_DEV(eth_dev);\n \tuint32_t num_queues, q_no;\n \n+\totx_ep_mbox_send_dev_exit(eth_dev);\n \totx_epvf->fn_list.disable_io_queues(otx_epvf);\n \tnum_queues = otx_epvf->nb_rx_queues;\n \tfor (q_no = 0; q_no < num_queues; q_no++) {\n@@ -482,19 +559,17 @@ otx_ep_dev_close(struct rte_eth_dev *eth_dev)\n }\n \n static int\n-otx_ep_dev_link_update(struct rte_eth_dev *eth_dev, int wait_to_complete)\n+otx_ep_dev_get_mac_addr(struct rte_eth_dev *eth_dev,\n+\t\t\tstruct rte_ether_addr *mac_addr)\n {\n-\tRTE_SET_USED(wait_to_complete);\n-\n-\tif (!eth_dev->data->dev_started)\n-\t\treturn 0;\n-\tstruct rte_eth_link link;\n+\tint ret;\n \n-\tmemset(&link, 0, sizeof(link));\n-\tlink.link_status = RTE_ETH_LINK_UP;\n-\tlink.link_speed = RTE_ETH_SPEED_NUM_10G;\n-\tlink.link_duplex = RTE_ETH_LINK_FULL_DUPLEX;\n-\treturn rte_eth_linkstatus_set(eth_dev, &link);\n+\tret = otx_ep_mbox_get_mac_addr(eth_dev, mac_addr);\n+\tif (ret)\n+\t\treturn -EINVAL;\n+\totx_ep_dbg(\"Get MAC address \" RTE_ETHER_ADDR_PRT_FMT \"\\n\",\n+\t\t RTE_ETHER_ADDR_BYTES(mac_addr));\n+\treturn 0;\n }\n \n /* Define our ethernet definitions */\n@@ -511,6 +586,8 @@ static const struct eth_dev_ops otx_ep_eth_dev_ops = {\n \t.stats_reset\t\t= otx_ep_dev_stats_reset,\n \t.link_update\t\t= otx_ep_dev_link_update,\n \t.dev_close\t\t= otx_ep_dev_close,\n+\t.mtu_set\t\t= otx_ep_dev_mtu_set,\n+\t.mac_addr_set = otx_ep_dev_set_default_mac_addr,\n };\n \n static int\n@@ -526,6 +603,37 @@ otx_ep_eth_dev_uninit(struct rte_eth_dev *eth_dev)\n \treturn 0;\n }\n \n+static int otx_ep_eth_dev_query_set_vf_mac(struct rte_eth_dev *eth_dev,\n+\t\t\t\t\t struct rte_ether_addr *mac_addr)\n+{\n+\tint ret_val;\n+\n+\tmemset(mac_addr, 0, sizeof(struct rte_ether_addr));\n+\tret_val = otx_ep_dev_get_mac_addr(eth_dev, mac_addr);\n+\tif (!ret_val) {\n+\t\tif (!rte_is_valid_assigned_ether_addr(mac_addr)) {\n+\t\t\totx_ep_dbg(\"PF doesn't have valid VF MAC addr\" RTE_ETHER_ADDR_PRT_FMT \"\\n\",\n+\t\t\t\t RTE_ETHER_ADDR_BYTES(mac_addr));\n+\t\t\trte_eth_random_addr(mac_addr->addr_bytes);\n+\t\t\totx_ep_dbg(\"Setting Random MAC address\" RTE_ETHER_ADDR_PRT_FMT \"\\n\",\n+\t\t\t\t RTE_ETHER_ADDR_BYTES(mac_addr));\n+\t\t\tret_val = otx_ep_dev_set_default_mac_addr(eth_dev, mac_addr);\n+\t\t\tif (ret_val) {\n+\t\t\t\totx_ep_err(\"Setting MAC address \" RTE_ETHER_ADDR_PRT_FMT \"fails\\n\",\n+\t\t\t\t\t RTE_ETHER_ADDR_BYTES(mac_addr));\n+\t\t\t\treturn ret_val;\n+\t\t\t}\n+\t\t}\n+\t\totx_ep_dbg(\"Received valid MAC addr from PF\" RTE_ETHER_ADDR_PRT_FMT \"\\n\",\n+\t\t\t RTE_ETHER_ADDR_BYTES(mac_addr));\n+\t} else {\n+\t\totx_ep_err(\"Getting MAC address from PF via Mbox fails with ret_val: %d\\n\",\n+\t\t\t ret_val);\n+\t\treturn ret_val;\n+\t}\n+\treturn 0;\n+}\n+\n static int\n otx_ep_eth_dev_init(struct rte_eth_dev *eth_dev)\n {\n@@ -541,6 +649,7 @@ otx_ep_eth_dev_init(struct rte_eth_dev *eth_dev)\n \totx_epvf->eth_dev = eth_dev;\n \totx_epvf->port_id = eth_dev->data->port_id;\n \teth_dev->dev_ops = &otx_ep_eth_dev_ops;\n+\trte_spinlock_init(&otx_epvf->mbox_lock);\n \teth_dev->data->mac_addrs = rte_zmalloc(\"otx_ep\", RTE_ETHER_ADDR_LEN, 0);\n \tif (eth_dev->data->mac_addrs == NULL) {\n \t\totx_ep_err(\"MAC addresses memory allocation failed\\n\");\n@@ -572,6 +681,16 @@ otx_ep_eth_dev_init(struct rte_eth_dev *eth_dev)\n \t\treturn -EINVAL;\n \t}\n \n+\tif (otx_ep_mbox_version_check(eth_dev))\n+\t\treturn -EINVAL;\n+\n+\tif (otx_ep_eth_dev_query_set_vf_mac(eth_dev,\n+\t\t\t\t(struct rte_ether_addr *)&vf_mac_addr)) {\n+\t\totx_ep_err(\"set mac addr failed\\n\");\n+\t\treturn -ENODEV;\n+\t}\n+\trte_ether_addr_copy(&vf_mac_addr, eth_dev->data->mac_addrs);\n+\n \treturn 0;\n }\n \ndiff --git a/drivers/net/octeon_ep/otx_ep_mbox.c b/drivers/net/octeon_ep/otx_ep_mbox.c\nnew file mode 100644\nindex 0000000000..1ad36e14c8\n--- /dev/null\n+++ b/drivers/net/octeon_ep/otx_ep_mbox.c\n@@ -0,0 +1,309 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2021 Marvell.\n+ */\n+\n+#include <ethdev_pci.h>\n+#include <rte_ether.h>\n+#include <rte_kvargs.h>\n+\n+#include \"otx_ep_common.h\"\n+#include \"otx_ep_vf.h\"\n+#include \"otx2_ep_vf.h\"\n+#include \"cnxk_ep_vf.h\"\n+#include \"otx_ep_mbox.h\"\n+\n+static int\n+__otx_ep_send_mbox_cmd(struct otx_ep_device *otx_ep,\n+\t\t union otx_ep_mbox_word cmd,\n+\t\t union otx_ep_mbox_word *rsp)\n+{\n+\tvolatile uint64_t reg_val = 0ull;\n+\tint count = 0;\n+\n+\tcmd.s.type = OTX_EP_MBOX_TYPE_CMD;\n+\totx2_write64(cmd.u64, otx_ep->hw_addr + CNXK_EP_R_MBOX_VF_PF_DATA(0));\n+\n+\t/* No response for notification messages */\n+\tif (!rsp)\n+\t\treturn 0;\n+\n+\tfor (count = 0; count < OTX_EP_MBOX_TIMEOUT_MS; count++) {\n+\t\trte_delay_ms(1);\n+\t\treg_val = otx2_read64(otx_ep->hw_addr + CNXK_EP_R_MBOX_VF_PF_DATA(0));\n+\t\tif (reg_val != cmd.u64) {\n+\t\t\trsp->u64 = reg_val;\n+\t\t\tbreak;\n+\t\t}\n+\t}\n+\tif (count == OTX_EP_MBOX_TIMEOUT_MS) {\n+\t\totx_ep_err(\"mbox send Timeout count:%d\\n\", count);\n+\t\treturn OTX_EP_MBOX_TIMEOUT_MS;\n+\t}\n+\tif (rsp->s.type != OTX_EP_MBOX_TYPE_RSP_ACK) {\n+\t\totx_ep_err(\"mbox received NACK from PF\\n\");\n+\t\treturn OTX_EP_MBOX_CMD_STATUS_NACK;\n+\t}\n+\n+\trsp->u64 = reg_val;\n+\treturn 0;\n+}\n+\n+static int\n+otx_ep_send_mbox_cmd(struct otx_ep_device *otx_ep,\n+\t\t union otx_ep_mbox_word cmd,\n+\t\t union otx_ep_mbox_word *rsp)\n+{\n+\tint ret;\n+\n+\trte_spinlock_lock(&otx_ep->mbox_lock);\n+\tret = __otx_ep_send_mbox_cmd(otx_ep, cmd, rsp);\n+\trte_spinlock_unlock(&otx_ep->mbox_lock);\n+\treturn ret;\n+}\n+\n+static int\n+otx_ep_mbox_bulk_read(struct otx_ep_device *otx_ep,\n+\t\t enum otx_ep_mbox_opcode opcode,\n+\t\t uint8_t *data, int32_t *size)\n+{\n+\tunion otx_ep_mbox_word cmd;\n+\tunion otx_ep_mbox_word rsp;\n+\tint read_cnt, i = 0, ret;\n+\tint data_len = 0, tmp_len = 0;\n+\n+\trte_spinlock_lock(&otx_ep->mbox_lock);\n+\tcmd.u64 = 0;\n+\tcmd.s_data.opcode = opcode;\n+\tcmd.s_data.frag = 0;\n+\t/* Send cmd to read data from PF */\n+\tret = __otx_ep_send_mbox_cmd(otx_ep, cmd, &rsp);\n+\tif (ret) {\n+\t\totx_ep_err(\"mbox bulk read data request failed\\n\");\n+\t\trte_spinlock_unlock(&otx_ep->mbox_lock);\n+\t\treturn ret;\n+\t}\n+\t/* PF sends the data length of requested CMD\n+\t * in ACK\n+\t */\n+\tmemcpy(&data_len, rsp.s_data.data, sizeof(data_len));\n+\ttmp_len = data_len;\n+\tcmd.u64 = 0;\n+\trsp.u64 = 0;\n+\tcmd.s_data.opcode = opcode;\n+\tcmd.s_data.frag = 1;\n+\twhile (data_len) {\n+\t\tret = __otx_ep_send_mbox_cmd(otx_ep, cmd, &rsp);\n+\t\tif (ret) {\n+\t\t\totx_ep_err(\"mbox bulk read data request failed\\n\");\n+\t\t\totx_ep->mbox_data_index = 0;\n+\t\t\tmemset(otx_ep->mbox_data_buf, 0, OTX_EP_MBOX_MAX_DATA_BUF_SIZE);\n+\t\t\trte_spinlock_unlock(&otx_ep->mbox_lock);\n+\t\t\treturn ret;\n+\t\t}\n+\t\tif (data_len > OTX_EP_MBOX_MAX_DATA_SIZE) {\n+\t\t\tdata_len -= OTX_EP_MBOX_MAX_DATA_SIZE;\n+\t\t\tread_cnt = OTX_EP_MBOX_MAX_DATA_SIZE;\n+\t\t} else {\n+\t\t\tread_cnt = data_len;\n+\t\t\tdata_len = 0;\n+\t\t}\n+\t\tfor (i = 0; i < read_cnt; i++) {\n+\t\t\totx_ep->mbox_data_buf[otx_ep->mbox_data_index] =\n+\t\t\t\trsp.s_data.data[i];\n+\t\t\totx_ep->mbox_data_index++;\n+\t\t}\n+\t\tcmd.u64 = 0;\n+\t\trsp.u64 = 0;\n+\t\tcmd.s_data.opcode = opcode;\n+\t\tcmd.s_data.frag = 1;\n+\t}\n+\tmemcpy(data, otx_ep->mbox_data_buf, tmp_len);\n+\t*size = tmp_len;\n+\totx_ep->mbox_data_index = 0;\n+\tmemset(otx_ep->mbox_data_buf, 0, OTX_EP_MBOX_MAX_DATA_BUF_SIZE);\n+\trte_spinlock_unlock(&otx_ep->mbox_lock);\n+\treturn 0;\n+}\n+\n+int\n+otx_ep_mbox_set_mtu(struct rte_eth_dev *eth_dev, uint16_t mtu)\n+{\n+\tstruct otx_ep_device *otx_ep =\n+\t\t(struct otx_ep_device *)(eth_dev)->data->dev_private;\n+\tunion otx_ep_mbox_word cmd;\n+\tunion otx_ep_mbox_word rsp;\n+\tint ret = 0;\n+\n+\tcmd.u64 = 0;\n+\tcmd.s_set_mtu.opcode = OTX_EP_MBOX_CMD_SET_MTU;\n+\tcmd.s_set_mtu.mtu = mtu;\n+\n+\tret = otx_ep_send_mbox_cmd(otx_ep, cmd, &rsp);\n+\tif (ret) {\n+\t\totx_ep_err(\"set MTU failed\\n\");\n+\t\treturn -EINVAL;\n+\t}\n+\totx_ep_dbg(\"mtu set success mtu %u\\n\", mtu);\n+\n+\treturn 0;\n+}\n+\n+int\n+otx_ep_mbox_set_mac_addr(struct rte_eth_dev *eth_dev,\n+\t\t\t struct rte_ether_addr *mac_addr)\n+{\n+\tstruct otx_ep_device *otx_ep =\n+\t\t(struct otx_ep_device *)(eth_dev)->data->dev_private;\n+\tunion otx_ep_mbox_word cmd;\n+\tunion otx_ep_mbox_word rsp;\n+\tint i, ret;\n+\n+\tcmd.u64 = 0;\n+\tcmd.s_set_mac.opcode = OTX_EP_MBOX_CMD_SET_MAC_ADDR;\n+\tfor (i = 0; i < RTE_ETHER_ADDR_LEN; i++)\n+\t\tcmd.s_set_mac.mac_addr[i] = mac_addr->addr_bytes[i];\n+\tret = otx_ep_send_mbox_cmd(otx_ep, cmd, &rsp);\n+\tif (ret) {\n+\t\totx_ep_err(\"set MAC address failed\\n\");\n+\t\treturn -EINVAL;\n+\t}\n+\totx_ep_dbg(\"%s VF MAC \" RTE_ETHER_ADDR_PRT_FMT \"\\n\",\n+\t\t __func__, RTE_ETHER_ADDR_BYTES(mac_addr));\n+\trte_ether_addr_copy(mac_addr, eth_dev->data->mac_addrs);\n+\treturn 0;\n+}\n+\n+int\n+otx_ep_mbox_get_mac_addr(struct rte_eth_dev *eth_dev,\n+\t\t\t struct rte_ether_addr *mac_addr)\n+{\n+\tstruct otx_ep_device *otx_ep =\n+\t\t(struct otx_ep_device *)(eth_dev)->data->dev_private;\n+\tunion otx_ep_mbox_word cmd;\n+\tunion otx_ep_mbox_word rsp;\n+\tint i, ret;\n+\n+\tcmd.u64 = 0;\n+\tcmd.s_set_mac.opcode = OTX_EP_MBOX_CMD_GET_MAC_ADDR;\n+\tret = otx_ep_send_mbox_cmd(otx_ep, cmd, &rsp);\n+\tif (ret) {\n+\t\totx_ep_err(\"get MAC address failed\\n\");\n+\t\treturn -EINVAL;\n+\t}\n+\tfor (i = 0; i < RTE_ETHER_ADDR_LEN; i++)\n+\t\tmac_addr->addr_bytes[i] = rsp.s_set_mac.mac_addr[i];\n+\totx_ep_dbg(\"%s VF MAC \" RTE_ETHER_ADDR_PRT_FMT \"\\n\",\n+\t\t __func__, RTE_ETHER_ADDR_BYTES(mac_addr));\n+\treturn 0;\n+}\n+\n+int otx_ep_mbox_get_link_status(struct rte_eth_dev *eth_dev,\n+\t\t\t\tuint8_t *oper_up)\n+{\n+\tstruct otx_ep_device *otx_ep =\n+\t\t(struct otx_ep_device *)(eth_dev)->data->dev_private;\n+\tunion otx_ep_mbox_word cmd;\n+\tunion otx_ep_mbox_word rsp;\n+\tint ret;\n+\n+\tcmd.u64 = 0;\n+\tcmd.s_link_status.opcode = OTX_EP_MBOX_CMD_GET_LINK_STATUS;\n+\tret = otx_ep_send_mbox_cmd(otx_ep, cmd, &rsp);\n+\tif (ret) {\n+\t\totx_ep_err(\"Get link status failed\\n\");\n+\t\treturn -EINVAL;\n+\t}\n+\t*oper_up = rsp.s_link_status.status;\n+\treturn 0;\n+}\n+\n+int otx_ep_mbox_get_link_info(struct rte_eth_dev *eth_dev,\n+\t\t\t struct rte_eth_link *link)\n+{\n+\tint32_t ret, size;\n+\tstruct otx_ep_iface_link_info link_info;\n+\tstruct otx_ep_device *otx_ep =\n+\t\t(struct otx_ep_device *)(eth_dev)->data->dev_private;\n+\tmemset(&link_info, 0, sizeof(struct otx_ep_iface_link_info));\n+\tret = otx_ep_mbox_bulk_read(otx_ep, OTX_EP_MBOX_CMD_GET_LINK_INFO,\n+\t\t\t\t (uint8_t *)&link_info, (int32_t *)&size);\n+\tif (ret) {\n+\t\totx_ep_err(\"Get link info failed\\n\");\n+\t\treturn ret;\n+\t}\n+\tlink->link_status = RTE_ETH_LINK_UP;\n+\tlink->link_duplex = RTE_ETH_LINK_FULL_DUPLEX;\n+\tlink->link_autoneg = (link_info.autoneg ==\n+\t\t\t OTX_EP_LINK_AUTONEG) ? RTE_ETH_LINK_AUTONEG : RTE_ETH_LINK_FIXED;\n+\n+\tlink->link_autoneg = link_info.autoneg;\n+\tlink->link_speed = link_info.speed;\n+\treturn 0;\n+}\n+\n+void\n+otx_ep_mbox_enable_interrupt(struct otx_ep_device *otx_ep)\n+{\n+\trte_write64(0x2, (uint8_t *)otx_ep->hw_addr +\n+\t\t CNXK_EP_R_MBOX_PF_VF_INT(0));\n+}\n+\n+void\n+otx_ep_mbox_disable_interrupt(struct otx_ep_device *otx_ep)\n+{\n+\trte_write64(0x00, (uint8_t *)otx_ep->hw_addr +\n+\t\t CNXK_EP_R_MBOX_PF_VF_INT(0));\n+}\n+\n+int\n+otx_ep_mbox_get_max_pkt_len(struct rte_eth_dev *eth_dev)\n+{\n+\tstruct otx_ep_device *otx_ep =\n+\t\t(struct otx_ep_device *)(eth_dev)->data->dev_private;\n+\tunion otx_ep_mbox_word cmd;\n+\tunion otx_ep_mbox_word rsp;\n+\tint ret;\n+\n+\trsp.u64 = 0;\n+\tcmd.u64 = 0;\n+\tcmd.s_get_mtu.opcode = OTX_EP_MBOX_CMD_GET_MTU;\n+\n+\tret = otx_ep_send_mbox_cmd(otx_ep, cmd, &rsp);\n+\tif (ret)\n+\t\treturn ret;\n+\treturn rsp.s_get_mtu.mtu;\n+}\n+\n+int otx_ep_mbox_version_check(struct rte_eth_dev *eth_dev)\n+{\n+\tstruct otx_ep_device *otx_ep =\n+\t\t(struct otx_ep_device *)(eth_dev)->data->dev_private;\n+\tunion otx_ep_mbox_word cmd;\n+\tunion otx_ep_mbox_word rsp;\n+\tint ret;\n+\n+\tcmd.u64 = 0;\n+\tcmd.s_version.opcode = OTX_EP_MBOX_CMD_VERSION;\n+\tcmd.s_version.version = OTX_EP_MBOX_VERSION;\n+\tret = otx_ep_send_mbox_cmd(otx_ep, cmd, &rsp);\n+\tif (!ret)\n+\t\treturn 0;\n+\tif (ret == OTX_EP_MBOX_CMD_STATUS_NACK) {\n+\t\totx_ep_err(\"VF Mbox version:%u is not compatible with PF\\n\",\n+\t\t\t(uint32_t)cmd.s_version.version);\n+\t}\n+\treturn ret;\n+}\n+\n+int otx_ep_mbox_send_dev_exit(struct rte_eth_dev *eth_dev)\n+{\n+\tstruct otx_ep_device *otx_ep =\n+\t\t(struct otx_ep_device *)(eth_dev)->data->dev_private;\n+\tunion otx_ep_mbox_word cmd;\n+\tint ret;\n+\n+\tcmd.u64 = 0;\n+\tcmd.s_version.opcode = OTX_EP_MBOX_CMD_DEV_REMOVE;\n+\tret = otx_ep_send_mbox_cmd(otx_ep, cmd, NULL);\n+\treturn ret;\n+}\ndiff --git a/drivers/net/octeon_ep/otx_ep_mbox.h b/drivers/net/octeon_ep/otx_ep_mbox.h\nnew file mode 100644\nindex 0000000000..9df3c53edd\n--- /dev/null\n+++ b/drivers/net/octeon_ep/otx_ep_mbox.h\n@@ -0,0 +1,163 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2021 Marvell.\n+ */\n+\n+#ifndef _OTX_EP_MBOX_H_\n+#define _OTX_EP_MBOX_H_\n+\n+\n+#define OTX_EP_MBOX_VERSION 1\n+\n+enum otx_ep_mbox_opcode {\n+\tOTX_EP_MBOX_CMD_VERSION,\n+\tOTX_EP_MBOX_CMD_SET_MTU,\n+\tOTX_EP_MBOX_CMD_SET_MAC_ADDR,\n+\tOTX_EP_MBOX_CMD_GET_MAC_ADDR,\n+\tOTX_EP_MBOX_CMD_GET_LINK_INFO,\n+\tOTX_EP_MBOX_CMD_GET_STATS,\n+\tOTX_EP_MBOX_CMD_SET_RX_STATE,\n+\tOTX_EP_MBOX_CMD_SET_LINK_STATUS,\n+\tOTX_EP_MBOX_CMD_GET_LINK_STATUS,\n+\tOTX_EP_MBOX_CMD_GET_MTU,\n+\tOTX_EP_MBOX_CMD_DEV_REMOVE,\n+\tOTX_EP_MBOX_CMD_LAST,\n+};\n+\n+enum otx_ep_mbox_word_type {\n+\tOTX_EP_MBOX_TYPE_CMD,\n+\tOTX_EP_MBOX_TYPE_RSP_ACK,\n+\tOTX_EP_MBOX_TYPE_RSP_NACK,\n+};\n+\n+enum otx_ep_mbox_cmd_status {\n+\tOTX_EP_MBOX_CMD_STATUS_NOT_SETUP = 1,\n+\tOTX_EP_MBOX_CMD_STATUS_TIMEDOUT = 2,\n+\tOTX_EP_MBOX_CMD_STATUS_NACK = 3,\n+\tOTX_EP_MBOX_CMD_STATUS_BUSY = 4\n+};\n+\n+enum otx_ep_mbox_state {\n+\tOTX_EP_MBOX_STATE_IDLE = 0,\n+\tOTX_EP_MBOX_STATE_BUSY = 1,\n+};\n+\n+enum otx_ep_link_status {\n+\tOTX_EP_LINK_STATUS_DOWN,\n+\tOTX_EP_LINK_STATUS_UP,\n+};\n+\n+enum otx_ep_link_duplex {\n+\tOTX_EP_LINK_HALF_DUPLEX,\n+\tOTX_EP_LINK_FULL_DUPLEX,\n+};\n+\n+enum otx_ep_link_autoneg {\n+\tOTX_EP_LINK_FIXED,\n+\tOTX_EP_LINK_AUTONEG,\n+};\n+\n+#define OTX_EP_MBOX_TIMEOUT_MS 1200\n+#define OTX_EP_MBOX_MAX_RETRIES 2\n+#define OTX_EP_MBOX_MAX_DATA_SIZE 6\n+#define OTX_EP_MBOX_MAX_DATA_BUF_SIZE 256\n+#define OTX_EP_MBOX_MORE_FRAG_FLAG 1\n+#define OTX_EP_MBOX_WRITE_WAIT_TIME msecs_to_jiffies(1)\n+\n+union otx_ep_mbox_word {\n+\tuint64_t u64;\n+\tstruct {\n+\t\tuint64_t opcode:8;\n+\t\tuint64_t type:2;\n+\t\tuint64_t rsvd:6;\n+\t\tuint64_t data:48;\n+\t} s;\n+\tstruct {\n+\t\tuint64_t opcode:8;\n+\t\tuint64_t type:2;\n+\t\tuint64_t frag:1;\n+\t\tuint64_t rsvd:5;\n+\t\tuint8_t data[6];\n+\t} s_data;\n+\tstruct {\n+\t\tuint64_t opcode:8;\n+\t\tuint64_t type:2;\n+\t\tuint64_t rsvd:6;\n+\t\tuint64_t version:48;\n+\t} s_version;\n+\tstruct {\n+\t\tuint64_t opcode:8;\n+\t\tuint64_t type:2;\n+\t\tuint64_t rsvd:6;\n+\t\tuint8_t mac_addr[6];\n+\t} s_set_mac;\n+\tstruct {\n+\t\tuint64_t opcode:8;\n+\t\tuint64_t type:2;\n+\t\tuint64_t rsvd:6;\n+\t\tuint64_t mtu:48;\n+\t} s_set_mtu;\n+\tstruct {\n+\t\tuint64_t opcode:8;\n+\t\tuint64_t type:2;\n+\t\tuint64_t rsvd:6;\n+\t\tuint64_t mtu:48;\n+\t} s_get_mtu;\n+\tstruct {\n+\t\tuint64_t opcode:8;\n+\t\tuint64_t type:2;\n+\t\tuint64_t state:1;\n+\t\tuint64_t rsvd:53;\n+\t} s_link_state;\n+\tstruct {\n+\t\tuint64_t opcode:8;\n+\t\tuint64_t type:2;\n+\t\tuint64_t status:1;\n+\t\tuint64_t rsvd:53;\n+\t} s_link_status;\n+} __rte_packed;\n+\n+/* Hardware interface link state information. */\n+struct otx_ep_iface_link_info {\n+\t/* Bitmap of Supported link speeds/modes. */\n+\tuint64_t supported_modes;\n+\n+\t/* Bitmap of Advertised link speeds/modes. */\n+\tuint64_t advertised_modes;\n+\n+\t/* Negotiated link speed in Mbps. */\n+\tuint32_t speed;\n+\n+\t/* MTU */\n+\tuint16_t mtu;\n+\n+\t/* Autonegotiation state. */\n+#define OCTEP_VF_LINK_MODE_AUTONEG_SUPPORTED BIT(0)\n+#define OCTEP_VF_LINK_MODE_AUTONEG_ADVERTISED BIT(1)\n+\tuint8_t autoneg;\n+\n+\t/* Pause frames setting. */\n+#define OCTEP_VF_LINK_MODE_PAUSE_SUPPORTED BIT(0)\n+#define OCTEP_VF_LINK_MODE_PAUSE_ADVERTISED BIT(1)\n+\tuint8_t pause;\n+\n+\t/* Admin state of the link (ifconfig <iface> up/down */\n+\tuint8_t admin_up;\n+\n+\t/* Operational state of the link: physical link is up down */\n+\tuint8_t oper_up;\n+};\n+\n+int otx_ep_mbox_set_mtu(struct rte_eth_dev *eth_dev, uint16_t mtu);\n+int otx_ep_mbox_set_mac_addr(struct rte_eth_dev *eth_dev,\n+\t\t\t struct rte_ether_addr *mac_addr);\n+int otx_ep_mbox_get_mac_addr(struct rte_eth_dev *eth_dev,\n+\t\t\t struct rte_ether_addr *mac_addr);\n+int otx_ep_mbox_get_link_status(struct rte_eth_dev *eth_dev,\n+\t\t\t\tuint8_t *oper_up);\n+int otx_ep_mbox_get_link_info(struct rte_eth_dev *eth_dev, struct rte_eth_link *link);\n+void otx_ep_mbox_enable_interrupt(struct otx_ep_device *otx_ep);\n+void otx_ep_mbox_disable_interrupt(struct otx_ep_device *otx_ep);\n+int otx_ep_mbox_get_max_pkt_len(struct rte_eth_dev *eth_dev);\n+int otx_ep_mbox_version_check(struct rte_eth_dev *eth_dev);\n+int otx_ep_mbox_send_dev_exit(struct rte_eth_dev *eth_dev);\n+#endif\n", "prefixes": [ "v3", "09/11" ] }