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GET /api/patches/126462/?format=api
{ "id": 126462, "url": "http://patches.dpdk.org/api/patches/126462/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20230424122835.39493-7-sedara@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20230424122835.39493-7-sedara@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20230424122835.39493-7-sedara@marvell.com", "date": "2023-04-24T12:28:29", "name": "[v3,06/11] net/octeon_ep: support ISM", "commit_ref": null, "pull_url": null, "state": "not-applicable", "archived": true, "hash": "ae71abda58061a72f5d742c47714eb8780386a3a", "submitter": { "id": 2729, "url": "http://patches.dpdk.org/api/people/2729/?format=api", "name": "Sathesh B Edara", "email": "sedara@marvell.com" }, "delegate": { "id": 310, "url": "http://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20230424122835.39493-7-sedara@marvell.com/mbox/", "series": [ { "id": 27844, "url": "http://patches.dpdk.org/api/series/27844/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=27844", "date": "2023-04-24T12:28:24", "name": "extend octeon ep driver functionality", "version": 3, "mbox": "http://patches.dpdk.org/series/27844/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/126462/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/126462/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 78659429DB;\n\tMon, 24 Apr 2023 14:29:02 +0200 (CEST)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 14A8D42BD9;\n\tMon, 24 Apr 2023 14:28:58 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n [67.231.156.173])\n by mails.dpdk.org (Postfix) with ESMTP id 510D142BC9\n for <dev@dpdk.org>; Mon, 24 Apr 2023 14:28:57 +0200 (CEST)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n by mx0b-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id\n 33OABCbs006481 for <dev@dpdk.org>; Mon, 24 Apr 2023 05:28:56 -0700", "from dc5-exch02.marvell.com ([199.233.59.182])\n by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3q4f3p622b-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Mon, 24 Apr 2023 05:28:56 -0700", "from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.48;\n Mon, 24 Apr 2023 05:28:54 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.48 via Frontend\n Transport; Mon, 24 Apr 2023 05:28:54 -0700", "from localhost.marvell.com (unknown [10.106.27.249])\n by maili.marvell.com (Postfix) with ESMTP id D8EFF3F70A0;\n Mon, 24 Apr 2023 05:28:53 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-transfer-encoding : content-type; s=pfpt0220;\n bh=+64lUjO2g+4U+CNLXORISJNHiSWDx+be/RPDHuC9W2U=;\n b=cqACS+O1Pl6D25XTW6d7JcxFEyAhMQMoYKf9Wwpn8FvWKyC/pUuVbSDFN4XoAvbGMCnC\n 235uHhZJSqjQLGeFMakgZzCc9nY34+fFTYgT6lH7OxaGU+gL0RqIcc7/I+golSAy1Bd0\n 49ouKl/EE14VedLA3DslvkMJ+lJ6ErqoPWM0dezwIFSYH5KStBlID+41y6QMVyya4LYv\n i6mBE9GOm5XEIMfi4TUs40DIt/Vqv2//EWI7AAnSszfG5SLWOSZw84NXhEAYzm1UBD3A\n 9s0I0AhDm6SBv8TXxFwqZo6T8zbMynjk6IltrQgKjLqpkcBpPx1OBnS+sgbYaCmWpbn6 EQ==", "From": "Sathesh Edara <sedara@marvell.com>", "To": "<sburla@marvell.com>, <jerinj@marvell.com>, <sedara@marvell.com>, \"Radha\n Mohan Chintakuntla\" <radhac@marvell.com>, Veerasenareddy Burru\n <vburru@marvell.com>", "CC": "<dev@dpdk.org>", "Subject": "[PATCH v3 06/11] net/octeon_ep: support ISM", "Date": "Mon, 24 Apr 2023 05:28:29 -0700", "Message-ID": "<20230424122835.39493-7-sedara@marvell.com>", "X-Mailer": "git-send-email 2.31.1", "In-Reply-To": "<20230424122835.39493-1-sedara@marvell.com>", "References": "<20230405142537.1899973-2-sedara@marvell.com>\n <20230424122835.39493-1-sedara@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-ORIG-GUID": "T28PW5v3WGoAL_wGAVuPhhyaNEq9Xxfs", "X-Proofpoint-GUID": "T28PW5v3WGoAL_wGAVuPhhyaNEq9Xxfs", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.254,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22\n definitions=2023-04-24_07,2023-04-21_01,2023-02-09_01", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Adds the ISM specific functionality.\n\nSigned-off-by: Sathesh Edara <sedara@marvell.com>\n---\n drivers/net/octeon_ep/cnxk_ep_vf.c | 35 +++++++++++++++--\n drivers/net/octeon_ep/cnxk_ep_vf.h | 12 ++++++\n drivers/net/octeon_ep/otx2_ep_vf.c | 45 ++++++++++++++++++---\n drivers/net/octeon_ep/otx2_ep_vf.h | 14 +++++++\n drivers/net/octeon_ep/otx_ep_common.h | 16 ++++++++\n drivers/net/octeon_ep/otx_ep_ethdev.c | 36 +++++++++++++++++\n drivers/net/octeon_ep/otx_ep_rxtx.c | 56 +++++++++++++++++++++------\n 7 files changed, 194 insertions(+), 20 deletions(-)", "diff": "diff --git a/drivers/net/octeon_ep/cnxk_ep_vf.c b/drivers/net/octeon_ep/cnxk_ep_vf.c\nindex 1a92887109..a437ae68cb 100644\n--- a/drivers/net/octeon_ep/cnxk_ep_vf.c\n+++ b/drivers/net/octeon_ep/cnxk_ep_vf.c\n@@ -2,11 +2,12 @@\n * Copyright(C) 2022 Marvell.\n */\n \n+#include <inttypes.h>\n #include <errno.h>\n \n #include <rte_common.h>\n #include <rte_cycles.h>\n-\n+#include <rte_memzone.h>\n #include \"cnxk_ep_vf.h\"\n \n static void\n@@ -85,6 +86,7 @@ cnxk_ep_vf_setup_iq_regs(struct otx_ep_device *otx_ep, uint32_t iq_no)\n \tstruct otx_ep_instr_queue *iq = otx_ep->instr_queue[iq_no];\n \tint loop = OTX_EP_BUSY_LOOP_COUNT;\n \tvolatile uint64_t reg_val = 0ull;\n+\tuint64_t ism_addr;\n \n \treg_val = oct_ep_read64(otx_ep->hw_addr + CNXK_EP_R_IN_CONTROL(iq_no));\n \n@@ -132,6 +134,19 @@ cnxk_ep_vf_setup_iq_regs(struct otx_ep_device *otx_ep, uint32_t iq_no)\n \t */\n \toct_ep_write64(OTX_EP_CLEAR_SDP_IN_INT_LVLS,\n \t\t otx_ep->hw_addr + CNXK_EP_R_IN_INT_LEVELS(iq_no));\n+\t/* Set up IQ ISM registers and structures */\n+\tism_addr = (otx_ep->ism_buffer_mz->iova | CNXK_EP_ISM_EN\n+\t\t | CNXK_EP_ISM_MSIX_DIS)\n+\t\t + CNXK_EP_IQ_ISM_OFFSET(iq_no);\n+\trte_write64(ism_addr, (uint8_t *)otx_ep->hw_addr +\n+\t\t CNXK_EP_R_IN_CNTS_ISM(iq_no));\n+\tiq->inst_cnt_ism =\n+\t\t(uint32_t *)((uint8_t *)otx_ep->ism_buffer_mz->addr\n+\t\t\t + CNXK_EP_IQ_ISM_OFFSET(iq_no));\n+\totx_ep_err(\"SDP_R[%d] INST Q ISM virt: %p, dma: 0x%\" PRIX64, iq_no,\n+\t\t (void *)iq->inst_cnt_ism, ism_addr);\n+\t*iq->inst_cnt_ism = 0;\n+\tiq->inst_cnt_ism_prev = 0;\n \treturn 0;\n }\n \n@@ -142,6 +157,7 @@ cnxk_ep_vf_setup_oq_regs(struct otx_ep_device *otx_ep, uint32_t oq_no)\n \tuint64_t oq_ctl = 0ull;\n \tint loop = OTX_EP_BUSY_LOOP_COUNT;\n \tstruct otx_ep_droq *droq = otx_ep->droq[oq_no];\n+\tuint64_t ism_addr;\n \n \t/* Wait on IDLE to set to 1, supposed to configure BADDR\n \t * as long as IDLE is 0\n@@ -201,9 +217,22 @@ cnxk_ep_vf_setup_oq_regs(struct otx_ep_device *otx_ep, uint32_t oq_no)\n \trte_write32((uint32_t)reg_val, droq->pkts_sent_reg);\n \n \totx_ep_dbg(\"SDP_R[%d]_sent: %x\", oq_no, rte_read32(droq->pkts_sent_reg));\n-\tloop = OTX_EP_BUSY_LOOP_COUNT;\n+\t/* Set up ISM registers and structures */\n+\tism_addr = (otx_ep->ism_buffer_mz->iova | CNXK_EP_ISM_EN\n+\t\t | CNXK_EP_ISM_MSIX_DIS)\n+\t\t + CNXK_EP_OQ_ISM_OFFSET(oq_no);\n+\trte_write64(ism_addr, (uint8_t *)otx_ep->hw_addr +\n+\t\t CNXK_EP_R_OUT_CNTS_ISM(oq_no));\n+\tdroq->pkts_sent_ism =\n+\t\t(uint32_t *)((uint8_t *)otx_ep->ism_buffer_mz->addr\n+\t\t\t + CNXK_EP_OQ_ISM_OFFSET(oq_no));\n+\totx_ep_err(\"SDP_R[%d] OQ ISM virt: %p dma: 0x%\" PRIX64,\n+\t\t oq_no, (void *)droq->pkts_sent_ism, ism_addr);\n+\t*droq->pkts_sent_ism = 0;\n+\tdroq->pkts_sent_ism_prev = 0;\n \n-\twhile (((rte_read32(droq->pkts_sent_reg)) != 0ull)) {\n+\tloop = OTX_EP_BUSY_LOOP_COUNT;\n+\twhile (((rte_read32(droq->pkts_sent_reg)) != 0ull) && loop--) {\n \t\treg_val = rte_read32(droq->pkts_sent_reg);\n \t\trte_write32((uint32_t)reg_val, droq->pkts_sent_reg);\n \t\trte_delay_ms(1);\ndiff --git a/drivers/net/octeon_ep/cnxk_ep_vf.h b/drivers/net/octeon_ep/cnxk_ep_vf.h\nindex aaa5774552..072b38ea15 100644\n--- a/drivers/net/octeon_ep/cnxk_ep_vf.h\n+++ b/drivers/net/octeon_ep/cnxk_ep_vf.h\n@@ -27,6 +27,7 @@\n #define CNXK_EP_R_IN_INT_LEVELS_START 0x10060\n #define CNXK_EP_R_IN_PKT_CNT_START 0x10080\n #define CNXK_EP_R_IN_BYTE_CNT_START 0x10090\n+#define CNXK_EP_R_IN_CNTS_ISM_START 0x10520\n \n #define CNXK_EP_R_IN_CONTROL(ring) \\\n \t(CNXK_EP_R_IN_CONTROL_START + ((ring) * CNXK_EP_RING_OFFSET))\n@@ -55,6 +56,8 @@\n #define CNXK_EP_R_IN_BYTE_CNT(ring) \\\n \t(CNXK_EP_R_IN_BYTE_CNT_START + ((ring) * CNXK_EP_RING_OFFSET))\n \n+#define CNXK_EP_R_IN_CNTS_ISM(ring) \\\n+\t(CNXK_EP_R_IN_CNTS_ISM_START + ((ring) * CNXK_EP_RING_OFFSET))\n \n /** Rings per Virtual Function **/\n #define CNXK_EP_R_IN_CTL_RPVF_MASK\t(0xF)\n@@ -87,6 +90,7 @@\n #define CNXK_EP_R_OUT_ENABLE_START 0x10170\n #define CNXK_EP_R_OUT_PKT_CNT_START 0x10180\n #define CNXK_EP_R_OUT_BYTE_CNT_START 0x10190\n+#define CNXK_EP_R_OUT_CNTS_ISM_START 0x10510\n \n #define CNXK_EP_R_OUT_CNTS(ring) \\\n \t(CNXK_EP_R_OUT_CNTS_START + ((ring) * CNXK_EP_RING_OFFSET))\n@@ -118,6 +122,9 @@\n #define CNXK_EP_R_OUT_BYTE_CNT(ring) \\\n \t(CNXK_EP_R_OUT_BYTE_CNT_START + ((ring) * CNXK_EP_RING_OFFSET))\n \n+#define CNXK_EP_R_OUT_CNTS_ISM(ring) \\\n+\t(CNXK_EP_R_OUT_CNTS_ISM_START + ((ring) * CNXK_EP_RING_OFFSET))\n+\n /*------------------ R_OUT Masks ----------------*/\n #define CNXK_EP_R_OUT_INT_LEVELS_BMODE (1ULL << 63)\n #define CNXK_EP_R_OUT_INT_LEVELS_TIMET (32)\n@@ -161,4 +168,9 @@ struct cnxk_ep_instr_64B {\n \tuint64_t exhdr[4];\n };\n \n+#define CNXK_EP_IQ_ISM_OFFSET(queue) (RTE_CACHE_LINE_SIZE * (queue) + 4)\n+#define CNXK_EP_OQ_ISM_OFFSET(queue) (RTE_CACHE_LINE_SIZE * (queue))\n+#define CNXK_EP_ISM_EN (0x1)\n+#define CNXK_EP_ISM_MSIX_DIS (0x2)\n+\n #endif /*_CNXK_EP_VF_H_ */\ndiff --git a/drivers/net/octeon_ep/otx2_ep_vf.c b/drivers/net/octeon_ep/otx2_ep_vf.c\nindex 3e4895862b..ced3a415a5 100644\n--- a/drivers/net/octeon_ep/otx2_ep_vf.c\n+++ b/drivers/net/octeon_ep/otx2_ep_vf.c\n@@ -6,6 +6,7 @@\n \n #include <rte_common.h>\n #include <rte_cycles.h>\n+#include <rte_memzone.h>\n #include \"otx_ep_common.h\"\n #include \"otx2_ep_vf.h\"\n \n@@ -236,6 +237,7 @@ otx2_vf_setup_iq_regs(struct otx_ep_device *otx_ep, uint32_t iq_no)\n {\n \tstruct otx_ep_instr_queue *iq = otx_ep->instr_queue[iq_no];\n \tvolatile uint64_t reg_val = 0ull;\n+\tuint64_t ism_addr;\n \tint loop = SDP_VF_BUSY_LOOP_COUNT;\n \n \treg_val = oct_ep_read64(otx_ep->hw_addr + SDP_VF_R_IN_CONTROL(iq_no));\n@@ -282,6 +284,22 @@ otx2_vf_setup_iq_regs(struct otx_ep_device *otx_ep, uint32_t iq_no)\n \t */\n \toct_ep_write64(OTX_EP_CLEAR_SDP_IN_INT_LVLS,\n \t\t otx_ep->hw_addr + SDP_VF_R_IN_INT_LEVELS(iq_no));\n+\n+\t/* Set up IQ ISM registers and structures */\n+\tism_addr = (otx_ep->ism_buffer_mz->iova | OTX2_EP_ISM_EN\n+\t\t | OTX2_EP_ISM_MSIX_DIS)\n+\t\t + OTX2_EP_IQ_ISM_OFFSET(iq_no);\n+\toct_ep_write64(ism_addr, (uint8_t *)otx_ep->hw_addr +\n+\t\t SDP_VF_R_IN_CNTS_ISM(iq_no));\n+\tiq->inst_cnt_ism =\n+\t\t(uint32_t *)((uint8_t *)otx_ep->ism_buffer_mz->addr\n+\t\t\t + OTX2_EP_IQ_ISM_OFFSET(iq_no));\n+\totx_ep_err(\"SDP_R[%d] INST Q ISM virt: %p, dma: 0x%x\", iq_no,\n+\t\t (void *)iq->inst_cnt_ism,\n+\t\t (unsigned int)ism_addr);\n+\t*iq->inst_cnt_ism = 0;\n+\tiq->inst_cnt_ism_prev = 0;\n+\n \treturn 0;\n }\n \n@@ -290,6 +308,7 @@ otx2_vf_setup_oq_regs(struct otx_ep_device *otx_ep, uint32_t oq_no)\n {\n \tvolatile uint64_t reg_val = 0ull;\n \tuint64_t oq_ctl = 0ull;\n+\tuint64_t ism_addr;\n \tint loop = OTX_EP_BUSY_LOOP_COUNT;\n \tstruct otx_ep_droq *droq = otx_ep->droq[oq_no];\n \n@@ -351,18 +370,32 @@ otx2_vf_setup_oq_regs(struct otx_ep_device *otx_ep, uint32_t oq_no)\n \n \totx_ep_dbg(\"SDP_R[%d]_sent: %x\", oq_no, rte_read32(droq->pkts_sent_reg));\n \n-\tloop = OTX_EP_BUSY_LOOP_COUNT;\n+\t/* Set up ISM registers and structures */\n+\tism_addr = (otx_ep->ism_buffer_mz->iova | OTX2_EP_ISM_EN\n+\t\t | OTX2_EP_ISM_MSIX_DIS)\n+\t\t + OTX2_EP_OQ_ISM_OFFSET(oq_no);\n+\toct_ep_write64(ism_addr, (uint8_t *)otx_ep->hw_addr +\n+\t\t SDP_VF_R_OUT_CNTS_ISM(oq_no));\n+\tdroq->pkts_sent_ism =\n+\t\t(uint32_t *)((uint8_t *)otx_ep->ism_buffer_mz->addr\n+\t\t\t + OTX2_EP_OQ_ISM_OFFSET(oq_no));\n+\totx_ep_err(\"SDP_R[%d] OQ ISM virt: %p, dma: 0x%x\", oq_no,\n+\t\t (void *)droq->pkts_sent_ism,\n+\t\t (unsigned int)ism_addr);\n+\t*droq->pkts_sent_ism = 0;\n+\tdroq->pkts_sent_ism_prev = 0;\n+\n+\tloop = SDP_VF_BUSY_LOOP_COUNT;\n \twhile (((rte_read32(droq->pkts_sent_reg)) != 0ull) && loop--) {\n \t\treg_val = rte_read32(droq->pkts_sent_reg);\n \t\trte_write32((uint32_t)reg_val, droq->pkts_sent_reg);\n \t\trte_delay_ms(1);\n \t}\n-\n-\tif (loop < 0) {\n-\t\totx_ep_err(\"Packets sent register value is not cleared\\n\");\n+\tif (loop < 0)\n \t\treturn -EIO;\n-\t}\n-\totx_ep_dbg(\"SDP_R[%d]_sent: %x\", oq_no, rte_read32(droq->pkts_sent_reg));\n+\totx_ep_dbg(\"SDP_R[%d]_sent: %x\", oq_no,\n+\t\t rte_read32(droq->pkts_sent_reg));\n+\n \treturn 0;\n }\n \ndiff --git a/drivers/net/octeon_ep/otx2_ep_vf.h b/drivers/net/octeon_ep/otx2_ep_vf.h\nindex 36c0b25dea..7c799475ab 100644\n--- a/drivers/net/octeon_ep/otx2_ep_vf.h\n+++ b/drivers/net/octeon_ep/otx2_ep_vf.h\n@@ -42,6 +42,7 @@\n #define SDP_VF_R_IN_INT_LEVELS_START (0x10060)\n #define SDP_VF_R_IN_PKT_CNT_START (0x10080)\n #define SDP_VF_R_IN_BYTE_CNT_START (0x10090)\n+#define SDP_VF_R_IN_CNTS_ISM_START (0x10520)\n \n #define SDP_VF_R_IN_CONTROL(ring) \\\n \t(SDP_VF_R_IN_CONTROL_START + ((ring) * SDP_VF_RING_OFFSET))\n@@ -70,6 +71,9 @@\n #define SDP_VF_R_IN_BYTE_CNT(ring) \\\n \t(SDP_VF_R_IN_BYTE_CNT_START + ((ring) * SDP_VF_RING_OFFSET))\n \n+#define SDP_VF_R_IN_CNTS_ISM(ring) \\\n+\t(SDP_VF_R_IN_CNTS_ISM_START + (SDP_VF_RING_OFFSET * (ring)))\n+\n /* SDP VF OQ Registers */\n #define SDP_VF_R_OUT_CNTS_START (0x10100)\n #define SDP_VF_R_OUT_INT_LEVELS_START (0x10110)\n@@ -80,6 +84,7 @@\n #define SDP_VF_R_OUT_ENABLE_START (0x10160)\n #define SDP_VF_R_OUT_PKT_CNT_START (0x10180)\n #define SDP_VF_R_OUT_BYTE_CNT_START (0x10190)\n+#define SDP_VF_R_OUT_CNTS_ISM_START (0x10510)\n \n #define SDP_VF_R_OUT_CONTROL(ring) \\\n \t(SDP_VF_R_OUT_CONTROL_START + ((ring) * SDP_VF_RING_OFFSET))\n@@ -108,6 +113,9 @@\n #define SDP_VF_R_OUT_BYTE_CNT(ring) \\\n \t(SDP_VF_R_OUT_BYTE_CNT_START + ((ring) * SDP_VF_RING_OFFSET))\n \n+#define SDP_VF_R_OUT_CNTS_ISM(ring) \\\n+\t(SDP_VF_R_OUT_CNTS_ISM_START + (SDP_VF_RING_OFFSET * (ring)))\n+\n /* SDP VF IQ Masks */\n #define SDP_VF_R_IN_CTL_RPVF_MASK (0xF)\n #define\tSDP_VF_R_IN_CTL_RPVF_POS (48)\n@@ -143,6 +151,12 @@ struct otx2_ep_instr_64B {\n \tuint64_t exhdr[4];\n };\n \n+#define OTX2_EP_IQ_ISM_OFFSET(queue) (RTE_CACHE_LINE_SIZE * (queue) + 4)\n+#define OTX2_EP_OQ_ISM_OFFSET(queue) (RTE_CACHE_LINE_SIZE * (queue))\n+#define OTX2_EP_ISM_EN (0x1)\n+#define OTX2_EP_ISM_MSIX_DIS (0x2)\n+#define OTX2_EP_MAX_RX_PKT_LEN (16384)\n+\n union out_int_lvl_t {\n \tuint64_t d64;\n \tstruct {\ndiff --git a/drivers/net/octeon_ep/otx_ep_common.h b/drivers/net/octeon_ep/otx_ep_common.h\nindex a3260d5243..76528ed49d 100644\n--- a/drivers/net/octeon_ep/otx_ep_common.h\n+++ b/drivers/net/octeon_ep/otx_ep_common.h\n@@ -185,6 +185,9 @@ struct otx_ep_instr_queue {\n \t */\n \tuint32_t flush_index;\n \n+\t/* Free-running/wrapping instruction counter for IQ. */\n+\tuint32_t inst_cnt;\n+\n \t/* This keeps track of the instructions pending in this queue. */\n \tuint64_t instr_pending;\n \n@@ -211,6 +214,12 @@ struct otx_ep_instr_queue {\n \n \t/* Memory zone */\n \tconst struct rte_memzone *iq_mz;\n+\n+\t/* Location in memory updated by SDP ISM */\n+\tuint32_t *inst_cnt_ism;\n+\n+\t/* track inst count locally to consolidate HW counter updates */\n+\tuint32_t inst_cnt_ism_prev;\n };\n \n /** Descriptor format.\n@@ -355,6 +364,10 @@ struct otx_ep_droq {\n \tconst struct rte_memzone *desc_ring_mz;\n \n \tconst struct rte_memzone *info_mz;\n+\n+\t/* Pointer to host memory copy of output packet count, set by ISM */\n+\tuint32_t *pkts_sent_ism;\n+\tuint32_t pkts_sent_ism_prev;\n };\n #define OTX_EP_DROQ_SIZE\t\t(sizeof(struct otx_ep_droq))\n \n@@ -459,6 +472,9 @@ struct otx_ep_device {\n \tuint64_t rx_offloads;\n \n \tuint64_t tx_offloads;\n+\n+\t/* DMA buffer for SDP ISM messages */\n+\tconst struct rte_memzone *ism_buffer_mz;\n };\n \n int otx_ep_setup_iqs(struct otx_ep_device *otx_ep, uint32_t iq_no,\ndiff --git a/drivers/net/octeon_ep/otx_ep_ethdev.c b/drivers/net/octeon_ep/otx_ep_ethdev.c\nindex 5677a2d6a6..30a7a450fb 100644\n--- a/drivers/net/octeon_ep/otx_ep_ethdev.c\n+++ b/drivers/net/octeon_ep/otx_ep_ethdev.c\n@@ -2,6 +2,7 @@\n * Copyright(C) 2021 Marvell.\n */\n \n+#include <inttypes.h>\n #include <ethdev_pci.h>\n \n #include \"otx_ep_common.h\"\n@@ -90,6 +91,32 @@ otx_ep_dev_stop(struct rte_eth_dev *eth_dev)\n \treturn 0;\n }\n \n+/*\n+ * We only need 2 uint32_t locations per IOQ, but separate these so\n+ * each IOQ has the variables on its own cache line.\n+ */\n+#define OTX_EP_ISM_BUFFER_SIZE (OTX_EP_MAX_IOQS_PER_VF * RTE_CACHE_LINE_SIZE)\n+static int\n+otx_ep_ism_setup(struct otx_ep_device *otx_epvf)\n+{\n+\totx_epvf->ism_buffer_mz =\n+\t\trte_eth_dma_zone_reserve(otx_epvf->eth_dev, \"ism\",\n+\t\t\t\t\t 0, OTX_EP_ISM_BUFFER_SIZE,\n+\t\t\t\t\t OTX_EP_PCI_RING_ALIGN, 0);\n+\n+\t/* Same DMA buffer is shared by OQ and IQ, clear it at start */\n+\tmemset(otx_epvf->ism_buffer_mz->addr, 0, OTX_EP_ISM_BUFFER_SIZE);\n+\tif (otx_epvf->ism_buffer_mz == NULL) {\n+\t\totx_ep_err(\"Failed to allocate ISM buffer\\n\");\n+\t\treturn(-1);\n+\t}\n+\totx_ep_dbg(\"ISM: virt: 0x%p, dma: 0x%\" PRIX64,\n+\t\t (void *)otx_epvf->ism_buffer_mz->addr,\n+\t\t otx_epvf->ism_buffer_mz->iova);\n+\n+\treturn 0;\n+}\n+\n static int\n otx_ep_chip_specific_setup(struct otx_ep_device *otx_epvf)\n {\n@@ -110,6 +137,8 @@ otx_ep_chip_specific_setup(struct otx_ep_device *otx_epvf)\n \t\totx_epvf->chip_id = dev_id;\n \t\tret = otx2_ep_vf_setup_device(otx_epvf);\n \t\totx_epvf->fn_list.disable_io_queues(otx_epvf);\n+\t\tif (otx_ep_ism_setup(otx_epvf))\n+\t\t\tret = -EINVAL;\n \t\tbreak;\n \tcase PCI_DEVID_CN10KA_EP_NET_VF:\n \tcase PCI_DEVID_CN10KB_EP_NET_VF:\n@@ -118,6 +147,8 @@ otx_ep_chip_specific_setup(struct otx_ep_device *otx_epvf)\n \t\totx_epvf->chip_id = dev_id;\n \t\tret = cnxk_ep_vf_setup_device(otx_epvf);\n \t\totx_epvf->fn_list.disable_io_queues(otx_epvf);\n+\t\tif (otx_ep_ism_setup(otx_epvf))\n+\t\t\tret = -EINVAL;\n \t\tbreak;\n \tdefault:\n \t\totx_ep_err(\"Unsupported device\\n\");\n@@ -434,6 +465,11 @@ otx_ep_dev_close(struct rte_eth_dev *eth_dev)\n \t}\n \totx_ep_dbg(\"Num IQs:%d freed\\n\", otx_epvf->nb_tx_queues);\n \n+\tif (rte_eth_dma_zone_free(eth_dev, \"ism\", 0)) {\n+\t\totx_ep_err(\"Failed to delete ISM buffer\\n\");\n+\t\treturn -EINVAL;\n+\t}\n+\n \treturn 0;\n }\n \ndiff --git a/drivers/net/octeon_ep/otx_ep_rxtx.c b/drivers/net/octeon_ep/otx_ep_rxtx.c\nindex 9712e6cce6..c4153bd583 100644\n--- a/drivers/net/octeon_ep/otx_ep_rxtx.c\n+++ b/drivers/net/octeon_ep/otx_ep_rxtx.c\n@@ -20,6 +20,7 @@\n #define OTX_EP_INFO_SIZE 8\n #define OTX_EP_FSZ_FS0 0\n #define DROQ_REFILL_THRESHOLD 16\n+#define OTX2_SDP_REQUEST_ISM (0x1ULL << 63)\n \n static void\n otx_ep_dmazone_free(const struct rte_memzone *mz)\n@@ -412,15 +413,32 @@ otx_ep_iqreq_add(struct otx_ep_instr_queue *iq, void *buf,\n static uint32_t\n otx_vf_update_read_index(struct otx_ep_instr_queue *iq)\n {\n-\tuint32_t new_idx = rte_read32(iq->inst_cnt_reg);\n-\tif (unlikely(new_idx == 0xFFFFFFFFU))\n-\t\trte_write32(new_idx, iq->inst_cnt_reg);\n+\tuint32_t val;\n+\n+\t/*\n+\t * Batch subtractions from the HW counter to reduce PCIe traffic\n+\t * This adds an extra local variable, but almost halves the\n+\t * number of PCIe writes.\n+\t */\n+\tval = *iq->inst_cnt_ism;\n+\tiq->inst_cnt += val - iq->inst_cnt_ism_prev;\n+\tiq->inst_cnt_ism_prev = val;\n+\n+\tif (val > (uint32_t)(1 << 31)) {\n+\t\t/*\n+\t\t * Only subtract the packet count in the HW counter\n+\t\t * when count above halfway to saturation.\n+\t\t */\n+\t\trte_write32(val, iq->inst_cnt_reg);\n+\t\t*iq->inst_cnt_ism = 0;\n+\t\tiq->inst_cnt_ism_prev = 0;\n+\t}\n+\trte_write64(OTX2_SDP_REQUEST_ISM, iq->inst_cnt_reg);\n+\n \t/* Modulo of the new index with the IQ size will give us\n \t * the new index.\n \t */\n-\tnew_idx &= (iq->nb_desc - 1);\n-\n-\treturn new_idx;\n+\treturn iq->inst_cnt & (iq->nb_desc - 1);\n }\n \n static void\n@@ -962,14 +980,30 @@ otx_ep_droq_read_packet(struct otx_ep_device *otx_ep,\n static inline uint32_t\n otx_ep_check_droq_pkts(struct otx_ep_droq *droq)\n {\n-\tvolatile uint64_t pkt_count;\n \tuint32_t new_pkts;\n+\tuint32_t val;\n+\n+\t/*\n+\t * Batch subtractions from the HW counter to reduce PCIe traffic\n+\t * This adds an extra local variable, but almost halves the\n+\t * number of PCIe writes.\n+\t */\n+\tval = *droq->pkts_sent_ism;\n+\tnew_pkts = val - droq->pkts_sent_ism_prev;\n+\tdroq->pkts_sent_ism_prev = val;\n \n-\t/* Latest available OQ packets */\n-\tpkt_count = rte_read32(droq->pkts_sent_reg);\n-\trte_write32(pkt_count, droq->pkts_sent_reg);\n-\tnew_pkts = pkt_count;\n+\tif (val > (uint32_t)(1 << 31)) {\n+\t\t/*\n+\t\t * Only subtract the packet count in the HW counter\n+\t\t * when count above halfway to saturation.\n+\t\t */\n+\t\trte_write32(val, droq->pkts_sent_reg);\n+\t\t*droq->pkts_sent_ism = 0;\n+\t\tdroq->pkts_sent_ism_prev = 0;\n+\t}\n+\trte_write64(OTX2_SDP_REQUEST_ISM, droq->pkts_sent_reg);\n \tdroq->pkts_pending += new_pkts;\n+\n \treturn new_pkts;\n }\n \n", "prefixes": [ "v3", "06/11" ] }