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GET /api/patches/126425/?format=api
{ "id": 126425, "url": "http://patches.dpdk.org/api/patches/126425/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20230423050814.825-2-syalavarthi@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20230423050814.825-2-syalavarthi@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20230423050814.825-2-syalavarthi@marvell.com", "date": "2023-04-23T05:08:12", "name": "[v1,1/3] ml/cnxk: split metadata fields into sections", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "c5c7445d0945743280b8a8d6a22efab6fea8a987", "submitter": { "id": 2480, "url": "http://patches.dpdk.org/api/people/2480/?format=api", "name": "Srikanth Yalavarthi", "email": "syalavarthi@marvell.com" }, "delegate": { "id": 1, "url": "http://patches.dpdk.org/api/users/1/?format=api", "username": "tmonjalo", "first_name": "Thomas", "last_name": "Monjalon", "email": "thomas@monjalon.net" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20230423050814.825-2-syalavarthi@marvell.com/mbox/", "series": [ { "id": 27829, "url": "http://patches.dpdk.org/api/series/27829/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=27829", "date": "2023-04-23T05:08:11", "name": "Add support for 32 I/O per model", "version": 1, "mbox": "http://patches.dpdk.org/series/27829/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/126425/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/126425/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id B5128429BA;\n\tSun, 23 Apr 2023 07:08:26 +0200 (CEST)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id D932242BD9;\n\tSun, 23 Apr 2023 07:08:22 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n [67.231.156.173])\n by mails.dpdk.org (Postfix) with ESMTP id 105EC40A80\n for <dev@dpdk.org>; Sun, 23 Apr 2023 07:08:21 +0200 (CEST)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n by mx0b-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id\n 33N4iPB5009043 for <dev@dpdk.org>; Sat, 22 Apr 2023 22:08:21 -0700", "from dc5-exch01.marvell.com ([199.233.59.181])\n by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3q4f3p225y-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Sat, 22 Apr 2023 22:08:21 -0700", "from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.48;\n Sat, 22 Apr 2023 22:08:19 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.48 via Frontend\n Transport; Sat, 22 Apr 2023 22:08:19 -0700", "from ml-host-33.caveonetworks.com (unknown [10.110.143.233])\n by maili.marvell.com (Postfix) with ESMTP id 96F9F3F704C;\n Sat, 22 Apr 2023 22:08:18 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-type; s=pfpt0220; bh=4lpqvncZNW/IYRnZDkegETqCGFDrReJ5ft7zaFd5eJo=;\n b=YHJ/OpE9q+FVqDwmJLNHtgCxa8ddBQsmh9/1hgvnsKQmtGpiIgbvqv+BBtEdoQqbrCj9\n IMRSCTzT8zICcXuYwyAt4eDTli+VS74IIyQ6+O0pfLsts4XdoLKqSzuy4o3VmEQfZMTx\n nwZgGiLofutFdPx25zvd/x5yrGTIksi6cDLBjRUf6BYiKIRTnzMATFYWutgQVGFp1jHh\n h5VGcUpGLzl8zOCsiGnwy0GmJcCMF3chzWYDbMSak4O6cXdS9ccwJuz8buRRBPkxJJ7w\n 2NpE9oyrCfz8PGfbKAuF5NOoUxgASg8Kp38NZbJrQMQNWhOnGlK3LY4uRMOsdc2JOsiX pQ==", "From": "Srikanth Yalavarthi <syalavarthi@marvell.com>", "To": "Srikanth Yalavarthi <syalavarthi@marvell.com>", "CC": "<dev@dpdk.org>, <sshankarnara@marvell.com>, <aprabhu@marvell.com>,\n <ptakkar@marvell.com>", "Subject": "[PATCH v1 1/3] ml/cnxk: split metadata fields into sections", "Date": "Sat, 22 Apr 2023 22:08:12 -0700", "Message-ID": "<20230423050814.825-2-syalavarthi@marvell.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": "<20230423050814.825-1-syalavarthi@marvell.com>", "References": "<20230423050814.825-1-syalavarthi@marvell.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Proofpoint-ORIG-GUID": "5suXOda_no1MdEr59k8t5BKXrmeGElBw", "X-Proofpoint-GUID": "5suXOda_no1MdEr59k8t5BKXrmeGElBw", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.254,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22\n definitions=2023-04-23_02,2023-04-21_01,2023-02-09_01", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Split metadata into header, model sections, weights & bias,\ninput / output and data sections. This is a preparatory step\nto introduce v2301 of model metadata.\n\nSigned-off-by: Srikanth Yalavarthi <syalavarthi@marvell.com>\n---\n drivers/ml/cnxk/cn10k_ml_model.c | 26 +-\n drivers/ml/cnxk/cn10k_ml_model.h | 487 ++++++++++++++++---------------\n 2 files changed, 270 insertions(+), 243 deletions(-)", "diff": "diff --git a/drivers/ml/cnxk/cn10k_ml_model.c b/drivers/ml/cnxk/cn10k_ml_model.c\nindex 2ded05c5dc..c0b7b061f5 100644\n--- a/drivers/ml/cnxk/cn10k_ml_model.c\n+++ b/drivers/ml/cnxk/cn10k_ml_model.c\n@@ -47,42 +47,42 @@ cn10k_ml_model_metadata_check(uint8_t *buffer, uint64_t size)\n \tmetadata = (struct cn10k_ml_model_metadata *)buffer;\n \n \t/* Header CRC check */\n-\tif (metadata->metadata_header.header_crc32c != 0) {\n-\t\theader_crc32c = rte_hash_crc(\n-\t\t\tbuffer, sizeof(metadata->metadata_header) - sizeof(uint32_t), 0);\n+\tif (metadata->header.header_crc32c != 0) {\n+\t\theader_crc32c =\n+\t\t\trte_hash_crc(buffer, sizeof(metadata->header) - sizeof(uint32_t), 0);\n \n-\t\tif (header_crc32c != metadata->metadata_header.header_crc32c) {\n+\t\tif (header_crc32c != metadata->header.header_crc32c) {\n \t\t\tplt_err(\"Invalid model, Header CRC mismatch\");\n \t\t\treturn -EINVAL;\n \t\t}\n \t}\n \n \t/* Payload CRC check */\n-\tif (metadata->metadata_header.payload_crc32c != 0) {\n-\t\tpayload_crc32c = rte_hash_crc(buffer + sizeof(metadata->metadata_header),\n-\t\t\t\t\t size - sizeof(metadata->metadata_header), 0);\n+\tif (metadata->header.payload_crc32c != 0) {\n+\t\tpayload_crc32c = rte_hash_crc(buffer + sizeof(metadata->header),\n+\t\t\t\t\t size - sizeof(metadata->header), 0);\n \n-\t\tif (payload_crc32c != metadata->metadata_header.payload_crc32c) {\n+\t\tif (payload_crc32c != metadata->header.payload_crc32c) {\n \t\t\tplt_err(\"Invalid model, Payload CRC mismatch\");\n \t\t\treturn -EINVAL;\n \t\t}\n \t}\n \n \t/* Model magic string */\n-\tif (strncmp((char *)metadata->metadata_header.magic, MRVL_ML_MODEL_MAGIC_STRING, 4) != 0) {\n-\t\tplt_err(\"Invalid model, magic = %s\", metadata->metadata_header.magic);\n+\tif (strncmp((char *)metadata->header.magic, MRVL_ML_MODEL_MAGIC_STRING, 4) != 0) {\n+\t\tplt_err(\"Invalid model, magic = %s\", metadata->header.magic);\n \t\treturn -EINVAL;\n \t}\n \n \t/* Target architecture */\n-\tif (metadata->metadata_header.target_architecture != MRVL_ML_MODEL_TARGET_ARCH) {\n+\tif (metadata->header.target_architecture != MRVL_ML_MODEL_TARGET_ARCH) {\n \t\tplt_err(\"Model target architecture (%u) not supported\",\n-\t\t\tmetadata->metadata_header.target_architecture);\n+\t\t\tmetadata->header.target_architecture);\n \t\treturn -ENOTSUP;\n \t}\n \n \t/* Header version */\n-\trte_memcpy(version, metadata->metadata_header.version, 4 * sizeof(uint8_t));\n+\trte_memcpy(version, metadata->header.version, 4 * sizeof(uint8_t));\n \tif (version[0] * 1000 + version[1] * 100 < MRVL_ML_MODEL_VERSION) {\n \t\tplt_err(\"Metadata version = %u.%u.%u.%u (< %u.%u.%u.%u) not supported\", version[0],\n \t\t\tversion[1], version[2], version[3], (MRVL_ML_MODEL_VERSION / 1000) % 10,\ndiff --git a/drivers/ml/cnxk/cn10k_ml_model.h b/drivers/ml/cnxk/cn10k_ml_model.h\nindex 1bc748265d..b30ad5a981 100644\n--- a/drivers/ml/cnxk/cn10k_ml_model.h\n+++ b/drivers/ml/cnxk/cn10k_ml_model.h\n@@ -30,298 +30,325 @@ enum cn10k_ml_model_state {\n #define MRVL_ML_OUTPUT_NAME_LEN\t 16\n #define MRVL_ML_INPUT_OUTPUT_SIZE 8\n \n-/* Model file metadata structure */\n-struct cn10k_ml_model_metadata {\n-\t/* Header (256-byte) */\n-\tstruct {\n-\t\t/* Magic string ('M', 'R', 'V', 'L') */\n-\t\tuint8_t magic[4];\n+/* Header (256-byte) */\n+struct cn10k_ml_model_metadata_header {\n+\t/* Magic string ('M', 'R', 'V', 'L') */\n+\tuint8_t magic[4];\n \n-\t\t/* Metadata version */\n-\t\tuint8_t version[4];\n+\t/* Metadata version */\n+\tuint8_t version[4];\n \n-\t\t/* Metadata size */\n-\t\tuint32_t metadata_size;\n+\t/* Metadata size */\n+\tuint32_t metadata_size;\n \n-\t\t/* Unique ID */\n-\t\tuint8_t uuid[128];\n+\t/* Unique ID */\n+\tuint8_t uuid[128];\n \n-\t\t/* Model target architecture\n-\t\t * 0 = Undefined\n-\t\t * 1 = M1K\n-\t\t * 128 = MLIP\n-\t\t * 256 = Experimental\n-\t\t */\n-\t\tuint32_t target_architecture;\n-\t\tuint8_t reserved[104];\n+\t/* Model target architecture\n+\t * 0 = Undefined\n+\t * 1 = M1K\n+\t * 128 = MLIP\n+\t * 256 = Experimental\n+\t */\n+\tuint32_t target_architecture;\n+\tuint8_t reserved[104];\n \n-\t\t/* CRC of data after metadata_header (i.e. after first 256 bytes) */\n-\t\tuint32_t payload_crc32c;\n+\t/* CRC of data after header (i.e. after first 256 bytes) */\n+\tuint32_t payload_crc32c;\n \n-\t\t/* CRC of first 252 bytes of metadata_header, after payload_crc calculation */\n-\t\tuint32_t header_crc32c;\n-\t} metadata_header;\n+\t/* CRC of first 252 bytes of header, after payload_crc calculation */\n+\tuint32_t header_crc32c;\n+};\n \n-\t/* Model information (256-byte) */\n-\tstruct {\n-\t\t/* Model name string */\n-\t\tuint8_t name[MRVL_ML_MODEL_NAME_LEN];\n+/* Model information (256-byte) */\n+struct cn10k_ml_model_metadata_model {\n+\t/* Model name string */\n+\tuint8_t name[MRVL_ML_MODEL_NAME_LEN];\n \n-\t\t/* Model version info (xx.xx.xx.xx) */\n-\t\tuint8_t version[4];\n+\t/* Model version info (xx.xx.xx.xx) */\n+\tuint8_t version[4];\n \n-\t\t/* Model code size (Init + Main + Finish) */\n-\t\tuint32_t code_size;\n+\t/* Model code size (Init + Main + Finish) */\n+\tuint32_t code_size;\n \n-\t\t/* Model data size (Weights and Bias) */\n-\t\tuint32_t data_size;\n+\t/* Model data size (Weights and Bias) */\n+\tuint32_t data_size;\n \n-\t\t/* OCM start offset, set to ocm_wb_range_start */\n-\t\tuint32_t ocm_start;\n+\t/* OCM start offset, set to ocm_wb_range_start */\n+\tuint32_t ocm_start;\n \n-\t\t/* OCM start offset, set to max OCM size */\n-\t\tuint32_t ocm_end;\n+\t/* OCM start offset, set to max OCM size */\n+\tuint32_t ocm_end;\n \n-\t\t/* Relocatable flag (always yes)\n-\t\t * 0 = Not relocatable\n-\t\t * 1 = Relocatable\n-\t\t */\n-\t\tuint8_t ocm_relocatable;\n+\t/* Relocatable flag (always yes)\n+\t * 0 = Not relocatable\n+\t * 1 = Relocatable\n+\t */\n+\tuint8_t ocm_relocatable;\n \n-\t\t/* Tile relocatable flag (always yes)\n-\t\t * 0 = Not relocatable\n-\t\t * 1 = Relocatable\n-\t\t */\n-\t\tuint8_t tile_relocatable;\n+\t/* Tile relocatable flag (always yes)\n+\t * 0 = Not relocatable\n+\t * 1 = Relocatable\n+\t */\n+\tuint8_t tile_relocatable;\n \n-\t\t/* Start tile (Always 0) */\n-\t\tuint8_t tile_start;\n+\t/* Start tile (Always 0) */\n+\tuint8_t tile_start;\n \n-\t\t/* End tile (num_tiles - 1) */\n-\t\tuint8_t tile_end;\n+\t/* End tile (num_tiles - 1) */\n+\tuint8_t tile_end;\n \n-\t\t/* Inference batch size */\n-\t\tuint8_t batch_size;\n+\t/* Inference batch size */\n+\tuint8_t batch_size;\n \n-\t\t/* Number of input tensors (Max 8) */\n-\t\tuint8_t num_input;\n+\t/* Number of input tensors (Max 8) */\n+\tuint8_t num_input;\n \n-\t\t/* Number of output tensors (Max 8) */\n-\t\tuint8_t num_output;\n-\t\tuint8_t reserved1;\n+\t/* Number of output tensors (Max 8) */\n+\tuint8_t num_output;\n+\tuint8_t reserved_1;\n \n-\t\t/* Total input size in bytes */\n-\t\tuint32_t input_size;\n+\t/* Total input size in bytes */\n+\tuint32_t input_size;\n \n-\t\t/* Total output size in bytes */\n-\t\tuint32_t output_size;\n+\t/* Total output size in bytes */\n+\tuint32_t output_size;\n \n-\t\t/* Table size in bytes */\n-\t\tuint32_t table_size;\n+\t/* Table size in bytes */\n+\tuint32_t table_size;\n \n-\t\t/* Number of layers in the network */\n-\t\tuint32_t num_layers;\n-\t\tuint32_t reserved2;\n+\t/* Number of layers in the network */\n+\tuint32_t num_layers;\n+\tuint32_t reserved_2;\n \n-\t\t/* Floor of absolute OCM region */\n-\t\tuint64_t ocm_tmp_range_floor;\n+\t/* Floor of absolute OCM region */\n+\tuint64_t ocm_tmp_range_floor;\n \n-\t\t/* Relative OCM start address of WB data block */\n-\t\tuint64_t ocm_wb_range_start;\n+\t/* Relative OCM start address of WB data block */\n+\tuint64_t ocm_wb_range_start;\n \n-\t\t/* Relative OCM end address of WB data block */\n-\t\tuint64_t ocm_wb_range_end;\n+\t/* Relative OCM end address of WB data block */\n+\tuint64_t ocm_wb_range_end;\n \n-\t\t/* Relative DDR start address of WB data block */\n-\t\tuint64_t ddr_wb_range_start;\n+\t/* Relative DDR start address of WB data block */\n+\tuint64_t ddr_wb_range_start;\n \n-\t\t/* Relative DDR end address of all outputs */\n-\t\tuint64_t ddr_wb_range_end;\n+\t/* Relative DDR end address of all outputs */\n+\tuint64_t ddr_wb_range_end;\n \n-\t\t/* Relative DDR start address of all inputs */\n-\t\tuint64_t ddr_input_range_start;\n+\t/* Relative DDR start address of all inputs */\n+\tuint64_t ddr_input_range_start;\n \n-\t\t/* Relative DDR end address of all inputs */\n-\t\tuint64_t ddr_input_range_end;\n+\t/* Relative DDR end address of all inputs */\n+\tuint64_t ddr_input_range_end;\n \n-\t\t/* Relative DDR start address of all outputs */\n-\t\tuint64_t ddr_output_range_start;\n+\t/* Relative DDR start address of all outputs */\n+\tuint64_t ddr_output_range_start;\n \n-\t\t/* Relative DDR end address of all outputs */\n-\t\tuint64_t ddr_output_range_end;\n+\t/* Relative DDR end address of all outputs */\n+\tuint64_t ddr_output_range_end;\n \n-\t\t/* Compiler version */\n-\t\tuint8_t compiler_version[8];\n+\t/* Compiler version */\n+\tuint8_t compiler_version[8];\n \n-\t\t/* CDK version */\n-\t\tuint8_t cdk_version[4];\n+\t/* CDK version */\n+\tuint8_t cdk_version[4];\n \n-\t\t/* Lower batch optimization support\n-\t\t * 0 - No,\n-\t\t * 1 - Yes\n-\t\t */\n-\t\tuint8_t supports_lower_batch_size_optimization;\n-\t\tuint8_t reserved3[59];\n-\t} model;\n+\t/* Lower batch optimization support\n+\t * 0 - No,\n+\t * 1 - Yes\n+\t */\n+\tuint8_t supports_lower_batch_size_optimization;\n+\tuint8_t reserved_3[59];\n+};\n \n-\t/* Init section (64-byte) */\n-\tstruct {\n-\t\tuint32_t file_offset;\n-\t\tuint32_t file_size;\n-\t\tuint8_t reserved[56];\n-\t} init_model;\n+/* Init section (64-byte) */\n+struct cn10k_ml_model_metadata_init_section {\n+\tuint32_t file_offset;\n+\tuint32_t file_size;\n+\tuint8_t reserved[56];\n+};\n \n-\t/* Main section (64-byte) */\n-\tstruct {\n-\t\tuint32_t file_offset;\n-\t\tuint32_t file_size;\n-\t\tuint8_t reserved[56];\n-\t} main_model;\n+/* Main section (64-byte) */\n+struct cn10k_ml_model_metadata_main_section {\n+\tuint32_t file_offset;\n+\tuint32_t file_size;\n+\tuint8_t reserved[56];\n+};\n \n-\t/* Finish section (64-byte) */\n-\tstruct {\n-\t\tuint32_t file_offset;\n-\t\tuint32_t file_size;\n-\t\tuint8_t reserved[56];\n-\t} finish_model;\n+/* Finish section (64-byte) */\n+struct cn10k_ml_model_metadata_finish_section {\n+\tuint32_t file_offset;\n+\tuint32_t file_size;\n+\tuint8_t reserved[56];\n+};\n \n-\tuint8_t reserved1[512]; /* End of 2k bytes */\n+/* Weights and Bias (64-byte) */\n+struct cn10k_ml_model_metadata_weights_bias_section {\n+\t/* Memory offset, set to ddr_wb_range_start */\n+\tuint64_t mem_offset;\n+\tuint32_t file_offset;\n+\tuint32_t file_size;\n \n-\t/* Weights and Bias (64-byte) */\n+\t/* Relocatable flag for WB\n+\t * 1 = Relocatable\n+\t * 2 = Not relocatable\n+\t */\n+\tuint8_t relocatable;\n+\tuint8_t reserved[47];\n+};\n+\n+/* Input section (64-byte per input) */\n+struct cn10k_ml_model_metadata_input_section {\n+\t/* DDR offset (in OCM absolute addresses for input) */\n+\tuint64_t mem_offset;\n+\n+\t/* Relocatable flag\n+\t * 1 = Relocatable\n+\t * 2 = Not relocatable\n+\t */\n+\tuint8_t relocatable;\n+\n+\t/* Input quantization\n+\t * 1 = Requires quantization\n+\t * 2 = Pre-quantized\n+\t */\n+\tuint8_t quantize;\n+\n+\t/* Type of incoming input\n+\t * 1 = INT8, 2 = UINT8, 3 = INT16, 4 = UINT16,\n+\t * 5 = INT32, 6 = UINT32, 7 = FP16, 8 = FP32\n+\t */\n+\tuint8_t input_type;\n+\n+\t/* Type of input required by model\n+\t * 1 = INT8, 2 = UINT8, 3 = INT16, 4 = UINT16,\n+\t * 5 = INT32, 6 = UINT32, 7 = FP16, 8 = FP32\n+\t */\n+\tuint8_t model_input_type;\n+\n+\t/* float_32 qscale value\n+\t * quantized = non-quantized * qscale\n+\t */\n+\tfloat qscale;\n+\n+\t/* Input shape */\n \tstruct {\n-\t\t/* Memory offset, set to ddr_wb_range_start */\n-\t\tuint64_t mem_offset;\n-\t\tuint32_t file_offset;\n-\t\tuint32_t file_size;\n-\n-\t\t/* Relocatable flag for WB\n-\t\t * 1 = Relocatable\n-\t\t * 2 = Not relocatable\n+\t\t/* Input format\n+\t\t * 1 = NCHW\n+\t\t * 2 = NHWC\n \t\t */\n-\t\tuint8_t relocatable;\n-\t\tuint8_t reserved[47];\n-\t} weights_bias;\n+\t\tuint8_t format;\n+\t\tuint8_t reserved[3];\n+\t\tuint32_t w;\n+\t\tuint32_t x;\n+\t\tuint32_t y;\n+\t\tuint32_t z;\n+\t} shape;\n+\tuint8_t reserved[4];\n+\n+\t/* Name of input */\n+\tuint8_t input_name[MRVL_ML_INPUT_NAME_LEN];\n+\n+\t/* DDR range end\n+\t * new = mem_offset + size_bytes - 1\n+\t */\n+\tuint64_t ddr_range_end;\n+};\n \n-\t/* Input (512-byte, 64-byte per input) provisioned for 8 inputs */\n-\tstruct {\n-\t\t/* DDR offset (in OCM absolute addresses for input) */\n-\t\tuint64_t mem_offset;\n+/* Output section (64-byte per output) */\n+struct cn10k_ml_model_metadata_output_section {\n+\t/* DDR offset in OCM absolute addresses for output */\n+\tuint64_t mem_offset;\n \n-\t\t/* Relocatable flag\n-\t\t * 1 = Relocatable\n-\t\t * 2 = Not relocatable\n-\t\t */\n-\t\tuint8_t relocatable;\n+\t/* Relocatable flag\n+\t * 1 = Relocatable\n+\t * 2 = Not relocatable\n+\t */\n+\tuint8_t relocatable;\n \n-\t\t/* Input quantization\n-\t\t * 1 = Requires quantization\n-\t\t * 2 = Pre-quantized\n-\t\t */\n-\t\tuint8_t quantize;\n+\t/* Output dequantization\n+\t * 1 = De-quantization required\n+\t * 2 = De-quantization not required\n+\t */\n+\tuint8_t dequantize;\n \n-\t\t/* Type of incoming input\n-\t\t * 1 = INT8, 2 = UINT8, 3 = INT16, 4 = UINT16,\n-\t\t * 5 = INT32, 6 = UINT32, 7 = FP16, 8 = FP32\n-\t\t */\n-\t\tuint8_t input_type;\n+\t/* Type of outgoing output\n+\t * 1 = INT8, 2 = UINT8, 3 = INT16, 4 = UINT16\n+\t * 5 = INT32, 6 = UINT32, 7 = FP16, 8 = FP32\n+\t */\n+\tuint8_t output_type;\n \n-\t\t/* Type of input required by model\n-\t\t * 1 = INT8, 2 = UINT8, 3 = INT16, 4 = UINT16,\n-\t\t * 5 = INT32, 6 = UINT32, 7 = FP16, 8 = FP32\n-\t\t */\n-\t\tuint8_t model_input_type;\n+\t/* Type of output produced by model\n+\t * 1 = INT8, 2 = UINT8, 3 = INT16, 4 = UINT16\n+\t * 5 = INT32, 6 = UINT32, 7 = FP16, 8 = FP32\n+\t */\n+\tuint8_t model_output_type;\n \n-\t\t/* float_32 qscale value\n-\t\t * quantized = non-quantized * qscale\n-\t\t */\n-\t\tfloat qscale;\n-\n-\t\t/* Input shape */\n-\t\tstruct {\n-\t\t\t/* Input format\n-\t\t\t * 1 = NCHW\n-\t\t\t * 2 = NHWC\n-\t\t\t */\n-\t\t\tuint8_t format;\n-\t\t\tuint8_t reserved[3];\n-\t\t\tuint32_t w;\n-\t\t\tuint32_t x;\n-\t\t\tuint32_t y;\n-\t\t\tuint32_t z;\n-\t\t} shape;\n-\t\tuint8_t reserved[4];\n-\n-\t\t/* Name of input */\n-\t\tuint8_t input_name[MRVL_ML_INPUT_NAME_LEN];\n-\n-\t\t/* DDR range end\n-\t\t * new = mem_offset + size_bytes - 1\n-\t\t */\n-\t\tuint64_t ddr_range_end;\n-\t} input[MRVL_ML_INPUT_OUTPUT_SIZE];\n+\t/* float_32 dscale value\n+\t * dequantized = quantized * dscale\n+\t */\n+\tfloat dscale;\n \n-\t/* Output (512 byte, 64-byte per input) provisioned for 8 outputs */\n-\tstruct {\n-\t\t/* DDR offset in OCM absolute addresses for output */\n-\t\tuint64_t mem_offset;\n+\t/* Number of items in the output */\n+\tuint32_t size;\n+\tuint8_t reserved[20];\n \n-\t\t/* Relocatable flag\n-\t\t * 1 = Relocatable\n-\t\t * 2 = Not relocatable\n-\t\t */\n-\t\tuint8_t relocatable;\n+\t/* DDR range end\n+\t * new = mem_offset + size_bytes - 1\n+\t */\n+\tuint64_t ddr_range_end;\n+\tuint8_t output_name[MRVL_ML_OUTPUT_NAME_LEN];\n+};\n \n-\t\t/* Output dequantization\n-\t\t * 1 = De-quantization required\n-\t\t * 2 = De-quantization not required\n-\t\t */\n-\t\tuint8_t dequantize;\n+/* Model data */\n+struct cn10k_ml_model_metadata_data_section {\n+\tuint8_t reserved[4068];\n \n-\t\t/* Type of outgoing output\n-\t\t * 1 = INT8, 2 = UINT8, 3 = INT16, 4 = UINT16\n-\t\t * 5 = INT32, 6 = UINT32, 7 = FP16, 8 = FP32\n-\t\t */\n-\t\tuint8_t output_type;\n+\t/* Beta: xx.xx.xx.xx,\n+\t * Later: YYYYMM.xx.xx\n+\t */\n+\tuint8_t compiler_version[8];\n \n-\t\t/* Type of output produced by model\n-\t\t * 1 = INT8, 2 = UINT8, 3 = INT16, 4 = UINT16\n-\t\t * 5 = INT32, 6 = UINT32, 7 = FP16, 8 = FP32\n-\t\t */\n-\t\tuint8_t model_output_type;\n+\t/* M1K CDK version (xx.xx.xx.xx) */\n+\tuint8_t m1k_cdk_version[4];\n+};\n \n-\t\t/* float_32 dscale value\n-\t\t * dequantized = quantized * dscale\n-\t\t */\n-\t\tfloat dscale;\n+/* Model file metadata structure */\n+struct cn10k_ml_model_metadata {\n+\t/* Header (256-byte) */\n+\tstruct cn10k_ml_model_metadata_header header;\n \n-\t\t/* Number of items in the output */\n-\t\tuint32_t size;\n-\t\tuint8_t reserved[20];\n+\t/* Model information (256-byte) */\n+\tstruct cn10k_ml_model_metadata_model model;\n \n-\t\t/* DDR range end\n-\t\t * new = mem_offset + size_bytes - 1\n-\t\t */\n-\t\tuint64_t ddr_range_end;\n-\t\tuint8_t output_name[MRVL_ML_OUTPUT_NAME_LEN];\n-\t} output[MRVL_ML_INPUT_OUTPUT_SIZE];\n+\t/* Init section (64-byte) */\n+\tstruct cn10k_ml_model_metadata_init_section init_model;\n \n-\tuint8_t reserved2[1792];\n+\t/* Main section (64-byte) */\n+\tstruct cn10k_ml_model_metadata_main_section main_model;\n \n-\t/* Model data */\n-\tstruct {\n-\t\tuint8_t reserved1[4068];\n+\t/* Finish section (64-byte) */\n+\tstruct cn10k_ml_model_metadata_finish_section finish_model;\n \n-\t\t/* Beta: xx.xx.xx.xx,\n-\t\t * Later: YYYYMM.xx.xx\n-\t\t */\n-\t\tuint8_t compiler_version[8];\n+\tuint8_t reserved_1[512]; /* End of 2k bytes */\n+\n+\t/* Weights and Bias (64-byte) */\n+\tstruct cn10k_ml_model_metadata_weights_bias_section weights_bias;\n+\n+\t/* Input (512-bytes, 64-byte per input) provisioned for 8 inputs */\n+\tstruct cn10k_ml_model_metadata_input_section input[MRVL_ML_INPUT_OUTPUT_SIZE];\n+\n+\t/* Output (512-bytes, 64-byte per output) provisioned for 8 outputs */\n+\tstruct cn10k_ml_model_metadata_output_section output[MRVL_ML_INPUT_OUTPUT_SIZE];\n \n-\t\t/* M1K CDK version (xx.xx.xx.xx) */\n-\t\tuint8_t m1k_cdk_version[4];\n-\t} data;\n+\tuint8_t reserved_2[1792];\n+\n+\t/* Model data */\n+\tstruct cn10k_ml_model_metadata_data_section data;\n \n \t/* Hidden 16 bytes of magic code */\n-\tuint8_t reserved3[16];\n+\tuint8_t reserved_3[16];\n };\n \n /* Model address structure */\n", "prefixes": [ "v1", "1/3" ] }