Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/126238/?format=api
{ "id": 126238, "url": "http://patches.dpdk.org/api/patches/126238/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20230418133942.2088671-2-kevin.osullivan@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20230418133942.2088671-2-kevin.osullivan@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20230418133942.2088671-2-kevin.osullivan@intel.com", "date": "2023-04-18T13:39:41", "name": "[v4,1/2] crypto/qat: add cipher-crc offload support to fw interface", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "0d04aaa8ad6cb4d102cf666f9626ad08b43766ec", "submitter": { "id": 2860, "url": "http://patches.dpdk.org/api/people/2860/?format=api", "name": "Kevin O'Sullivan", "email": "kevin.osullivan@intel.com" }, "delegate": { "id": 6690, "url": "http://patches.dpdk.org/api/users/6690/?format=api", "username": "akhil", "first_name": "akhil", "last_name": "goyal", "email": "gakhil@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20230418133942.2088671-2-kevin.osullivan@intel.com/mbox/", "series": [ { "id": 27759, "url": "http://patches.dpdk.org/api/series/27759/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=27759", "date": "2023-04-18T13:39:40", "name": "crypto/qat: add cipher-crc offload feature", "version": 4, "mbox": "http://patches.dpdk.org/series/27759/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/126238/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/126238/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 3E8114297D;\n\tTue, 18 Apr 2023 15:40:21 +0200 (CEST)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 2B3C242BD9;\n\tTue, 18 Apr 2023 15:40:21 +0200 (CEST)", "from mga11.intel.com (mga11.intel.com [192.55.52.93])\n by mails.dpdk.org (Postfix) with ESMTP id 38D4242BC9\n for <dev@dpdk.org>; Tue, 18 Apr 2023 15:40:19 +0200 (CEST)", "from fmsmga003.fm.intel.com ([10.253.24.29])\n by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 18 Apr 2023 06:40:18 -0700", "from silpixa00401033.ir.intel.com ([10.55.129.124])\n by FMSMGA003.fm.intel.com with ESMTP; 18 Apr 2023 06:40:17 -0700" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1681825219; x=1713361219;\n h=from:to:cc:subject:date:message-id:in-reply-to:\n references:mime-version:content-transfer-encoding;\n bh=0XHN3gaMFBblZaEALFc8wn26YWXjM8zCqle5SFa7PyU=;\n b=ZtU18yfN+jMfEIyboZ294FVcbxIC2qBXq8AAPtcjU9IvhmSsMrHJ7wEz\n 4+1WOHLseMdRgD4lNm30B3hmChTeXMMlnizGB4bChZE8CqtwUsRcUD5a+\n N/+aZHr0fih3EVR/4x4TZ76qG84GbtJbZz7asN0nVbWCGkGx4BP+7bhVz\n lN+HbZgDCw8WplPlfyjuV2b7qc9DwOhF96LsaLUdW622x/j+jiRZ0CrKP\n wtIpmMb0z9xwIkI5xwS1BNaK23rkcjITuTxRano8ijJcRnxVLA8uiNBQu\n h7f9Lxy0R3KNEHdGv2xqqSkBxDho+ZI2sROfAe9jZS3xKKebWfm3TPIy3 Q==;", "X-IronPort-AV": [ "E=McAfee;i=\"6600,9927,10684\"; a=\"342660719\"", "E=Sophos;i=\"5.99,207,1677571200\"; d=\"scan'208\";a=\"342660719\"", "E=McAfee;i=\"6600,9927,10684\"; a=\"780506907\"", "E=Sophos;i=\"5.99,207,1677571200\"; d=\"scan'208\";a=\"780506907\"" ], "X-ExtLoop1": "1", "From": "Kevin O'Sullivan <kevin.osullivan@intel.com>", "To": "dev@dpdk.org", "Cc": "kai.ji@intel.com, Kevin O'Sullivan <kevin.osullivan@intel.com>,\n David Coyle <david.coyle@intel.com>", "Subject": "[PATCH v4 1/2] crypto/qat: add cipher-crc offload support to fw\n interface", "Date": "Tue, 18 Apr 2023 13:39:41 +0000", "Message-Id": "<20230418133942.2088671-2-kevin.osullivan@intel.com>", "X-Mailer": "git-send-email 2.34.1", "In-Reply-To": "<20230418133942.2088671-1-kevin.osullivan@intel.com>", "References": "<20230313142603.234169-1-kevin.osullivan@intel.com>\n <20230418133942.2088671-1-kevin.osullivan@intel.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "This patch adds support to the QAT firmware interface header files\nfor the combined cipher-crc offload feature for DOCSIS on gen2/gen3/\ngen4 QAT devices. The main change is that new structures have been\nadded for the crc content descriptor for the various generations.\n\nSigned-off-by: Kevin O'Sullivan <kevin.osullivan@intel.com>\nSigned-off-by: David Coyle <david.coyle@intel.com>\nAcked-by: Kai Ji <kai.ji@intel.com>\n---\n drivers/common/qat/qat_adf/icp_qat_fw.h | 1 -\n drivers/common/qat/qat_adf/icp_qat_fw_la.h | 3 +-\n drivers/common/qat/qat_adf/icp_qat_hw.h | 133 +++++++++++++++++++++\n 3 files changed, 135 insertions(+), 2 deletions(-)", "diff": "diff --git a/drivers/common/qat/qat_adf/icp_qat_fw.h b/drivers/common/qat/qat_adf/icp_qat_fw.h\nindex be10fc9bde..3aa17ae041 100644\n--- a/drivers/common/qat/qat_adf/icp_qat_fw.h\n+++ b/drivers/common/qat/qat_adf/icp_qat_fw.h\n@@ -4,7 +4,6 @@\n #ifndef _ICP_QAT_FW_H_\n #define _ICP_QAT_FW_H_\n #include <sys/types.h>\n-#include \"icp_qat_hw.h\"\n \n #define QAT_FIELD_SET(flags, val, bitpos, mask) \\\n { (flags) = (((flags) & (~((mask) << (bitpos)))) | \\\ndiff --git a/drivers/common/qat/qat_adf/icp_qat_fw_la.h b/drivers/common/qat/qat_adf/icp_qat_fw_la.h\nindex c4901eb869..227a6cebc8 100644\n--- a/drivers/common/qat/qat_adf/icp_qat_fw_la.h\n+++ b/drivers/common/qat/qat_adf/icp_qat_fw_la.h\n@@ -18,7 +18,8 @@ enum icp_qat_fw_la_cmd_id {\n \tICP_QAT_FW_LA_CMD_MGF1 = 9,\n \tICP_QAT_FW_LA_CMD_AUTH_PRE_COMP = 10,\n \tICP_QAT_FW_LA_CMD_CIPHER_PRE_COMP = 11,\n-\tICP_QAT_FW_LA_CMD_DELIMITER = 12\n+\tICP_QAT_FW_LA_CMD_CIPHER_CRC = 17,\n+\tICP_QAT_FW_LA_CMD_DELIMITER = 18\n };\n \n #define ICP_QAT_FW_LA_ICV_VER_STATUS_PASS ICP_QAT_FW_COMN_STATUS_FLAG_OK\ndiff --git a/drivers/common/qat/qat_adf/icp_qat_hw.h b/drivers/common/qat/qat_adf/icp_qat_hw.h\nindex 866147cd77..8b864e1630 100644\n--- a/drivers/common/qat/qat_adf/icp_qat_hw.h\n+++ b/drivers/common/qat/qat_adf/icp_qat_hw.h\n@@ -4,6 +4,8 @@\n #ifndef _ICP_QAT_HW_H_\n #define _ICP_QAT_HW_H_\n \n+#include \"icp_qat_fw.h\"\n+\n #define ADF_C4XXXIOV_VFLEGFUSES_OFFSET\t0x4C\n #define ADF1_C4XXXIOV_VFLEGFUSES_LEN\t4\n \n@@ -260,14 +262,19 @@ enum icp_qat_hw_cipher_convert {\n };\n \n #define QAT_CIPHER_MODE_BITPOS 4\n+#define QAT_CIPHER_MODE_LE_BITPOS 28\n #define QAT_CIPHER_MODE_MASK 0xF\n #define QAT_CIPHER_ALGO_BITPOS 0\n+#define QAT_CIPHER_ALGO_LE_BITPOS 24\n #define QAT_CIPHER_ALGO_MASK 0xF\n #define QAT_CIPHER_CONVERT_BITPOS 9\n+#define QAT_CIPHER_CONVERT_LE_BITPOS 17\n #define QAT_CIPHER_CONVERT_MASK 0x1\n #define QAT_CIPHER_DIR_BITPOS 8\n+#define QAT_CIPHER_DIR_LE_BITPOS 16\n #define QAT_CIPHER_DIR_MASK 0x1\n #define QAT_CIPHER_AEAD_HASH_CMP_LEN_BITPOS 10\n+#define QAT_CIPHER_AEAD_HASH_CMP_LEN_LE_BITPOS 18\n #define QAT_CIPHER_AEAD_HASH_CMP_LEN_MASK 0x1F\n #define QAT_CIPHER_MODE_F8_KEY_SZ_MULT 2\n #define QAT_CIPHER_MODE_XTS_KEY_SZ_MULT 2\n@@ -281,7 +288,9 @@ enum icp_qat_hw_cipher_convert {\n #define QAT_CIPHER_AEAD_AAD_UPPER_SHIFT 8\n #define QAT_CIPHER_AEAD_AAD_SIZE_LOWER_MASK 0xFF\n #define QAT_CIPHER_AEAD_AAD_SIZE_UPPER_MASK 0x3F\n+#define QAT_CIPHER_AEAD_AAD_SIZE_MASK 0x3FFF\n #define QAT_CIPHER_AEAD_AAD_SIZE_BITPOS 16\n+#define QAT_CIPHER_AEAD_AAD_SIZE_LE_BITPOS 0\n #define ICP_QAT_HW_CIPHER_CONFIG_BUILD_UPPER(aad_size) \\\n \t({ \\\n \ttypeof(aad_size) aad_size1 = aad_size; \\\n@@ -362,6 +371,28 @@ struct icp_qat_hw_cipher_algo_blk {\n \tuint8_t key[ICP_QAT_HW_CIPHER_MAX_KEY_SZ];\n } __rte_cache_aligned;\n \n+struct icp_qat_hw_gen2_crc_cd {\n+\tuint32_t flags;\n+\tuint32_t reserved1[5];\n+\tuint32_t initial_crc;\n+\tuint32_t reserved2[3];\n+};\n+\n+#define QAT_GEN3_COMP_REFLECT_IN_BITPOS 17\n+#define QAT_GEN3_COMP_REFLECT_IN_MASK 0x1\n+#define QAT_GEN3_COMP_REFLECT_OUT_BITPOS 18\n+#define QAT_GEN3_COMP_REFLECT_OUT_MASK 0x1\n+\n+struct icp_qat_hw_gen3_crc_cd {\n+\tuint32_t flags;\n+\tuint32_t reserved1[3];\n+\tuint32_t polynomial;\n+\tuint32_t xor_val;\n+\tuint32_t reserved2[2];\n+\tuint32_t initial_crc;\n+\tuint32_t reserved3;\n+};\n+\n struct icp_qat_hw_ucs_cipher_config {\n \tuint32_t val;\n \tuint32_t reserved[3];\n@@ -372,6 +403,108 @@ struct icp_qat_hw_cipher_algo_blk20 {\n \tuint8_t key[ICP_QAT_HW_CIPHER_MAX_KEY_SZ];\n } __rte_cache_aligned;\n \n+enum icp_qat_hw_ucs_cipher_reflect_out {\n+\tICP_QAT_HW_CIPHER_UCS_REFLECT_OUT_DISABLED = 0,\n+\tICP_QAT_HW_CIPHER_UCS_REFLECT_OUT_ENABLED = 1,\n+};\n+\n+enum icp_qat_hw_ucs_cipher_reflect_in {\n+\tICP_QAT_HW_CIPHER_UCS_REFLECT_IN_DISABLED = 0,\n+\tICP_QAT_HW_CIPHER_UCS_REFLECT_IN_ENABLED = 1,\n+};\n+\n+enum icp_qat_hw_ucs_cipher_crc_encoding {\n+\tICP_QAT_HW_CIPHER_UCS_CRC_NOT_REQUIRED = 0,\n+\tICP_QAT_HW_CIPHER_UCS_CRC32 = 1,\n+\tICP_QAT_HW_CIPHER_UCS_CRC64 = 2,\n+};\n+\n+#define QAT_CIPHER_UCS_REFLECT_OUT_LE_BITPOS 17\n+#define QAT_CIPHER_UCS_REFLECT_OUT_MASK 0x1\n+#define QAT_CIPHER_UCS_REFLECT_IN_LE_BITPOS 16\n+#define QAT_CIPHER_UCS_REFLECT_IN_MASK 0x1\n+#define QAT_CIPHER_UCS_CRC_ENCODING_LE_BITPOS 14\n+#define QAT_CIPHER_UCS_CRC_ENCODING_MASK 0x3\n+\n+struct icp_qat_fw_ucs_slice_cipher_config {\n+\tenum icp_qat_hw_cipher_mode mode;\n+\tenum icp_qat_hw_cipher_algo algo;\n+\tuint16_t hash_cmp_val;\n+\tenum icp_qat_hw_cipher_dir dir;\n+\tuint16_t associated_data_len_in_bytes;\n+\tenum icp_qat_hw_ucs_cipher_reflect_out crc_reflect_out;\n+\tenum icp_qat_hw_ucs_cipher_reflect_in crc_reflect_in;\n+\tenum icp_qat_hw_ucs_cipher_crc_encoding crc_encoding;\n+};\n+\n+struct icp_qat_hw_gen4_crc_cd {\n+\tuint32_t ucs_config[4];\n+\tuint32_t polynomial;\n+\tuint32_t reserved1;\n+\tuint32_t xor_val;\n+\tuint32_t reserved2;\n+\tuint32_t initial_crc;\n+\tuint32_t reserved3;\n+};\n+\n+static inline uint32_t\n+ICP_QAT_HW_UCS_CIPHER_GEN4_BUILD_CONFIG_LOWER(\n+\tstruct icp_qat_fw_ucs_slice_cipher_config csr)\n+{\n+\tuint32_t val32 = 0;\n+\n+\tQAT_FIELD_SET(val32,\n+\t\t\tcsr.mode,\n+\t\t\tQAT_CIPHER_MODE_LE_BITPOS,\n+\t\t\tQAT_CIPHER_MODE_MASK);\n+\n+\tQAT_FIELD_SET(val32,\n+\t\t\tcsr.algo,\n+\t\t\tQAT_CIPHER_ALGO_LE_BITPOS,\n+\t\t\tQAT_CIPHER_ALGO_MASK);\n+\n+\tQAT_FIELD_SET(val32,\n+\t\t\tcsr.hash_cmp_val,\n+\t\t\tQAT_CIPHER_AEAD_HASH_CMP_LEN_LE_BITPOS,\n+\t\t\tQAT_CIPHER_AEAD_HASH_CMP_LEN_MASK);\n+\n+\tQAT_FIELD_SET(val32,\n+\t\t\tcsr.dir,\n+\t\t\tQAT_CIPHER_DIR_LE_BITPOS,\n+\t\t\tQAT_CIPHER_DIR_MASK);\n+\n+\treturn rte_bswap32(val32);\n+}\n+\n+static inline uint32_t\n+ICP_QAT_HW_UCS_CIPHER_GEN4_BUILD_CONFIG_UPPER(\n+\tstruct icp_qat_fw_ucs_slice_cipher_config csr)\n+{\n+\tuint32_t val32 = 0;\n+\n+\tQAT_FIELD_SET(val32,\n+\t\t\tcsr.associated_data_len_in_bytes,\n+\t\t\tQAT_CIPHER_AEAD_AAD_SIZE_LE_BITPOS,\n+\t\t\tQAT_CIPHER_AEAD_AAD_SIZE_MASK);\n+\n+\tQAT_FIELD_SET(val32,\n+\t\t\tcsr.crc_reflect_out,\n+\t\t\tQAT_CIPHER_UCS_REFLECT_OUT_LE_BITPOS,\n+\t\t\tQAT_CIPHER_UCS_REFLECT_OUT_MASK);\n+\n+\tQAT_FIELD_SET(val32,\n+\t\t\tcsr.crc_reflect_in,\n+\t\t\tQAT_CIPHER_UCS_REFLECT_IN_LE_BITPOS,\n+\t\t\tQAT_CIPHER_UCS_REFLECT_IN_MASK);\n+\n+\tQAT_FIELD_SET(val32,\n+\t\t\tcsr.crc_encoding,\n+\t\t\tQAT_CIPHER_UCS_CRC_ENCODING_LE_BITPOS,\n+\t\t\tQAT_CIPHER_UCS_CRC_ENCODING_MASK);\n+\n+\treturn rte_bswap32(val32);\n+}\n+\n /* ========================================================================= */\n /* COMPRESSION SLICE */\n /* ========================================================================= */\n", "prefixes": [ "v4", "1/2" ] }