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GET /api/patches/126231/?format=api
{ "id": 126231, "url": "http://patches.dpdk.org/api/patches/126231/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20230418092325.2578712-5-suanmingm@nvidia.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20230418092325.2578712-5-suanmingm@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20230418092325.2578712-5-suanmingm@nvidia.com", "date": "2023-04-18T09:23:24", "name": "[RFC,4/5] crypto/mlx5: add queue pair setup", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "77f27e7c82c1d78057ef185a5f2a7d07b45d6815", "submitter": { "id": 1887, "url": "http://patches.dpdk.org/api/people/1887/?format=api", "name": "Suanming Mou", "email": "suanmingm@nvidia.com" }, "delegate": { "id": 6690, "url": "http://patches.dpdk.org/api/users/6690/?format=api", "username": "akhil", "first_name": "akhil", "last_name": "goyal", "email": "gakhil@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20230418092325.2578712-5-suanmingm@nvidia.com/mbox/", "series": [ { "id": 27756, "url": "http://patches.dpdk.org/api/series/27756/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=27756", "date": "2023-04-18T09:23:20", "name": "crypto/mlx5: support AES-GCM", "version": 1, "mbox": "http://patches.dpdk.org/series/27756/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/126231/comments/", "check": "warning", "checks": "http://patches.dpdk.org/api/patches/126231/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 32B524297B;\n\tTue, 18 Apr 2023 11:24:29 +0200 (CEST)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 5C8E742D29;\n\tTue, 18 Apr 2023 11:24:11 +0200 (CEST)", "from NAM11-BN8-obe.outbound.protection.outlook.com\n (mail-bn8nam11on2041.outbound.protection.outlook.com [40.107.236.41])\n by mails.dpdk.org (Postfix) with ESMTP id 9174641149\n for <dev@dpdk.org>; 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helo=mail.nvidia.com; pr=C", "From": "Suanming Mou <suanmingm@nvidia.com>", "To": "<matan@nvidia.com>", "CC": "<rasland@nvidia.com>, <mkashani@nvidia.com>, <dev@dpdk.org>", "Subject": "[RFC PATCH 4/5] crypto/mlx5: add queue pair setup", "Date": "Tue, 18 Apr 2023 12:23:24 +0300", "Message-ID": "<20230418092325.2578712-5-suanmingm@nvidia.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20230418092325.2578712-1-suanmingm@nvidia.com>", "References": "<20230418092325.2578712-1-suanmingm@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[10.126.230.37]", "X-ClientProxiedBy": "rnnvmail203.nvidia.com (10.129.68.9) To\n rnnvmail201.nvidia.com (10.129.68.8)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "BN8NAM11FT039:EE_|BL1PR12MB5125:EE_", "X-MS-Office365-Filtering-Correlation-Id": "fb6e19e0-d8a5-4ffb-9ebf-08db3feea92f", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n AY5ahq5/J2XX9kuAx9DQ8lg7XrVPW653TIBZPnHKjzldFdSXFkRl26ToIBhO1uCo+Ikm0NIL+ZW6/G2lir+bsMekSK0SpOlUSQWWy5w+8iMaWMPSGK/rHvIHSFBGG6pRwdUXBpmf3FYPZXjy1iqF1780TwkZalexGpLk15O1Vkp/oPpLirlN8C8xD0IMJsB7NqfHyuMXv0A1QATqZPYTdgrY67U3dIS04Nwr8fnai77ImISDxchIR2WJGXUKFs7C/rmv5IYFoQDDfJtdAyp1ZNcVxmEStXtYPh4CCB7czMGhQECiXxkPGjNMgmSzGaVFiDYeoXHA5M8Q+bxon2ZJLv2lzPGSs8tR4GWlh1u6BbSbl3Vt1ZLmGG+YvEWEJop56XUkcnfKpqNgebuIkLGKnMZjI3BYTgEvFcNQAORwwLsPZt0ufRBabfzEbDTMXgeqScyRNOPOW7UmIQhsIyXDCwp/vm4MtogtLTGT6tmxWKxIeTfq5r9M3sUUbZIyil5aYlyXIm1/DqL/FKL/My/6NQtFOv1HXKYrr38xZh4VOK33wf+sQc4wk4sXzjxJ8YGVuV8P3PUbiCwQUnPpMXy+ly+1R0j2xaBtBXfpy5FSL76rA0HaPS4Ka8HTROPImuaik1+woCKLvVJjqc7I9k9sVq9EYx53IXbUizn+0hhjQDho2cNmtKyegp5X5gd6h0xLGXCaE97UG1jHvf1sHpIrxxJWGBz9uKWZL45OLUNOTQZUTgBJkWCIgW6+qds0Ma+OUO2hVb4l2bVaFS3kbgoTVkaQ+o+CmJt8ez8rk3vzd34=", "X-Forefront-Antispam-Report": "CIP:216.228.117.161; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE;\n SFS:(13230028)(4636009)(136003)(376002)(346002)(396003)(39860400002)(451199021)(36840700001)(40470700004)(46966006)(36756003)(5660300002)(30864003)(2906002)(6862004)(8936002)(40480700001)(55016003)(86362001)(70206006)(70586007)(4326008)(82740400003)(41300700001)(82310400005)(356005)(8676002)(47076005)(336012)(34020700004)(426003)(36860700001)(54906003)(6286002)(1076003)(26005)(37006003)(16526019)(478600001)(316002)(40460700003)(6636002)(6666004)(186003)(7636003)(7696005)(2616005);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "18 Apr 2023 09:24:07.4262 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n fb6e19e0-d8a5-4ffb-9ebf-08db3feea92f", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n BN8NAM11FT039.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "BL1PR12MB5125", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Crypto queue pair is for handling the encryption/decryption operations.\n\nAs AES-GCM AEAD API provides AAD, mbuf, digest separately, low-level FW\nonly accepts the data in a single contiguous memory region, two internal\nQPs are created for AES-GCM queue pair. One for organizing the memory\nto be contiguous if they are not. The other is for crypto.\n\nIf the buffers are checked as implicitly contiguous, the buffer will be\nsent to the crypto QP directly for encryption/decryption. If not, the\nbuffers will be handled by the first UMR QP. The UMR QP will convert\nthe buffers to be contiguous one. Then the well organized \"new\" buffer\ncan be handled by crypto QP.\n\nThe crypto QP is initialized as follower, and UMR as leader. Once\ncrypto operation input buffer requires memory address space converting\nby UMR QP, the crypto QP processing will be triggered by UMR QP.\nOtherwise, the ring crypto QP doorbell directly.\n\nThe existing max_segs_num devarg is used for define how many segments\nthe chained mbuf contains same as AES-XTS before.\n\nSigned-off-by: Suanming Mou <suanmingm@nvidia.com>\n---\n drivers/common/mlx5/mlx5_devx_cmds.c | 6 +\n drivers/common/mlx5/mlx5_devx_cmds.h | 3 +\n drivers/common/mlx5/mlx5_prm.h | 24 +++\n drivers/crypto/mlx5/mlx5_crypto.c | 17 ++\n drivers/crypto/mlx5/mlx5_crypto.h | 12 ++\n drivers/crypto/mlx5/mlx5_crypto_gcm.c | 254 ++++++++++++++++++++++++++\n 6 files changed, 316 insertions(+)", "diff": "diff --git a/drivers/common/mlx5/mlx5_devx_cmds.c b/drivers/common/mlx5/mlx5_devx_cmds.c\nindex 8b51a75cc8..6be02c0a65 100644\n--- a/drivers/common/mlx5/mlx5_devx_cmds.c\n+++ b/drivers/common/mlx5/mlx5_devx_cmds.c\n@@ -2563,6 +2563,12 @@ mlx5_devx_cmd_create_qp(void *ctx,\n \t\t\t\t attr->dbr_umem_valid);\n \t\t\tMLX5_SET(qpc, qpc, dbr_umem_id, attr->dbr_umem_id);\n \t\t}\n+\t\tif (attr->cd_master)\n+\t\t\tMLX5_SET(qpc, qpc, cd_master, attr->cd_master);\n+\t\tif (attr->cd_slave_send)\n+\t\t\tMLX5_SET(qpc, qpc, cd_slave_send, attr->cd_slave_send);\n+\t\tif (attr->cd_slave_recv)\n+\t\t\tMLX5_SET(qpc, qpc, cd_slave_receive, attr->cd_slave_recv);\n \t\tMLX5_SET64(qpc, qpc, dbr_addr, attr->dbr_address);\n \t\tMLX5_SET64(create_qp_in, in, wq_umem_offset,\n \t\t\t attr->wq_umem_offset);\ndiff --git a/drivers/common/mlx5/mlx5_devx_cmds.h b/drivers/common/mlx5/mlx5_devx_cmds.h\nindex 79502cda08..e68aa077d7 100644\n--- a/drivers/common/mlx5/mlx5_devx_cmds.h\n+++ b/drivers/common/mlx5/mlx5_devx_cmds.h\n@@ -590,6 +590,9 @@ struct mlx5_devx_qp_attr {\n \tuint64_t wq_umem_offset;\n \tuint32_t user_index:24;\n \tuint32_t mmo:1;\n+\tuint32_t cd_master:1;\n+\tuint32_t cd_slave_send:1;\n+\tuint32_t cd_slave_recv:1;\n };\n \n struct mlx5_devx_virtio_q_couners_attr {\ndiff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h\nindex 25ff66ee7e..c8d73a8456 100644\n--- a/drivers/common/mlx5/mlx5_prm.h\n+++ b/drivers/common/mlx5/mlx5_prm.h\n@@ -594,6 +594,17 @@ struct mlx5_rdma_write_wqe {\n \tstruct mlx5_wqe_dseg dseg[];\n } __rte_packed;\n \n+struct mlx5_wqe_send_en_seg {\n+\tuint32_t reserve[2];\n+\tuint32_t sqnpc;\n+\tuint32_t qpn;\n+} __rte_packed;\n+\n+struct mlx5_wqe_send_en_wqe {\n+\tstruct mlx5_wqe_cseg ctr;\n+\tstruct mlx5_wqe_send_en_seg sseg;\n+} __rte_packed;\n+\n #ifdef PEDANTIC\n #pragma GCC diagnostic error \"-Wpedantic\"\n #endif\n@@ -668,6 +679,19 @@ union mlx5_gga_compress_opaque {\n \tuint32_t data[64];\n };\n \n+union mlx5_gga_crypto_opaque {\n+\tstruct {\n+\t\tuint32_t syndrome;\n+\t\tuint32_t reserved0[2];\n+\t\tstruct {\n+\t\t\tuint32_t iv[3];\n+\t\t\tuint32_t tag_size;\n+\t\t\tuint32_t aad_size;\n+\t\t} cp __rte_packed;\n+\t} __rte_packed;\n+\tuint8_t data[64];\n+};\n+\n struct mlx5_ifc_regexp_mmo_control_bits {\n \tuint8_t reserved_at_31[0x2];\n \tuint8_t le[0x1];\ndiff --git a/drivers/crypto/mlx5/mlx5_crypto.c b/drivers/crypto/mlx5/mlx5_crypto.c\nindex 8946f13e5e..f2e5b25c15 100644\n--- a/drivers/crypto/mlx5/mlx5_crypto.c\n+++ b/drivers/crypto/mlx5/mlx5_crypto.c\n@@ -849,12 +849,27 @@ mlx5_crypto_max_segs_num(uint16_t max_wqe_size)\n \treturn max_segs_cap;\n }\n \n+static __rte_always_inline int\n+mlx5_crypto_configure_gcm_wqe_size(struct mlx5_crypto_priv *priv)\n+{\n+\tuint32_t send_en_wqe_size;\n+\n+\tpriv->umr_wqe_size = RTE_ALIGN(sizeof(struct mlx5_umr_wqe) + sizeof(struct mlx5_wqe_dseg),\n+\t\tMLX5_SEND_WQE_BB);\n+\tsend_en_wqe_size = RTE_ALIGN(sizeof(struct mlx5_wqe_send_en_wqe), MLX5_SEND_WQE_BB);\n+\tpriv->umr_wqe_stride = priv->umr_wqe_size / MLX5_SEND_WQE_BB;\n+\tpriv->wqe_set_size = priv->umr_wqe_size + send_en_wqe_size;\n+\treturn 0;\n+}\n+\n static int\n mlx5_crypto_configure_wqe_size(struct mlx5_crypto_priv *priv,\n \t\t\t\tuint16_t max_wqe_size, uint32_t max_segs_num)\n {\n \tuint32_t rdmw_wqe_size, umr_wqe_size;\n \n+\tif (priv->is_gcm_dek_wrap)\n+\t\treturn mlx5_crypto_configure_gcm_wqe_size(priv);\n \tmlx5_crypto_get_wqe_sizes(max_segs_num, &umr_wqe_size,\n \t\t\t\t\t&rdmw_wqe_size);\n \tpriv->wqe_set_size = rdmw_wqe_size + umr_wqe_size;\n@@ -927,12 +942,14 @@ mlx5_crypto_dev_probe(struct mlx5_common_device *cdev,\n \tpriv->cdev = cdev;\n \tpriv->crypto_dev = crypto_dev;\n \tpriv->is_wrapped_mode = wrapped_mode;\n+\tpriv->max_segs_num = devarg_prms.max_segs_num;\n \tpriv->caps = mlx5_crypto_caps;\n \t/* Init and override AES-GCM configuration. */\n \tif (devarg_prms.is_aes_gcm) {\n \t\tret = mlx5_crypto_gcm_init(priv);\n \t\tif (ret) {\n \t\t\tDRV_LOG(ERR, \"Failed to init AES-GCM crypto.\");\n+\t\t\treturn -ENOTSUP;\n \t\t}\n \t}\n \tif (mlx5_devx_uar_prepare(cdev, &priv->uar) != 0) {\ndiff --git a/drivers/crypto/mlx5/mlx5_crypto.h b/drivers/crypto/mlx5/mlx5_crypto.h\nindex c34a860404..9945891ea8 100644\n--- a/drivers/crypto/mlx5/mlx5_crypto.h\n+++ b/drivers/crypto/mlx5/mlx5_crypto.h\n@@ -47,15 +47,27 @@ struct mlx5_crypto_qp {\n \tstruct mlx5_crypto_priv *priv;\n \tstruct mlx5_devx_cq cq_obj;\n \tstruct mlx5_devx_qp qp_obj;\n+\tstruct mlx5_devx_cq umr_cq_obj;\n+\tstruct mlx5_devx_qp umr_qp_obj;\n \tstruct rte_cryptodev_stats stats;\n \tstruct rte_crypto_op **ops;\n \tstruct mlx5_devx_obj **mkey; /* WQE's indirect mekys. */\n+\tstruct mlx5_klm *klm_array;\n \tstruct mlx5_mr_ctrl mr_ctrl;\n+\tstruct mlx5_pmd_mr opaque_mr;\n+\tstruct mlx5_pmd_mr klm_mr;\n+\t/* Crypto QP. */\n \tuint8_t *wqe;\n \tuint16_t entries_n;\n \tuint16_t pi;\n \tuint16_t ci;\n \tuint16_t db_pi;\n+\t/* UMR QP. */\n+\tuint8_t *umr_wqe;\n+\tuint16_t umr_wqbbs;\n+\tuint16_t umr_pi;\n+\tuint16_t umr_ci;\n+\tuint32_t umr_errors;\n };\n \n struct mlx5_crypto_dek {\ndiff --git a/drivers/crypto/mlx5/mlx5_crypto_gcm.c b/drivers/crypto/mlx5/mlx5_crypto_gcm.c\nindex 6c2c759fba..b67f22c591 100644\n--- a/drivers/crypto/mlx5/mlx5_crypto_gcm.c\n+++ b/drivers/crypto/mlx5/mlx5_crypto_gcm.c\n@@ -123,6 +123,257 @@ mlx5_crypto_sym_gcm_session_configure(struct rte_cryptodev *dev,\n \treturn 0;\n }\n \n+static void\n+mlx5_crypto_gcm_indirect_mkeys_release(struct mlx5_crypto_qp *qp, uint16_t n)\n+{\n+\tuint16_t i;\n+\n+\tfor (i = 0; i < n; i++)\n+\t\tif (qp->mkey[i])\n+\t\t\tclaim_zero(mlx5_devx_cmd_destroy(qp->mkey[i]));\n+}\n+\n+static int\n+mlx5_crypto_gcm_indirect_mkeys_prepare(struct mlx5_crypto_priv *priv,\n+\t\t\t\t struct mlx5_crypto_qp *qp)\n+{\n+\tuint32_t i;\n+\tstruct mlx5_devx_mkey_attr attr = {\n+\t\t.pd = priv->cdev->pdn,\n+\t\t.umr_en = 1,\n+\t\t.set_remote_rw = 1,\n+\t\t.klm_num = priv->max_segs_num,\n+\t};\n+\n+\tfor (i = 0; i < qp->entries_n; i++) {\n+\t\tattr.klm_array = (struct mlx5_klm *)&qp->klm_array[i * priv->max_segs_num];\n+\t\tqp->mkey[i] = mlx5_devx_cmd_mkey_create(priv->cdev->ctx, &attr);\n+\t\tif (!qp->mkey[i])\n+\t\t\tgoto error;\n+\t}\n+\treturn 0;\n+error:\n+\tDRV_LOG(ERR, \"Failed to allocate gcm indirect mkey.\");\n+\tmlx5_crypto_gcm_indirect_mkeys_release(qp, i);\n+\treturn -1;\n+}\n+\n+static int\n+mlx5_crypto_gcm_qp_release(struct rte_cryptodev *dev, uint16_t qp_id)\n+{\n+\tstruct mlx5_crypto_qp *qp = dev->data->queue_pairs[qp_id];\n+\n+\tif (qp->umr_qp_obj.qp != NULL)\n+\t\tmlx5_devx_qp_destroy(&qp->umr_qp_obj);\n+\tif (qp->umr_cq_obj.cq != NULL)\n+\t\tmlx5_devx_cq_destroy(&qp->umr_cq_obj);\n+\tif (qp->qp_obj.qp != NULL)\n+\t\tmlx5_devx_qp_destroy(&qp->qp_obj);\n+\tif (qp->cq_obj.cq != NULL)\n+\t\tmlx5_devx_cq_destroy(&qp->cq_obj);\n+\tif (qp->opaque_mr.obj != NULL) {\n+\t\tvoid *opaq = qp->opaque_mr.addr;\n+\n+\t\tmlx5_common_verbs_dereg_mr(&qp->opaque_mr);\n+\t\trte_free(opaq);\n+\t}\n+\tmlx5_crypto_gcm_indirect_mkeys_release(qp, qp->entries_n);\n+\tif (qp->klm_mr.obj != NULL) {\n+\t\tvoid *klm = qp->klm_mr.addr;\n+\n+\t\tmlx5_common_verbs_dereg_mr(&qp->klm_mr);\n+\t\trte_free(klm);\n+\t}\n+\tmlx5_mr_btree_free(&qp->mr_ctrl.cache_bh);\n+\trte_free(qp);\n+\tdev->data->queue_pairs[qp_id] = NULL;\n+\treturn 0;\n+}\n+\n+static void\n+mlx5_crypto_gcm_init_qp(struct mlx5_crypto_qp *qp)\n+{\n+\tvolatile struct mlx5_gga_wqe *restrict wqe =\n+\t\t\t\t (volatile struct mlx5_gga_wqe *)qp->qp_obj.wqes;\n+\tvolatile union mlx5_gga_crypto_opaque *opaq = qp->opaque_mr.addr;\n+\tconst uint32_t sq_ds = rte_cpu_to_be_32((qp->qp_obj.qp->id << 8) | 4u);\n+\tconst uint32_t flags = RTE_BE32(MLX5_COMP_ALWAYS <<\n+\t\t\t\t\tMLX5_COMP_MODE_OFFSET);\n+\tconst uint32_t opaq_lkey = rte_cpu_to_be_32(qp->opaque_mr.lkey);\n+\tint i;\n+\n+\t/* All the next fields state should stay constant. */\n+\tfor (i = 0; i < qp->entries_n; ++i, ++wqe) {\n+\t\twqe->sq_ds = sq_ds;\n+\t\twqe->flags = flags;\n+\t\twqe->opaque_lkey = opaq_lkey;\n+\t\twqe->opaque_vaddr = rte_cpu_to_be_64((uint64_t)(uintptr_t)&opaq[i]);\n+\t}\n+}\n+\n+static inline int\n+mlx5_crypto_gcm_umr_qp_setup(struct rte_cryptodev *dev, struct mlx5_crypto_qp *qp,\n+\t\t\t uint16_t log_nb_desc, int socket_id)\n+{\n+\tstruct mlx5_crypto_priv *priv = dev->data->dev_private;\n+\tstruct mlx5_devx_qp_attr attr = {0};\n+\tuint32_t ret;\n+\tuint32_t log_wqbb_n;\n+\tstruct mlx5_devx_cq_attr cq_attr = {\n+\t\t.use_first_only = 1,\n+\t\t.uar_page_id = mlx5_os_get_devx_uar_page_id(priv->uar.obj),\n+\t};\n+\tsize_t klm_size = priv->max_segs_num * sizeof(struct mlx5_klm);\n+\tvoid *klm_array;\n+\n+\tklm_array = rte_calloc(__func__, (size_t)qp->entries_n, klm_size, 64);\n+\tif (klm_array == NULL) {\n+\t\tDRV_LOG(ERR, \"Failed to allocate opaque memory.\");\n+\t\trte_errno = ENOMEM;\n+\t\treturn -1;\n+\t}\n+\tif (mlx5_common_verbs_reg_mr(priv->cdev->pd, klm_array,\n+\t\t\t\t qp->entries_n * klm_size,\n+\t\t\t\t &qp->klm_mr) != 0) {\n+\t\trte_free(klm_array);\n+\t\tDRV_LOG(ERR, \"Failed to register klm MR.\");\n+\t\trte_errno = ENOMEM;\n+\t\treturn -1;\n+\t}\n+\tqp->klm_array = (struct mlx5_klm *)qp->klm_mr.addr;\n+\tif (mlx5_devx_cq_create(priv->cdev->ctx, &qp->umr_cq_obj, log_nb_desc,\n+\t\t\t\t&cq_attr, socket_id) != 0) {\n+\t\tDRV_LOG(ERR, \"Failed to create UMR CQ.\");\n+\t\treturn -1;\n+\t}\n+\t/* Set UMR + SEND_EN WQE as maximum same with crypto. */\n+\tlog_wqbb_n = rte_log2_u32(qp->entries_n *\n+\t\t\t(priv->wqe_set_size / MLX5_SEND_WQE_BB));\n+\tattr.pd = priv->cdev->pdn;\n+\tattr.uar_index = mlx5_os_get_devx_uar_page_id(priv->uar.obj);\n+\tattr.cqn = qp->umr_cq_obj.cq->id;\n+\tattr.num_of_receive_wqes = 0;\n+\tattr.num_of_send_wqbbs = RTE_BIT32(log_wqbb_n);\n+\tattr.ts_format =\n+\t\tmlx5_ts_format_conv(priv->cdev->config.hca_attr.qp_ts_format);\n+\tattr.cd_master = 1;\n+\tret = mlx5_devx_qp_create(priv->cdev->ctx, &qp->umr_qp_obj,\n+\t\t\t\t attr.num_of_send_wqbbs * MLX5_SEND_WQE_BB,\n+\t\t\t\t &attr, socket_id);\n+\tif (ret) {\n+\t\tDRV_LOG(ERR, \"Failed to create UMR QP.\");\n+\t\treturn -1;\n+\t}\n+\tif (mlx5_devx_qp2rts(&qp->umr_qp_obj, qp->umr_qp_obj.qp->id)) {\n+\t\tDRV_LOG(ERR, \"Failed to change UMR QP state to RTS.\");\n+\t\treturn -1;\n+\t}\n+\t/* Save the UMR WQEBBS for checking the WQE boundary. */\n+\tqp->umr_wqbbs = attr.num_of_send_wqbbs;\n+\treturn 0;\n+}\n+\n+static int\n+mlx5_crypto_gcm_qp_setup(struct rte_cryptodev *dev, uint16_t qp_id,\n+\t\t\t const struct rte_cryptodev_qp_conf *qp_conf,\n+\t\t\t int socket_id)\n+{\n+\tstruct mlx5_crypto_priv *priv = dev->data->dev_private;\n+\tstruct mlx5_hca_attr *attr = &priv->cdev->config.hca_attr;\n+\tstruct mlx5_crypto_qp *qp;\n+\tstruct mlx5_devx_cq_attr cq_attr = {\n+\t\t.uar_page_id = mlx5_os_get_devx_uar_page_id(priv->uar.obj),\n+\t};\n+\tstruct mlx5_devx_qp_attr qp_attr = {\n+\t\t.pd = priv->cdev->pdn,\n+\t\t.uar_index = mlx5_os_get_devx_uar_page_id(priv->uar.obj),\n+\t\t.user_index = qp_id,\n+\t};\n+\tuint32_t log_ops_n = rte_log2_u32(qp_conf->nb_descriptors);\n+\tuint32_t entries = RTE_BIT32(log_ops_n);\n+\tuint32_t alloc_size = sizeof(*qp);\n+\tvoid *opaq_buf;\n+\tint ret;\n+\n+\talloc_size = RTE_ALIGN(alloc_size, RTE_CACHE_LINE_SIZE);\n+\talloc_size += (sizeof(struct rte_crypto_op *) +\n+\t\t sizeof(struct mlx5_devx_obj *)) * entries;\n+\tqp = rte_zmalloc_socket(__func__, alloc_size, RTE_CACHE_LINE_SIZE,\n+\t\t\t\tsocket_id);\n+\tif (qp == NULL) {\n+\t\tDRV_LOG(ERR, \"Failed to allocate qp memory.\");\n+\t\trte_errno = ENOMEM;\n+\t\treturn -rte_errno;\n+\t}\n+\tqp->priv = priv;\n+\tqp->entries_n = entries;\n+\tif (mlx5_mr_ctrl_init(&qp->mr_ctrl, &priv->cdev->mr_scache.dev_gen,\n+\t\t\t\t priv->dev_config.socket_id)) {\n+\t\tDRV_LOG(ERR, \"Cannot allocate MR Btree for qp %u.\",\n+\t\t\t(uint32_t)qp_id);\n+\t\trte_errno = ENOMEM;\n+\t\tgoto err;\n+\t}\n+\topaq_buf = rte_calloc(__func__, (size_t)entries,\n+\t\t\t sizeof(union mlx5_gga_crypto_opaque),\n+\t\t\t sizeof(union mlx5_gga_crypto_opaque));\n+\tif (opaq_buf == NULL) {\n+\t\tDRV_LOG(ERR, \"Failed to allocate opaque memory.\");\n+\t\trte_errno = ENOMEM;\n+\t\tgoto err;\n+\t}\n+\tif (mlx5_common_verbs_reg_mr(priv->cdev->pd, opaq_buf, entries *\n+\t\t\t\t sizeof(union mlx5_gga_crypto_opaque),\n+\t\t\t\t &qp->opaque_mr) != 0) {\n+\t\trte_free(opaq_buf);\n+\t\tDRV_LOG(ERR, \"Failed to register opaque MR.\");\n+\t\trte_errno = ENOMEM;\n+\t\tgoto err;\n+\t}\n+\tret = mlx5_devx_cq_create(priv->cdev->ctx, &qp->cq_obj, log_ops_n,\n+\t\t\t\t &cq_attr, socket_id);\n+\tif (ret != 0) {\n+\t\tDRV_LOG(ERR, \"Failed to create CQ.\");\n+\t\tgoto err;\n+\t}\n+\tqp_attr.cqn = qp->cq_obj.cq->id;\n+\tqp_attr.ts_format = mlx5_ts_format_conv(attr->qp_ts_format);\n+\tqp_attr.num_of_receive_wqes = 0;\n+\tqp_attr.num_of_send_wqbbs = entries;\n+\tqp_attr.mmo = attr->crypto_mmo.crypto_mmo_qp;\n+\t/* Set MMO QP as follower as the input data may depend on UMR. */\n+\tqp_attr.cd_slave_send = 1;\n+\tret = mlx5_devx_qp_create(priv->cdev->ctx, &qp->qp_obj,\n+\t\t\t\t qp_attr.num_of_send_wqbbs * MLX5_WQE_SIZE,\n+\t\t\t\t &qp_attr, socket_id);\n+\tif (ret != 0) {\n+\t\tDRV_LOG(ERR, \"Failed to create QP.\");\n+\t\tgoto err;\n+\t}\n+\tmlx5_crypto_gcm_init_qp(qp);\n+\tret = mlx5_devx_qp2rts(&qp->qp_obj, 0);\n+\tif (ret)\n+\t\tgoto err;\n+\tqp->ops = (struct rte_crypto_op **)(qp + 1);\n+\tqp->mkey = (struct mlx5_devx_obj **)(qp->ops + entries);\n+\tif (mlx5_crypto_gcm_umr_qp_setup(dev, qp, log_ops_n, socket_id)) {\n+\t\tDRV_LOG(ERR, \"Failed to setup UMR QP.\");\n+\t\tgoto err;\n+\t}\n+\tDRV_LOG(INFO, \"QP %u: SQN=0x%X CQN=0x%X entries num = %u\",\n+\t\t(uint32_t)qp_id, qp->qp_obj.qp->id, qp->cq_obj.cq->id, entries);\n+\tif (mlx5_crypto_gcm_indirect_mkeys_prepare(priv, qp)) {\n+\t\tDRV_LOG(ERR, \"Cannot allocate indirect memory regions.\");\n+\t\trte_errno = ENOMEM;\n+\t\tgoto err;\n+\t}\n+\tdev->data->queue_pairs[qp_id] = qp;\n+\treturn 0;\n+err:\n+\tmlx5_crypto_gcm_qp_release(dev, qp_id);\n+\treturn -1;\n+}\n+\n int\n mlx5_crypto_gcm_init(struct mlx5_crypto_priv *priv)\n {\n@@ -133,6 +384,8 @@ mlx5_crypto_gcm_init(struct mlx5_crypto_priv *priv)\n \n \t/* Override AES-GCM specified ops. */\n \tdev_ops->sym_session_configure = mlx5_crypto_sym_gcm_session_configure;\n+\tdev_ops->queue_pair_setup = mlx5_crypto_gcm_qp_setup;\n+\tdev_ops->queue_pair_release = mlx5_crypto_gcm_qp_release;\n \t/* Generate GCM capability. */\n \tret = mlx5_crypto_generate_gcm_cap(&cdev->config.hca_attr.crypto_mmo,\n \t\t\t\t\t mlx5_crypto_gcm_caps);\n@@ -140,6 +393,7 @@ mlx5_crypto_gcm_init(struct mlx5_crypto_priv *priv)\n \t\tDRV_LOG(ERR, \"No enough AES-GCM cap.\");\n \t\treturn -1;\n \t}\n+\tpriv->max_segs_num = rte_align32pow2((priv->max_segs_num + 2) * 2);\n \tpriv->caps = mlx5_crypto_gcm_caps;\n \tpriv->is_gcm_dek_wrap = !!(cdev->config.hca_attr.sw_wrapped_dek &\n \t\t\t\t(1 << MLX5_CRYPTO_KEY_PURPOSE_GCM));\n", "prefixes": [ "RFC", "4/5" ] }