Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/126230/?format=api
{ "id": 126230, "url": "http://patches.dpdk.org/api/patches/126230/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20230418092325.2578712-4-suanmingm@nvidia.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20230418092325.2578712-4-suanmingm@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20230418092325.2578712-4-suanmingm@nvidia.com", "date": "2023-04-18T09:23:23", "name": "[RFC,3/5] crypto/mlx5: add AES-GCM session configure", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "87bab625fb366e252aaf77d82c69b277b6b99e5c", "submitter": { "id": 1887, "url": "http://patches.dpdk.org/api/people/1887/?format=api", "name": "Suanming Mou", "email": "suanmingm@nvidia.com" }, "delegate": { "id": 6690, "url": "http://patches.dpdk.org/api/users/6690/?format=api", "username": "akhil", "first_name": "akhil", "last_name": "goyal", "email": "gakhil@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20230418092325.2578712-4-suanmingm@nvidia.com/mbox/", "series": [ { "id": 27756, "url": "http://patches.dpdk.org/api/series/27756/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=27756", "date": "2023-04-18T09:23:20", "name": "crypto/mlx5: support AES-GCM", "version": 1, "mbox": "http://patches.dpdk.org/series/27756/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/126230/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/126230/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 5EDE24297B;\n\tTue, 18 Apr 2023 11:24:21 +0200 (CEST)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id CEFD842D13;\n\tTue, 18 Apr 2023 11:24:05 +0200 (CEST)", "from NAM10-MW2-obe.outbound.protection.outlook.com\n (mail-mw2nam10on2080.outbound.protection.outlook.com [40.107.94.80])\n by mails.dpdk.org (Postfix) with ESMTP id 94EB642D0E\n for <dev@dpdk.org>; Tue, 18 Apr 2023 11:24:03 +0200 (CEST)", "from MW4PR04CA0256.namprd04.prod.outlook.com (2603:10b6:303:88::21)\n by DM4PR12MB5867.namprd12.prod.outlook.com (2603:10b6:8:66::18) with\n Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6298.45; Tue, 18 Apr\n 2023 09:24:01 +0000", "from CO1NAM11FT104.eop-nam11.prod.protection.outlook.com\n (2603:10b6:303:88:cafe::d7) by MW4PR04CA0256.outlook.office365.com\n (2603:10b6:303:88::21) with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6298.47 via Frontend\n Transport; Tue, 18 Apr 2023 09:24:01 +0000", "from mail.nvidia.com (216.228.117.160) by\n CO1NAM11FT104.mail.protection.outlook.com (10.13.174.220) with Microsoft SMTP\n Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id\n 15.20.6319.20 via Frontend Transport; Tue, 18 Apr 2023 09:24:01 +0000", "from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com\n (10.129.200.66) with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.5; Tue, 18 Apr 2023\n 02:23:52 -0700", "from nvidia.com (10.126.230.37) by rnnvmail201.nvidia.com\n (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.37; Tue, 18 Apr\n 2023 02:23:50 -0700" ], "ARC-Seal": "i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none;\n b=nZ274HeIQGXI2e56ZRcyUsqzwsChKt3vmLcM2ktocDmku1Ka0BWagmTMXPxBL62mskH6TI40P1kzG/yXQ0s3L9mcJiYynZeGs7e/nZVBYwOxxyael65MYHRiFYRKm+X0GQLu/1q9wYra9lgxN/marzOFZsQcX3bs7GriX4XfNLunzGm3ISDCiagHP0x0nDUEScyfyA5RycL4t8IId60DOdEvcinuyh4Kr0AS7og0QGmu5gNmhOmdfB56Mos7R/q0z1sKinpuPLo5OMg2QyzSL/mp11wsYM5R4g/yik/N7NXqY0Jw1QmutQUD/ET0zGUT/6ObpeueWPbZfKSrxzCxIQ==", "ARC-Message-Signature": "i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com;\n s=arcselector9901;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1;\n bh=ri9x2S+IfjlRJppSDgvTi76s2MAEVKhz8d9ssiKmVCM=;\n b=UTEQFegXefb8fnktbEQBMP/RH/Lt8f4auyhDUGDrDiRjup/lPjTtaK4gemho+7tgGOLUBQGh6pf2KN+L/tggtU4vHS1GUOoq7KCOGtjS/Y7QDq7GUEPXPd+OV4uJzdGaCjdGFMHtMEYnNavUI7keTMLilP1dHlNeY8SE1sPRuqooAOW2vzSd/g5VaR+NVPreXTRoAhwv58X5tlxm0Z74oJ04NnH8ffhrW0eM8X+XtV7q8hPeV+bYegNKH2pE6cpVgBaC8+xqeXZ0KMwmZQdd5/8ckTI4M+QYKj0fSyremYnVldC4wiJIpA8i/nXmoRwnzIVLxUYV3hKbUENh5QNYig==", "ARC-Authentication-Results": "i=1; mx.microsoft.com 1; spf=pass (sender ip is\n 216.228.117.160) smtp.rcpttodomain=dpdk.org smtp.mailfrom=nvidia.com;\n dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com;\n dkim=none (message not signed); arc=none", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com;\n s=selector2;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n bh=ri9x2S+IfjlRJppSDgvTi76s2MAEVKhz8d9ssiKmVCM=;\n b=J4sehTatYim+Elg+QXufz0tC4Ei3XBm/KwOX6kI0FSuzp9FS9YZjhEHvDIFlRbRgmoc1UvMRW62vWXwhe8ADom8T6WYiXZOw/lyPuVVzevhoeWNbYjbNLA8mgnlRpAcKEJz9LngO01hy7t1yNVxjqwuEIln5T7e8PzFlQRjsD9RkQzg/hnEb2vIDITmmM1k/qdsSr5qm0yg1E17p2miqhp5S1yc4RTqGiRuhA1L/wJCMjJG8IzJkOkul428wGl6YoQrRcY5kpFCQkKv0cJMGmAitGvafPaN2pHhkWex3vnPcM6jtSgHOvtdgmWtptZiZhPWrK4vgrUrG9v+CCe1ilw==", "X-MS-Exchange-Authentication-Results": "spf=pass (sender IP is 216.228.117.160)\n smtp.mailfrom=nvidia.com;\n dkim=none (message not signed)\n header.d=none;dmarc=pass action=none header.from=nvidia.com;", "Received-SPF": "Pass (protection.outlook.com: domain of nvidia.com designates\n 216.228.117.160 as permitted sender) receiver=protection.outlook.com;\n client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C", "From": "Suanming Mou <suanmingm@nvidia.com>", "To": "<matan@nvidia.com>", "CC": "<rasland@nvidia.com>, <mkashani@nvidia.com>, <dev@dpdk.org>", "Subject": "[RFC PATCH 3/5] crypto/mlx5: add AES-GCM session configure", "Date": "Tue, 18 Apr 2023 12:23:23 +0300", "Message-ID": "<20230418092325.2578712-4-suanmingm@nvidia.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20230418092325.2578712-1-suanmingm@nvidia.com>", "References": "<20230418092325.2578712-1-suanmingm@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[10.126.230.37]", "X-ClientProxiedBy": "rnnvmail203.nvidia.com (10.129.68.9) To\n rnnvmail201.nvidia.com (10.129.68.8)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "CO1NAM11FT104:EE_|DM4PR12MB5867:EE_", "X-MS-Office365-Filtering-Correlation-Id": "0d68cf0e-8689-4eda-061d-08db3feea566", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n Ln7hI/CySQtyVqYbTrR1v9IElbWI/64Tr+6YtxpCISc5fNEsbPliakDGcL4wriimSieeNjsjGjHCd0ChxXiZL2QFFoBZBikS4vKrKU2tBIPhDyx8amKdy6B78RAC6uN09SPRZ0vTxHbyAAvPExtkU5TNft62UPamataid/I9eo5wmD8BWILgtrTnh54ELZDb3q3DS/+J4W2VmWDrsO53lYPootNI1RRe832a+A5UkMm5vtIV8BReqUzqwkIEAhF0g8bKQY2VH+mtDS4YkFPOAT22lYRx+9DTxjKnq1YXaJIKK+41BnNSRrsqj+QhHeGp/Fbip164iIELXuYysPL/vHJxsrtI/YJfK2PH+U3vj4YY4sXYq8FR8X0/tf0zqQhvrY9ZT6ifuUkhJ/1zpjlHac2smas1wY36RLK+98h+ELmQlJtGu2eYc+oAthWEI/5QLOutGOpssHSGD6rctZvLxUJsMGikEMuPE/m+RUkHJlsGef2JmbN/J5wzQOw488euNNcKyDyrN0gBPR41JWhcnX8mgEOFC9SN9RWEqDV0v02uNgKHsE8K4jp7I0xX38lVkMCU+bellJ79zXTp6le+TMRwbUEM/ZdPVIDJktr0MtPSFgIFXPkzfwkb9zKgc4M5jbF7Oyz4Aw3qeOjxAbq69pOiY8RJHrNj2DkPXOeEL58swUhiY/emLVBBTVmXL37h78Ww29wMfNdNrcCh2o4EmhEo3LmBd5+CfvPtb5s3ksVd4fdPac4oKSAimxwthZOshfEjc6GWtpeH7E3cpAe5tl1j4Cx8Zyx3QX26r7zWolo=", "X-Forefront-Antispam-Report": "CIP:216.228.117.160; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE;\n SFS:(13230028)(4636009)(136003)(39860400002)(396003)(346002)(376002)(451199021)(46966006)(40470700004)(36840700001)(40480700001)(55016003)(82310400005)(4326008)(2616005)(40460700003)(16526019)(6286002)(186003)(41300700001)(36860700001)(426003)(336012)(47076005)(83380400001)(7696005)(6666004)(6636002)(37006003)(316002)(54906003)(478600001)(1076003)(26005)(70206006)(70586007)(7636003)(356005)(82740400003)(86362001)(36756003)(6862004)(8676002)(8936002)(34020700004)(2906002)(5660300002);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "18 Apr 2023 09:24:01.1812 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 0d68cf0e-8689-4eda-061d-08db3feea566", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n CO1NAM11FT104.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "DM4PR12MB5867", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Sessions are used in symmetric transformations in order to prepare\nobjects and data for packet processing stage.\n\nThe AES-GCM session includes IV, AAD, digest(tag), DEK, operation\nmode information.\n\nSigned-off-by: Suanming Mou <suanmingm@nvidia.com>\n---\n drivers/common/mlx5/mlx5_prm.h | 12 +++++++\n drivers/crypto/mlx5/mlx5_crypto.c | 15 ---------\n drivers/crypto/mlx5/mlx5_crypto.h | 35 ++++++++++++++++++++\n drivers/crypto/mlx5/mlx5_crypto_gcm.c | 46 +++++++++++++++++++++++++++\n 4 files changed, 93 insertions(+), 15 deletions(-)", "diff": "diff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h\nindex 9728be24dd..25ff66ee7e 100644\n--- a/drivers/common/mlx5/mlx5_prm.h\n+++ b/drivers/common/mlx5/mlx5_prm.h\n@@ -528,11 +528,23 @@ enum {\n \tMLX5_BLOCK_SIZE_4048B\t= 0x6,\n };\n \n+enum {\n+\tMLX5_ENCRYPTION_TYPE_AES_GCM = 0x3,\n+};\n+\n+enum {\n+\tMLX5_CRYPTO_OP_TYPE_ENCRYPTION = 0x0,\n+\tMLX5_CRYPTO_OP_TYPE_DECRYPTION = 0x1,\n+};\n+\n #define MLX5_BSF_SIZE_OFFSET\t\t30\n #define MLX5_BSF_P_TYPE_OFFSET\t\t24\n #define MLX5_ENCRYPTION_ORDER_OFFSET\t16\n #define MLX5_BLOCK_SIZE_OFFSET\t\t24\n \n+#define MLX5_CRYPTO_MMO_TYPE_OFFSET 24\n+#define MLX5_CRYPTO_MMO_OP_OFFSET 20\n+\n struct mlx5_wqe_umr_bsf_seg {\n \t/*\n \t * bs_bpt_eo_es contains:\ndiff --git a/drivers/crypto/mlx5/mlx5_crypto.c b/drivers/crypto/mlx5/mlx5_crypto.c\nindex 66c9f94346..8946f13e5e 100644\n--- a/drivers/crypto/mlx5/mlx5_crypto.c\n+++ b/drivers/crypto/mlx5/mlx5_crypto.c\n@@ -83,21 +83,6 @@ static const struct rte_driver mlx5_drv = {\n \n static struct cryptodev_driver mlx5_cryptodev_driver;\n \n-struct mlx5_crypto_session {\n-\tuint32_t bs_bpt_eo_es;\n-\t/**< bsf_size, bsf_p_type, encryption_order and encryption standard,\n-\t * saved in big endian format.\n-\t */\n-\tuint32_t bsp_res;\n-\t/**< crypto_block_size_pointer and reserved 24 bits saved in big\n-\t * endian format.\n-\t */\n-\tuint32_t iv_offset:16;\n-\t/**< Starting point for Initialisation Vector. */\n-\tstruct mlx5_crypto_dek *dek; /**< Pointer to dek struct. */\n-\tuint32_t dek_id; /**< DEK ID */\n-} __rte_packed;\n-\n static void\n mlx5_crypto_dev_infos_get(struct rte_cryptodev *dev,\n \t\t\t struct rte_cryptodev_info *dev_info)\ndiff --git a/drivers/crypto/mlx5/mlx5_crypto.h b/drivers/crypto/mlx5/mlx5_crypto.h\nindex 11352f9409..c34a860404 100644\n--- a/drivers/crypto/mlx5/mlx5_crypto.h\n+++ b/drivers/crypto/mlx5/mlx5_crypto.h\n@@ -73,6 +73,41 @@ struct mlx5_crypto_devarg_params {\n \tuint32_t is_aes_gcm:1;\n };\n \n+struct mlx5_crypto_session {\n+\tunion {\n+\t\t/**< AES-XTS configuration. */\n+\t\tstruct {\n+\t\t\tuint32_t bs_bpt_eo_es;\n+\t\t\t/**< bsf_size, bsf_p_type, encryption_order and encryption standard,\n+\t\t\t * saved in big endian format.\n+\t\t\t */\n+\t\t\tuint32_t bsp_res;\n+\t\t\t/**< crypto_block_size_pointer and reserved 24 bits saved in big\n+\t\t\t * endian format.\n+\t\t\t */\n+\t\t};\n+\t\t/**< AES-GCM configuration. */\n+\t\tstruct {\n+\t\t\tuint32_t mmo_ctrl;\n+\t\t\t/**< Crypto control fields with algo type and op type in big\n+\t\t\t * endian format.\n+\t\t\t */\n+\t\t\tuint16_t tag_len;\n+\t\t\t/**< AES-GCM crypto digest size in bytes. */\n+\t\t\tuint16_t aad_len;\n+\t\t\t/**< The length of the additional authenticated data (AAD) in bytes. */\n+\t\t\tuint32_t op_type;\n+\t\t\t/**< Operation type. */\n+\t\t};\n+\t};\n+\tuint32_t iv_offset:16;\n+\t/**< Starting point for Initialisation Vector. */\n+\tuint32_t iv_len;\n+\t/**< Initialisation Vector length. */\n+\tstruct mlx5_crypto_dek *dek; /**< Pointer to dek struct. */\n+\tuint32_t dek_id; /**< DEK ID */\n+} __rte_packed;\n+\n int\n mlx5_crypto_dek_destroy(struct mlx5_crypto_priv *priv,\n \t\t\tstruct mlx5_crypto_dek *dek);\ndiff --git a/drivers/crypto/mlx5/mlx5_crypto_gcm.c b/drivers/crypto/mlx5/mlx5_crypto_gcm.c\nindex c7fd86d7b9..6c2c759fba 100644\n--- a/drivers/crypto/mlx5/mlx5_crypto_gcm.c\n+++ b/drivers/crypto/mlx5/mlx5_crypto_gcm.c\n@@ -81,12 +81,58 @@ mlx5_crypto_generate_gcm_cap(struct mlx5_hca_crypto_mmo_attr *mmo_attr,\n \treturn 0;\n }\n \n+static int\n+mlx5_crypto_sym_gcm_session_configure(struct rte_cryptodev *dev,\n+\t\t\t\t struct rte_crypto_sym_xform *xform,\n+\t\t\t\t struct rte_cryptodev_sym_session *session)\n+{\n+\tstruct mlx5_crypto_priv *priv = dev->data->dev_private;\n+\tstruct mlx5_crypto_session *sess_private_data = CRYPTODEV_GET_SYM_SESS_PRIV(session);\n+\tstruct rte_crypto_aead_xform *aead = &xform->aead;\n+\tuint32_t op_type;\n+\n+\tif (unlikely(xform->next != NULL)) {\n+\t\tDRV_LOG(ERR, \"Xform next is not supported.\");\n+\t\treturn -ENOTSUP;\n+\t}\n+\tif (aead->algo != RTE_CRYPTO_AEAD_AES_GCM) {\n+\t\tDRV_LOG(ERR, \"Only AES-GCM algorithm is supported.\");\n+\t\treturn -ENOTSUP;\n+\t}\n+\tif (aead->op == RTE_CRYPTO_AEAD_OP_ENCRYPT)\n+\t\top_type = MLX5_CRYPTO_OP_TYPE_ENCRYPTION;\n+\telse\n+\t\top_type = MLX5_CRYPTO_OP_TYPE_DECRYPTION;\n+\tsess_private_data->op_type = op_type;\n+\tsess_private_data->mmo_ctrl = rte_cpu_to_be_32\n+\t\t\t(op_type << MLX5_CRYPTO_MMO_OP_OFFSET |\n+\t\t\t MLX5_ENCRYPTION_TYPE_AES_GCM << MLX5_CRYPTO_MMO_TYPE_OFFSET);\n+\tsess_private_data->aad_len = aead->aad_length;\n+\tsess_private_data->tag_len = aead->digest_length;\n+\tsess_private_data->iv_offset = aead->iv.offset;\n+\tsess_private_data->iv_len = aead->iv.length;\n+\tsess_private_data->dek = mlx5_crypto_dek_prepare(priv, xform);\n+\tif (sess_private_data->dek == NULL) {\n+\t\tDRV_LOG(ERR, \"Failed to prepare dek.\");\n+\t\treturn -ENOMEM;\n+\t}\n+\tsess_private_data->dek_id =\n+\t\t\trte_cpu_to_be_32(sess_private_data->dek->obj->id &\n+\t\t\t\t\t 0xffffff);\n+\tDRV_LOG(DEBUG, \"Session %p was configured.\", sess_private_data);\n+\treturn 0;\n+}\n+\n int\n mlx5_crypto_gcm_init(struct mlx5_crypto_priv *priv)\n {\n \tstruct mlx5_common_device *cdev = priv->cdev;\n+\tstruct rte_cryptodev *crypto_dev = priv->crypto_dev;\n+\tstruct rte_cryptodev_ops *dev_ops = crypto_dev->dev_ops;\n \tint ret;\n \n+\t/* Override AES-GCM specified ops. */\n+\tdev_ops->sym_session_configure = mlx5_crypto_sym_gcm_session_configure;\n \t/* Generate GCM capability. */\n \tret = mlx5_crypto_generate_gcm_cap(&cdev->config.hca_attr.crypto_mmo,\n \t\t\t\t\t mlx5_crypto_gcm_caps);\n", "prefixes": [ "RFC", "3/5" ] }