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GET /api/patches/126228/?format=api
{ "id": 126228, "url": "http://patches.dpdk.org/api/patches/126228/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20230418092325.2578712-3-suanmingm@nvidia.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20230418092325.2578712-3-suanmingm@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20230418092325.2578712-3-suanmingm@nvidia.com", "date": "2023-04-18T09:23:22", "name": "[RFC,2/5] crypto/mlx5: add AES-GCM encryption key", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "5f998233c9cb8bd38f702e295912b770bcae240b", "submitter": { "id": 1887, "url": "http://patches.dpdk.org/api/people/1887/?format=api", "name": "Suanming Mou", "email": "suanmingm@nvidia.com" }, "delegate": { "id": 6690, "url": "http://patches.dpdk.org/api/users/6690/?format=api", "username": "akhil", "first_name": "akhil", "last_name": "goyal", "email": "gakhil@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20230418092325.2578712-3-suanmingm@nvidia.com/mbox/", "series": [ { "id": 27756, "url": "http://patches.dpdk.org/api/series/27756/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=27756", "date": "2023-04-18T09:23:20", "name": "crypto/mlx5: support AES-GCM", "version": 1, "mbox": "http://patches.dpdk.org/series/27756/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/126228/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/126228/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": 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2023 12:23:22 +0300", "Message-ID": "<20230418092325.2578712-3-suanmingm@nvidia.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20230418092325.2578712-1-suanmingm@nvidia.com>", "References": "<20230418092325.2578712-1-suanmingm@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[10.126.230.37]", "X-ClientProxiedBy": "rnnvmail203.nvidia.com (10.129.68.9) To\n rnnvmail201.nvidia.com (10.129.68.8)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "CO1NAM11FT092:EE_|SJ1PR12MB6051:EE_", "X-MS-Office365-Filtering-Correlation-Id": "a6cdef5a-ea0a-49ed-4114-08db3feea419", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n GgTppgbcPZmWhYKIpjF5RCs3OUhTaoEHGL3LmpaTJK3MP3cp3JWdMehBJgSi08MoNb1k0r9w3LTsAHVaz0GKyhYg3puU3ftGXurJghttIVcD+SQM72+xEM4f9U27FmrUIpx4exNwbKSE2YrJVMbDzkbWxPkJQBRBRYyz376WwvMw9Y1Aap0aV8FfzeUy5l2OXEOZtihwv8/KaDkRHcwx1rUR8adVQ7zVZ3ufTT9mlmtsh8fi2ZT5BTn1/3+hm5p/imywzbQKCZYAzg9PuOlp5BpZo9KzufUFMCy1rP4S483T+GgRplp+tPvTf2G//2smsruDCMqp8EcsfDiyJSW8FAOzg+OYF4mqwlyWzzDKil4AtBCt47GUaUnxuTBsC2PYdEalGIHFkBk2ip2bgtQ4C1w/joVVK/KvRfzDioOA1RzYWpdSlxvd64QmeTlly4nx3OkDQfuD1fOpK7GpRMVbdosnBICCbphLOuH8ndXUHu4DtvqFFt2HJ6BOLYt7aCxb0oRDHs+FtgEsRBw/G9hrIMZIE76NG5c//ksDSnYe86W7VRP36RM8vqiFq0IhYOqJNqZ0VM9vdKVCbch4XtBax+2ygY2OBV31NL9fo1XcRB4k5ozrJSla2Sp4oT2dvtydVf1dH+mkM/o43M2/p0Mz1sjqkoevvrfr/cTIMUu8cPThiJ58TD70BE+5ng8D89jKAu8lhAcAUanTSAaJZgFB/bVVXqCdvG3mg7AzqHjCovpWUpHO3i85MRf2aBhK05IADjcBcW1S6Xy3fYAqsbhExcnPXnEtEYyc07K1w+NRjTM=", "X-Forefront-Antispam-Report": "CIP:216.228.117.160; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE;\n SFS:(13230028)(4636009)(396003)(39860400002)(376002)(346002)(136003)(451199021)(36840700001)(46966006)(40470700004)(36756003)(37006003)(54906003)(6636002)(4326008)(316002)(70586007)(70206006)(478600001)(7696005)(6666004)(40480700001)(55016003)(82310400005)(8936002)(8676002)(6862004)(5660300002)(41300700001)(30864003)(2906002)(82740400003)(34020700004)(356005)(86362001)(7636003)(426003)(336012)(2616005)(16526019)(1076003)(26005)(6286002)(186003)(40460700003)(36860700001)(47076005)(83380400001);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "18 Apr 2023 09:23:59.0004 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n a6cdef5a-ea0a-49ed-4114-08db3feea419", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n CO1NAM11FT092.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "SJ1PR12MB6051", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "The crypto device requires the DEK(data encryption key) object for\ndata encryption/decryption operation.\n\nThis commit adds the AES-GCM DEK object management support.\n\nSigned-off-by: Suanming Mou <suanmingm@nvidia.com>\n---\n drivers/common/mlx5/mlx5_devx_cmds.c | 6 +-\n drivers/common/mlx5/mlx5_devx_cmds.h | 1 +\n drivers/common/mlx5/mlx5_prm.h | 6 +-\n drivers/crypto/mlx5/mlx5_crypto.c | 2 +-\n drivers/crypto/mlx5/mlx5_crypto.h | 3 +-\n drivers/crypto/mlx5/mlx5_crypto_dek.c | 157 ++++++++++++++++++++------\n drivers/crypto/mlx5/mlx5_crypto_gcm.c | 2 +\n 7 files changed, 137 insertions(+), 40 deletions(-)", "diff": "diff --git a/drivers/common/mlx5/mlx5_devx_cmds.c b/drivers/common/mlx5/mlx5_devx_cmds.c\nindex 592a7cffdb..8b51a75cc8 100644\n--- a/drivers/common/mlx5/mlx5_devx_cmds.c\n+++ b/drivers/common/mlx5/mlx5_devx_cmds.c\n@@ -3166,10 +3166,14 @@ mlx5_devx_cmd_create_dek_obj(void *ctx, struct mlx5_devx_dek_attr *attr)\n \tptr = MLX5_ADDR_OF(create_dek_in, in, dek);\n \tMLX5_SET(dek, ptr, key_size, attr->key_size);\n \tMLX5_SET(dek, ptr, has_keytag, attr->has_keytag);\n+\tMLX5_SET(dek, ptr, sw_wrapped, attr->sw_wrapped);\n \tMLX5_SET(dek, ptr, key_purpose, attr->key_purpose);\n \tMLX5_SET(dek, ptr, pd, attr->pd);\n \tMLX5_SET64(dek, ptr, opaque, attr->opaque);\n-\tkey_addr = MLX5_ADDR_OF(dek, ptr, key);\n+\tif (attr->sw_wrapped)\n+\t\tkey_addr = MLX5_ADDR_OF(dek, ptr, sw_wrapped_dek);\n+\telse\n+\t\tkey_addr = MLX5_ADDR_OF(dek, ptr, key);\n \tmemcpy(key_addr, (void *)(attr->key), MLX5_CRYPTO_KEY_MAX_SIZE);\n \tdek_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),\n \t\t\t\t\t\t out, sizeof(out));\ndiff --git a/drivers/common/mlx5/mlx5_devx_cmds.h b/drivers/common/mlx5/mlx5_devx_cmds.h\nindex d640482346..79502cda08 100644\n--- a/drivers/common/mlx5/mlx5_devx_cmds.h\n+++ b/drivers/common/mlx5/mlx5_devx_cmds.h\n@@ -664,6 +664,7 @@ struct mlx5_devx_dek_attr {\n \tuint32_t key_size:4;\n \tuint32_t has_keytag:1;\n \tuint32_t key_purpose:4;\n+\tuint32_t sw_wrapped:1;\n \tuint32_t pd:24;\n \tuint64_t opaque;\n \tuint8_t key[MLX5_CRYPTO_KEY_MAX_SIZE];\ndiff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h\nindex a3b85f514e..9728be24dd 100644\n--- a/drivers/common/mlx5/mlx5_prm.h\n+++ b/drivers/common/mlx5/mlx5_prm.h\n@@ -3736,7 +3736,8 @@ enum {\n struct mlx5_ifc_dek_bits {\n \tu8 modify_field_select[0x40];\n \tu8 state[0x8];\n-\tu8 reserved_at_48[0xc];\n+\tu8 sw_wrapped[0x1];\n+\tu8 reserved_at_49[0xb];\n \tu8 key_size[0x4];\n \tu8 has_keytag[0x1];\n \tu8 reserved_at_59[0x3];\n@@ -3747,7 +3748,8 @@ struct mlx5_ifc_dek_bits {\n \tu8 opaque[0x40];\n \tu8 reserved_at_1c0[0x40];\n \tu8 key[0x400];\n-\tu8 reserved_at_600[0x200];\n+\tu8 sw_wrapped_dek[0x400];\n+\tu8 reserved_at_a00[0x300];\n };\n \n struct mlx5_ifc_create_dek_in_bits {\ndiff --git a/drivers/crypto/mlx5/mlx5_crypto.c b/drivers/crypto/mlx5/mlx5_crypto.c\nindex 6963d8a9c9..66c9f94346 100644\n--- a/drivers/crypto/mlx5/mlx5_crypto.c\n+++ b/drivers/crypto/mlx5/mlx5_crypto.c\n@@ -196,7 +196,7 @@ mlx5_crypto_sym_session_configure(struct rte_cryptodev *dev,\n \t\treturn -ENOTSUP;\n \t}\n \tcipher = &xform->cipher;\n-\tsess_private_data->dek = mlx5_crypto_dek_prepare(priv, cipher);\n+\tsess_private_data->dek = mlx5_crypto_dek_prepare(priv, xform);\n \tif (sess_private_data->dek == NULL) {\n \t\tDRV_LOG(ERR, \"Failed to prepare dek.\");\n \t\treturn -ENOMEM;\ndiff --git a/drivers/crypto/mlx5/mlx5_crypto.h b/drivers/crypto/mlx5/mlx5_crypto.h\nindex 80c2cab0dd..11352f9409 100644\n--- a/drivers/crypto/mlx5/mlx5_crypto.h\n+++ b/drivers/crypto/mlx5/mlx5_crypto.h\n@@ -40,6 +40,7 @@ struct mlx5_crypto_priv {\n \tuint16_t umr_wqe_stride;\n \tuint16_t max_rdmar_ds;\n \tuint32_t is_wrapped_mode:1;\n+\tuint32_t is_gcm_dek_wrap:1;\n };\n \n struct mlx5_crypto_qp {\n@@ -78,7 +79,7 @@ mlx5_crypto_dek_destroy(struct mlx5_crypto_priv *priv,\n \n struct mlx5_crypto_dek *\n mlx5_crypto_dek_prepare(struct mlx5_crypto_priv *priv,\n-\t\t\tstruct rte_crypto_cipher_xform *cipher);\n+\t\t\tstruct rte_crypto_sym_xform *xform);\n \n int\n mlx5_crypto_dek_setup(struct mlx5_crypto_priv *priv);\ndiff --git a/drivers/crypto/mlx5/mlx5_crypto_dek.c b/drivers/crypto/mlx5/mlx5_crypto_dek.c\nindex 7339ef2bd9..ba6dab52f7 100644\n--- a/drivers/crypto/mlx5/mlx5_crypto_dek.c\n+++ b/drivers/crypto/mlx5/mlx5_crypto_dek.c\n@@ -14,10 +14,29 @@\n #include \"mlx5_crypto.h\"\n \n struct mlx5_crypto_dek_ctx {\n-\tstruct rte_crypto_cipher_xform *cipher;\n+\tstruct rte_crypto_sym_xform *xform;\n \tstruct mlx5_crypto_priv *priv;\n };\n \n+static int\n+mlx5_crypto_dek_get_key(struct rte_crypto_sym_xform *xform,\n+\t\t\tconst uint8_t **key,\n+\t\t\tuint16_t *key_len)\n+{\n+\tif (xform->type == RTE_CRYPTO_SYM_XFORM_CIPHER) {\n+\t\t*key = xform->cipher.key.data;\n+\t\t*key_len = xform->cipher.key.length;\n+\t} else if (xform->type == RTE_CRYPTO_SYM_XFORM_AEAD) {\n+\t\t*key = xform->aead.key.data;\n+\t\t*key_len = xform->aead.key.length;\n+\t} else {\n+\t\tDRV_LOG(ERR, \"Xform dek type not supported.\");\n+\t\trte_errno = -EINVAL;\n+\t\treturn -1;\n+\t}\n+\treturn 0;\n+}\n+\n int\n mlx5_crypto_dek_destroy(struct mlx5_crypto_priv *priv,\n \t\t\tstruct mlx5_crypto_dek *dek)\n@@ -27,19 +46,22 @@ mlx5_crypto_dek_destroy(struct mlx5_crypto_priv *priv,\n \n struct mlx5_crypto_dek *\n mlx5_crypto_dek_prepare(struct mlx5_crypto_priv *priv,\n-\t\t\tstruct rte_crypto_cipher_xform *cipher)\n+\t\t\tstruct rte_crypto_sym_xform *xform)\n {\n+\tconst uint8_t *key;\n+\tuint16_t key_len;\n \tstruct mlx5_hlist *dek_hlist = priv->dek_hlist;\n \tstruct mlx5_crypto_dek_ctx dek_ctx = {\n-\t\t.cipher = cipher,\n+\t\t.xform = xform,\n \t\t.priv = priv,\n \t};\n-\tstruct rte_crypto_cipher_xform *cipher_ctx = cipher;\n-\tuint64_t key64 = __rte_raw_cksum(cipher_ctx->key.data,\n-\t\t\t\t\t cipher_ctx->key.length, 0);\n-\tstruct mlx5_list_entry *entry = mlx5_hlist_register(dek_hlist,\n-\t\t\t\t\t\t\t key64, &dek_ctx);\n+\tuint64_t key64;\n+\tstruct mlx5_list_entry *entry;\n \n+\tif (mlx5_crypto_dek_get_key(xform, &key, &key_len))\n+\t\treturn NULL;\n+\tkey64 = __rte_raw_cksum(key, key_len, 0);\n+\tentry = mlx5_hlist_register(dek_hlist, key64, &dek_ctx);\n \treturn entry == NULL ? NULL :\n \t\t\t container_of(entry, struct mlx5_crypto_dek, entry);\n }\n@@ -76,76 +98,141 @@ mlx5_crypto_dek_match_cb(void *tool_ctx __rte_unused,\n \t\t\t struct mlx5_list_entry *entry, void *cb_ctx)\n {\n \tstruct mlx5_crypto_dek_ctx *ctx = cb_ctx;\n-\tstruct rte_crypto_cipher_xform *cipher_ctx = ctx->cipher;\n+\tstruct rte_crypto_sym_xform *xform = ctx->xform;\n \tstruct mlx5_crypto_dek *dek =\n \t\t\tcontainer_of(entry, typeof(*dek), entry);\n \tuint32_t key_len = dek->size;\n+\tuint16_t xkey_len;\n+\tconst uint8_t *key;\n \n-\tif (key_len != cipher_ctx->key.length)\n+\tif (mlx5_crypto_dek_get_key(xform, &key, &xkey_len))\n+\t\treturn -1;\n+\tif (key_len != xkey_len)\n \t\treturn -1;\n-\treturn memcmp(cipher_ctx->key.data, dek->data, cipher_ctx->key.length);\n+\treturn memcmp(key, dek->data, xkey_len);\n }\n \n-static struct mlx5_list_entry *\n-mlx5_crypto_dek_create_cb(void *tool_ctx __rte_unused, void *cb_ctx)\n+static int\n+mlx5_crypto_dek_create_aes_xts(struct mlx5_crypto_dek *dek,\n+\t\tstruct mlx5_devx_dek_attr *dek_attr,\n+\t\tvoid *cb_ctx)\n {\n \tstruct mlx5_crypto_dek_ctx *ctx = cb_ctx;\n-\tstruct rte_crypto_cipher_xform *cipher_ctx = ctx->cipher;\n-\tstruct mlx5_crypto_dek *dek = rte_zmalloc(__func__, sizeof(*dek),\n-\t\t\t\t\t\t RTE_CACHE_LINE_SIZE);\n-\tstruct mlx5_devx_dek_attr dek_attr = {\n-\t\t.pd = ctx->priv->cdev->pdn,\n-\t\t.key_purpose = MLX5_CRYPTO_KEY_PURPOSE_AES_XTS,\n-\t\t.has_keytag = 1,\n-\t};\n+\tstruct rte_crypto_cipher_xform *cipher_ctx = &ctx->xform->cipher;\n \tbool is_wrapped = ctx->priv->is_wrapped_mode;\n \n-\tif (dek == NULL) {\n-\t\tDRV_LOG(ERR, \"Failed to allocate dek memory.\");\n-\t\treturn NULL;\n+\tif (cipher_ctx->algo != RTE_CRYPTO_CIPHER_AES_XTS) {\n+\t\tDRV_LOG(ERR, \"Only AES-XTS algo supported.\");\n+\t\treturn -EINVAL;\n \t}\n+\tdek_attr->key_purpose = MLX5_CRYPTO_KEY_PURPOSE_AES_XTS;\n+\tdek_attr->has_keytag = 1;\n \tif (is_wrapped) {\n \t\tswitch (cipher_ctx->key.length) {\n \t\tcase 48:\n \t\t\tdek->size = 48;\n-\t\t\tdek_attr.key_size = MLX5_CRYPTO_KEY_SIZE_128b;\n+\t\t\tdek_attr->key_size = MLX5_CRYPTO_KEY_SIZE_128b;\n \t\t\tbreak;\n \t\tcase 80:\n \t\t\tdek->size = 80;\n-\t\t\tdek_attr.key_size = MLX5_CRYPTO_KEY_SIZE_256b;\n+\t\t\tdek_attr->key_size = MLX5_CRYPTO_KEY_SIZE_256b;\n \t\t\tbreak;\n \t\tdefault:\n \t\t\tDRV_LOG(ERR, \"Wrapped key size not supported.\");\n-\t\t\treturn NULL;\n+\t\t\treturn -EINVAL;\n \t\t}\n \t} else {\n \t\tswitch (cipher_ctx->key.length) {\n \t\tcase 32:\n \t\t\tdek->size = 40;\n-\t\t\tdek_attr.key_size = MLX5_CRYPTO_KEY_SIZE_128b;\n+\t\t\tdek_attr->key_size = MLX5_CRYPTO_KEY_SIZE_128b;\n \t\t\tbreak;\n \t\tcase 64:\n \t\t\tdek->size = 72;\n-\t\t\tdek_attr.key_size = MLX5_CRYPTO_KEY_SIZE_256b;\n+\t\t\tdek_attr->key_size = MLX5_CRYPTO_KEY_SIZE_256b;\n \t\t\tbreak;\n \t\tdefault:\n \t\t\tDRV_LOG(ERR, \"Key size not supported.\");\n-\t\t\treturn NULL;\n+\t\t\treturn -EINVAL;\n \t\t}\n-\t\tmemcpy(&dek_attr.key[cipher_ctx->key.length],\n+\t\tmemcpy(&dek_attr->key[cipher_ctx->key.length],\n \t\t\t\t\t\t&ctx->priv->keytag, 8);\n \t}\n-\tmemcpy(&dek_attr.key, cipher_ctx->key.data, cipher_ctx->key.length);\n+\tmemcpy(&dek_attr->key, cipher_ctx->key.data, cipher_ctx->key.length);\n+\tmemcpy(&dek->data, cipher_ctx->key.data, cipher_ctx->key.length);\n+\treturn 0;\n+}\n+\n+static int\n+mlx5_crypto_dek_create_aes_gcm(struct mlx5_crypto_dek *dek,\n+\t\tstruct mlx5_devx_dek_attr *dek_attr,\n+\t\tvoid *cb_ctx)\n+{\n+\tstruct mlx5_crypto_dek_ctx *ctx = cb_ctx;\n+\tstruct rte_crypto_aead_xform *aead_ctx = &ctx->xform->aead;\n+\n+\tif (aead_ctx->algo != RTE_CRYPTO_AEAD_AES_GCM) {\n+\t\tDRV_LOG(ERR, \"Only AES-GCM algo supported.\");\n+\t\treturn -EINVAL;\n+\t}\n+\tdek_attr->key_purpose = MLX5_CRYPTO_KEY_PURPOSE_GCM;\n+\tswitch (aead_ctx->key.length) {\n+\tcase 16:\n+\t\tdek->size = 16;\n+\t\tdek_attr->key_size = MLX5_CRYPTO_KEY_SIZE_128b;\n+\t\tbreak;\n+\tcase 32:\n+\t\tdek->size = 32;\n+\t\tdek_attr->key_size = MLX5_CRYPTO_KEY_SIZE_256b;\n+\t\tbreak;\n+\tdefault:\n+\t\tDRV_LOG(ERR, \"Wrapped key size not supported.\");\n+\t\treturn -EINVAL;\n+\t}\n+#ifdef MLX5_DEK_WRAP\n+\tif (ctx->priv->is_gcm_dek_wrap)\n+\t\tdek_attr->sw_wrapped = 1;\n+#endif\n+\tmemcpy(&dek_attr->key, aead_ctx->key.data, aead_ctx->key.length);\n+\tmemcpy(&dek->data, aead_ctx->key.data, aead_ctx->key.length);\n+\treturn 0;\n+}\n+\n+static struct mlx5_list_entry *\n+mlx5_crypto_dek_create_cb(void *tool_ctx __rte_unused, void *cb_ctx)\n+{\n+\tstruct mlx5_crypto_dek_ctx *ctx = cb_ctx;\n+\tstruct rte_crypto_sym_xform *xform = ctx->xform;\n+\tstruct mlx5_crypto_dek *dek = rte_zmalloc(__func__, sizeof(*dek),\n+\t\t\t\t\t\t RTE_CACHE_LINE_SIZE);\n+\tstruct mlx5_devx_dek_attr dek_attr = {\n+\t\t.pd = ctx->priv->cdev->pdn,\n+\t};\n+\tint ret = -1;\n+\n+\tif (dek == NULL) {\n+\t\tDRV_LOG(ERR, \"Failed to allocate dek memory.\");\n+\t\treturn NULL;\n+\t}\n+\tif (xform->type == RTE_CRYPTO_SYM_XFORM_CIPHER)\n+\t\tret = mlx5_crypto_dek_create_aes_xts(dek, &dek_attr, cb_ctx);\n+\telse if (xform->type == RTE_CRYPTO_SYM_XFORM_AEAD)\n+\t\tret = mlx5_crypto_dek_create_aes_gcm(dek, &dek_attr, cb_ctx);\n+\tif (ret)\n+\t\tgoto fail;\n \tdek->obj = mlx5_devx_cmd_create_dek_obj(ctx->priv->cdev->ctx,\n \t\t\t\t\t\t&dek_attr);\n \tif (dek->obj == NULL) {\n-\t\trte_free(dek);\n-\t\treturn NULL;\n+\t\tDRV_LOG(ERR, \"Failed to create dek obj.\");\n+\t\tgoto fail;\n \t}\n-\tmemcpy(&dek->data, cipher_ctx->key.data, cipher_ctx->key.length);\n \treturn &dek->entry;\n+fail:\n+\trte_free(dek);\n+\treturn NULL;\n }\n \n+\n static void\n mlx5_crypto_dek_remove_cb(void *tool_ctx __rte_unused,\n \t\t\t struct mlx5_list_entry *entry)\ndiff --git a/drivers/crypto/mlx5/mlx5_crypto_gcm.c b/drivers/crypto/mlx5/mlx5_crypto_gcm.c\nindex d60ac379cf..c7fd86d7b9 100644\n--- a/drivers/crypto/mlx5/mlx5_crypto_gcm.c\n+++ b/drivers/crypto/mlx5/mlx5_crypto_gcm.c\n@@ -95,6 +95,8 @@ mlx5_crypto_gcm_init(struct mlx5_crypto_priv *priv)\n \t\treturn -1;\n \t}\n \tpriv->caps = mlx5_crypto_gcm_caps;\n+\tpriv->is_gcm_dek_wrap = !!(cdev->config.hca_attr.sw_wrapped_dek &\n+\t\t\t\t(1 << MLX5_CRYPTO_KEY_PURPOSE_GCM));\n \treturn 0;\n }\n \n", "prefixes": [ "RFC", "2/5" ] }