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GET /api/patches/126224/?format=api
{ "id": 126224, "url": "http://patches.dpdk.org/api/patches/126224/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20230418082529.544777-5-sivaprasad.tummala@amd.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20230418082529.544777-5-sivaprasad.tummala@amd.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20230418082529.544777-5-sivaprasad.tummala@amd.com", "date": "2023-04-18T08:25:29", "name": "[v4,4/4] power: amd power monitor support", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "028a2f5fbbbb5c4eaca0c8c3e8de83da37fc78db", "submitter": { "id": 2510, "url": "http://patches.dpdk.org/api/people/2510/?format=api", "name": "Sivaprasad Tummala", "email": "Sivaprasad.Tummala@amd.com" }, "delegate": { "id": 24651, "url": "http://patches.dpdk.org/api/users/24651/?format=api", "username": "dmarchand", "first_name": "David", "last_name": "Marchand", "email": "david.marchand@redhat.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20230418082529.544777-5-sivaprasad.tummala@amd.com/mbox/", "series": [ { "id": 27753, "url": "http://patches.dpdk.org/api/series/27753/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=27753", "date": "2023-04-18T08:25:26", "name": "[v4,1/4] doc: announce new cpu flag added to rte_cpu_flag_t", "version": 4, "mbox": "http://patches.dpdk.org/series/27753/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/126224/comments/", "check": "warning", "checks": "http://patches.dpdk.org/api/patches/126224/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 4A04B4297B;\n\tTue, 18 Apr 2023 10:26:26 +0200 (CEST)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 34F2042D29;\n\tTue, 18 Apr 2023 10:26:04 +0200 (CEST)", "from NAM11-DM6-obe.outbound.protection.outlook.com\n (mail-dm6nam11on2064.outbound.protection.outlook.com [40.107.223.64])\n by mails.dpdk.org (Postfix) with ESMTP id 8697A40698\n for <dev@dpdk.org>; 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helo=SATLEXMB04.amd.com; pr=C", "From": "Sivaprasad Tummala <sivaprasad.tummala@amd.com>", "To": "<david.hunt@intel.com>", "CC": "<dev@dpdk.org>, <david.marchand@redhat.com>, <ferruh.yigit@amd.com>", "Subject": "[PATCH v4 4/4] power: amd power monitor support", "Date": "Tue, 18 Apr 2023 01:25:29 -0700", "Message-ID": "<20230418082529.544777-5-sivaprasad.tummala@amd.com>", "X-Mailer": "git-send-email 2.34.1", "In-Reply-To": "<20230418082529.544777-1-sivaprasad.tummala@amd.com>", "References": "<20230417043136.470110-1-sivaprasad.tummala@amd.com>\n <20230418082529.544777-1-sivaprasad.tummala@amd.com>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"UTF-8\"", "Content-Transfer-Encoding": "8bit", "X-Originating-IP": "[10.180.168.240]", "X-ClientProxiedBy": "SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com\n (10.181.40.145)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "BN8NAM11FT053:EE_|DM6PR12MB4402:EE_", "X-MS-Office365-Filtering-Correlation-Id": "c6d67b32-ca02-439c-1ee7-08db3fe688ba", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n YT1R/ujInrFGSNkcH3T88I8BtSs1POL02phF8GmEVxCMaSo2v1UR7asKVWY0XFVBgYi3AYAwGHp4nWk3oJQlxJpcqE6N5cmmaCYZEasCeIl0JqcVSoUDyE4aZiV9u18JdaXKff11K1/YHISlPNqiJUZvSLMkYJztGcCE5UwuK+f+Biff41QrQ0JOAQ7sKD+LjL/Ady+Prgk3jVnyE+4ImXsLF+wHBtKU7z7Gj4agpT3sAPMtMDYgvi7+tbsi+NO+JagZQCDOKC/I9bUKCPwOkP5mYtBOAfUICg+Arsn6Zr9dqwgkzx4ZhGdC8ZJCw8Qo5sv9r5ZXvDLL/uzauLXPVY9roQUlZLulB17/W5Gyaxfcb94pL0r6/XPU7eLFowD5m9ZRWpbaJRmXUsfUxoQ8d6WZGF2yiGWUZEjs0cl4MX1Rv+tSk2I82lm5WU+X4+dOlzD+yZW05eAkOHqu0UXSJ4XMNWvzH3OVWvYDU9Atc9akpHsC25OwUmJ0likeb9Yza5UkUI7YAtWwrRj34IZ+bfjxx8KKab5YzuxjDW3sNWQqY4fO/c06mnckdJvLnra2gulJOkEbmPWZKO43BsFz8bGnulGgnyygMcHo5+O568wvF6KNq4iSbfihG6jSdUnVyKi5VZwbSOco2eZnnucva6jp+ynqnKy1nClsehuiJWZuPAhJPVPLxeOn5ksIhx7uuyA9ACI1K1YR8/6Lqh72Wnw65sC49QN8UZKU05EJzFE=", "X-Forefront-Antispam-Report": "CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:;\n IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE;\n SFS:(13230028)(4636009)(346002)(136003)(376002)(39860400002)(396003)(451199021)(36840700001)(40470700004)(46966006)(36756003)(8936002)(8676002)(40460700003)(44832011)(5660300002)(2906002)(82310400005)(86362001)(40480700001)(478600001)(7696005)(6666004)(54906003)(16526019)(186003)(2616005)(36860700001)(1076003)(70586007)(70206006)(26005)(41300700001)(356005)(82740400003)(316002)(83380400001)(81166007)(6916009)(4326008)(47076005)(426003)(336012)(36900700001);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "amd.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "18 Apr 2023 08:25:57.1515 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n c6d67b32-ca02-439c-1ee7-08db3fe688ba", "X-MS-Exchange-CrossTenant-Id": "3dd8961f-e488-4e60-8e11-a82d994e183d", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17];\n Helo=[SATLEXMB04.amd.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n BN8NAM11FT053.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "DM6PR12MB4402", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "mwaitx allows EPYC processors to enter a implementation dependent\npower/performance optimized state (C1 state) for a specific period\nor until a store to the monitored address range.\n\nSigned-off-by: Sivaprasad Tummala <sivaprasad.tummala@amd.com>\n---\n lib/eal/x86/rte_power_intrinsics.c | 77 +++++++++++++++++++++++++-----\n 1 file changed, 66 insertions(+), 11 deletions(-)", "diff": "diff --git a/lib/eal/x86/rte_power_intrinsics.c b/lib/eal/x86/rte_power_intrinsics.c\nindex 6eb9e50807..27055bab52 100644\n--- a/lib/eal/x86/rte_power_intrinsics.c\n+++ b/lib/eal/x86/rte_power_intrinsics.c\n@@ -17,6 +17,60 @@ static struct power_wait_status {\n \tvolatile void *monitor_addr; /**< NULL if not currently sleeping */\n } __rte_cache_aligned wait_status[RTE_MAX_LCORE];\n \n+/**\n+ * These functions uses UMONITOR/UMWAIT instructions and will enter C0.2 state.\n+ * For more information about usage of these instructions, please refer to\n+ * Intel(R) 64 and IA-32 Architectures Software Developer's Manual.\n+ */\n+static void intel_umonitor(volatile void *addr)\n+{\n+\t/* UMONITOR */\n+\tasm volatile(\".byte 0xf3, 0x0f, 0xae, 0xf7;\"\n+\t\t\t:\n+\t\t\t: \"D\"(addr));\n+}\n+\n+static void intel_umwait(const uint64_t timeout)\n+{\n+\tconst uint32_t tsc_l = (uint32_t)timeout;\n+\tconst uint32_t tsc_h = (uint32_t)(timeout >> 32);\n+\t/* UMWAIT */\n+\tasm volatile(\".byte 0xf2, 0x0f, 0xae, 0xf7;\"\n+\t\t\t: /* ignore rflags */\n+\t\t\t: \"D\"(0), /* enter C0.2 */\n+\t\t\t\"a\"(tsc_l), \"d\"(tsc_h));\n+}\n+\n+/**\n+ * These functions uses MONITORX/MWAITX instructions and will enter C1 state.\n+ * For more information about usage of these instructions, please refer to\n+ * AMD64 Architecture Programmer’s Manual.\n+ */\n+static void amd_monitorx(volatile void *addr)\n+{\n+\t/* MONITORX */\n+\tasm volatile(\".byte 0x0f, 0x01, 0xfa;\"\n+\t\t\t:\n+\t\t\t: \"a\"(addr),\n+\t\t\t\"c\"(0), /* no extensions */\n+\t\t\t\"d\"(0)); /* no hints */\n+}\n+\n+static void amd_mwaitx(const uint64_t timeout)\n+{\n+\t/* MWAITX */\n+\tasm volatile(\".byte 0x0f, 0x01, 0xfb;\"\n+\t\t\t: /* ignore rflags */\n+\t\t\t: \"a\"(0), /* enter C1 */\n+\t\t\t\"c\"(2), /* enable timer */\n+\t\t\t\"b\"(timeout));\n+}\n+\n+static struct {\n+\tvoid (*mmonitor)(volatile void *addr);\n+\tvoid (*mwait)(const uint64_t timeout);\n+} __rte_cache_aligned power_monitor_ops;\n+\n static inline void\n __umwait_wakeup(volatile void *addr)\n {\n@@ -75,8 +129,6 @@ int\n rte_power_monitor(const struct rte_power_monitor_cond *pmc,\n \t\tconst uint64_t tsc_timestamp)\n {\n-\tconst uint32_t tsc_l = (uint32_t)tsc_timestamp;\n-\tconst uint32_t tsc_h = (uint32_t)(tsc_timestamp >> 32);\n \tconst unsigned int lcore_id = rte_lcore_id();\n \tstruct power_wait_status *s;\n \tuint64_t cur_value;\n@@ -109,10 +161,8 @@ rte_power_monitor(const struct rte_power_monitor_cond *pmc,\n \t * versions support this instruction natively.\n \t */\n \n-\t/* set address for UMONITOR */\n-\tasm volatile(\".byte 0xf3, 0x0f, 0xae, 0xf7;\"\n-\t\t\t:\n-\t\t\t: \"D\"(pmc->addr));\n+\t/* set address for mmonitor */\n+\tpower_monitor_ops.mmonitor(pmc->addr);\n \n \t/* now that we've put this address into monitor, we can unlock */\n \trte_spinlock_unlock(&s->lock);\n@@ -123,11 +173,8 @@ rte_power_monitor(const struct rte_power_monitor_cond *pmc,\n \tif (pmc->fn(cur_value, pmc->opaque) != 0)\n \t\tgoto end;\n \n-\t/* execute UMWAIT */\n-\tasm volatile(\".byte 0xf2, 0x0f, 0xae, 0xf7;\"\n-\t\t\t: /* ignore rflags */\n-\t\t\t: \"D\"(0), /* enter C0.2 */\n-\t\t\t \"a\"(tsc_l), \"d\"(tsc_h));\n+\t/* execute mwait */\n+\tpower_monitor_ops.mwait(tsc_timestamp);\n \n end:\n \t/* erase sleep address */\n@@ -173,6 +220,14 @@ RTE_INIT(rte_power_intrinsics_init) {\n \t\twait_multi_supported = 1;\n \tif (i.power_monitor)\n \t\tmonitor_supported = 1;\n+\n+\tif (rte_cpu_get_flag_enabled(RTE_CPUFLAG_MONITORX)) { /* AMD */\n+\t\tpower_monitor_ops.mmonitor = &amd_monitorx;\n+\t\tpower_monitor_ops.mwait = &amd_mwaitx;\n+\t} else { /* Intel */\n+\t\tpower_monitor_ops.mmonitor = &intel_umonitor;\n+\t\tpower_monitor_ops.mwait = &intel_umwait;\n+\t}\n }\n \n int\n", "prefixes": [ "v4", "4/4" ] }