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GET /api/patches/126166/?format=api
{ "id": 126166, "url": "http://patches.dpdk.org/api/patches/126166/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20230412162636.30843-4-doshir@vmware.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20230412162636.30843-4-doshir@vmware.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20230412162636.30843-4-doshir@vmware.com", "date": "2023-04-12T16:26:32", "name": "[next,3/7] vmxnet3: add support for large passthrough BAR register", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": true, "hash": "242ff88c520e678b04ac66b329a49351911c1a75", "submitter": { "id": 3045, "url": "http://patches.dpdk.org/api/people/3045/?format=api", "name": "Ronak Doshi", "email": "doshir@vmware.com" }, "delegate": { "id": 319, "url": "http://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20230412162636.30843-4-doshir@vmware.com/mbox/", "series": [ { "id": 27734, "url": "http://patches.dpdk.org/api/series/27734/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=27734", "date": "2023-04-12T16:26:29", "name": "vmxnet3: upgrade to version 7", "version": 1, "mbox": "http://patches.dpdk.org/series/27734/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/126166/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/126166/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 60D324296B;\n\tMon, 17 Apr 2023 10:15:56 +0200 (CEST)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id B366E42D36;\n\tMon, 17 Apr 2023 10:15:12 +0200 (CEST)", "from EX-PRD-EDGE02.vmware.com (ex-prd-edge02.vmware.com\n [208.91.3.34]) by mails.dpdk.org (Postfix) with ESMTP id 84EAE410F2\n for <dev@dpdk.org>; Wed, 12 Apr 2023 18:26:51 +0200 (CEST)", "from sc9-mailhost1.vmware.com (10.113.161.71) by\n EX-PRD-EDGE02.vmware.com (10.188.245.7) with Microsoft SMTP Server id\n 15.1.2375.34; Wed, 12 Apr 2023 09:26:33 -0700", "from htb-1n-eng-dhcp122.eng.vmware.com (unknown [10.20.114.216])\n by sc9-mailhost1.vmware.com (Postfix) with ESMTP id 027C8201E4;\n Wed, 12 Apr 2023 09:26:39 -0700 (PDT)", "by htb-1n-eng-dhcp122.eng.vmware.com (Postfix, from userid 0)\n id E8C3AA8385; Wed, 12 Apr 2023 09:26:38 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; s=s1024; d=vmware.com;\n h=from:to:cc:subject:date:message-id:in-reply-to:mime-version:\n content-type; bh=SqdvuXHFRjO4vWEh4fc1HS6oJBGR1vTANLGr/cKawr8=;\n b=FUQAQ2lV8Lbpl1+ICksN1aiCc+x+VezOnQXrveFFp43kFkIrXmRMRHrYWv2y8t\n bqGLSTLvgadf4jUb2VlQmyppKf+5+bOj/XtAGuYH/yRSZDH8nmzVvt+D4GqbBi\n Zm8/b2lrLZTSXLj+4hvsbMwpvaqAJUKtITzAMLmgs28AO/g=", "From": "Ronak Doshi <doshir@vmware.com>", "To": "Jochen Behrens <jbehrens@vmware.com>", "CC": "<dev@dpdk.org>, Ronak Doshi <doshir@vmware.com>", "Subject": "[PATCH next 3/7] vmxnet3: add support for large passthrough BAR\n register", "Date": "Wed, 12 Apr 2023 09:26:32 -0700", "Message-ID": "<20230412162636.30843-4-doshir@vmware.com>", "X-Mailer": "git-send-email 2.11.0", "In-Reply-To": "<20230412162636.30843-1-doshir@vmware.com>", "References": "<20230412162636.30843-1-doshir@vmware.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "Received-SPF": "None (EX-PRD-EDGE02.vmware.com: doshir@vmware.com does not\n designate permitted sender hosts)", "X-Mailman-Approved-At": "Mon, 17 Apr 2023 10:15:01 +0200", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "For vmxnet3 to work in UPT mode, the BAR sizes have been increased.\nThe PT page has been extended to 2 pages and also includes OOB pages\nas a part of PT BAR. This patch enhances vmxnet3 to use appropriate\nBAR offsets based on the capability registered. To use new offsets,\nVMXNET3_CAP_LARGE_BAR needs to be set by the device. If it is not set\nthen the device will use legacy PT page layout.\n\nSigned-off-by: Ronak Doshi <doshir@vmware.com>\nAcked-by: Jochen Behrens <jbehrens@vmware.com>\n---\n drivers/net/vmxnet3/base/vmxnet3_defs.h | 13 +++++++++++--\n drivers/net/vmxnet3/vmxnet3_ethdev.c | 11 +++++++++++\n drivers/net/vmxnet3/vmxnet3_ethdev.h | 2 ++\n drivers/net/vmxnet3/vmxnet3_rxtx.c | 13 +++++++------\n 4 files changed, 31 insertions(+), 8 deletions(-)", "diff": "diff --git a/drivers/net/vmxnet3/base/vmxnet3_defs.h b/drivers/net/vmxnet3/base/vmxnet3_defs.h\nindex 759fdb6e4a..27f35a0062 100644\n--- a/drivers/net/vmxnet3/base/vmxnet3_defs.h\n+++ b/drivers/net/vmxnet3/base/vmxnet3_defs.h\n@@ -43,8 +43,16 @@\n #define VMXNET3_REG_RXPROD 0x800 /* Rx Producer Index for ring 1 */\n #define VMXNET3_REG_RXPROD2 0xA00 /* Rx Producer Index for ring 2 */\n \n-#define VMXNET3_PT_REG_SIZE 4096 /* BAR 0 */\n-#define VMXNET3_VD_REG_SIZE 4096 /* BAR 1 */\n+/* For Large PT BAR, the following offset to DB register */\n+#define VMXNET3_REG_LB_TXPROD 0x1000 /* Tx Producer Index */\n+#define VMXNET3_REG_LB_RXPROD 0x1400 /* Rx Producer Index for ring 1 */\n+#define VMXNET3_REG_LB_RXPROD2 0x1800 /* Rx Producer Index for ring 2 */\n+\n+#define VMXNET3_PT_REG_SIZE 4096 /* BAR 0 */\n+#define VMXNET3_LARGE_PT_REG_SIZE 8192 /* large PT pages */\n+#define VMXNET3_VD_REG_SIZE 4096 /* BAR 1 */\n+#define VMXNET3_LARGE_BAR0_REG_SIZE (4096 * 4096) /* LARGE BAR 0 */\n+#define VMXNET3_OOB_REG_SIZE (4094 * 4096) /* OOB pages */\n \n /*\n * The two Vmxnet3 MMIO Register PCI BARs (BAR 0 at offset 10h and BAR 1 at\n@@ -56,6 +64,7 @@\n * VMXNET3_MSIX_BAR_SIZE is defined in \"vmxnet3Int.h\"\n */\n #define VMXNET3_PHYSMEM_PAGES 4\n+#define VMXNET3_PHYSMEM_LB_PAGES 4099 /* 4096 + 1 + 2 */\n \n #define VMXNET3_REG_ALIGN 8 /* All registers are 8-byte aligned. */\n #define VMXNET3_REG_ALIGN_MASK 0x7\ndiff --git a/drivers/net/vmxnet3/vmxnet3_ethdev.c b/drivers/net/vmxnet3/vmxnet3_ethdev.c\nindex 8d656ffaf8..a04a16a3e0 100644\n--- a/drivers/net/vmxnet3/vmxnet3_ethdev.c\n+++ b/drivers/net/vmxnet3/vmxnet3_ethdev.c\n@@ -456,6 +456,17 @@ eth_vmxnet3_dev_init(struct rte_eth_dev *eth_dev)\n \t\thw->uptv2_enabled = TRUE;\n \t\teth_vmxnet3_setup_capabilities(hw, eth_dev);\n \t}\n+\n+\tif (hw->used_DCR_capabilities[0] & (1 << VMXNET3_CAP_LARGE_BAR)) {\n+\t\thw->tx_prod_offset = VMXNET3_REG_LB_TXPROD;\n+\t\thw->rx_prod_offset[0] = VMXNET3_REG_LB_RXPROD;\n+\t\thw->rx_prod_offset[1] = VMXNET3_REG_LB_RXPROD2;\n+\t} else {\n+\t\thw->tx_prod_offset = VMXNET3_REG_TXPROD;\n+\t\thw->rx_prod_offset[0] = VMXNET3_REG_RXPROD;\n+\t\thw->rx_prod_offset[1] = VMXNET3_REG_RXPROD2;\n+\t}\n+\n \t/* Getting MAC Address */\n \tmac_lo = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_MACL);\n \tmac_hi = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_MACH);\ndiff --git a/drivers/net/vmxnet3/vmxnet3_ethdev.h b/drivers/net/vmxnet3/vmxnet3_ethdev.h\nindex 1bbf2b4465..cabd83e7e1 100644\n--- a/drivers/net/vmxnet3/vmxnet3_ethdev.h\n+++ b/drivers/net/vmxnet3/vmxnet3_ethdev.h\n@@ -122,6 +122,8 @@ struct vmxnet3_hw {\n \tUPT1_RxStats\t saved_rx_stats[VMXNET3_EXT_MAX_RX_QUEUES];\n \tUPT1_TxStats snapshot_tx_stats[VMXNET3_MAX_TX_QUEUES];\n \tUPT1_RxStats snapshot_rx_stats[VMXNET3_MAX_RX_QUEUES];\n+\tuint16_t tx_prod_offset;\n+\tuint16_t rx_prod_offset[2];\n \t/* device capability bit map */\n \tuint32_t\t DCR_capabilities[8];\n \t/* pass-through capability bit map */\ndiff --git a/drivers/net/vmxnet3/vmxnet3_rxtx.c b/drivers/net/vmxnet3/vmxnet3_rxtx.c\nindex a875ffec07..83daac02c4 100644\n--- a/drivers/net/vmxnet3/vmxnet3_rxtx.c\n+++ b/drivers/net/vmxnet3/vmxnet3_rxtx.c\n@@ -57,8 +57,6 @@\n #define\tVMXNET3_TX_OFFLOAD_NOTSUP_MASK\t\\\n \t(RTE_MBUF_F_TX_OFFLOAD_MASK ^ VMXNET3_TX_OFFLOAD_MASK)\n \n-static const uint32_t rxprod_reg[2] = {VMXNET3_REG_RXPROD, VMXNET3_REG_RXPROD2};\n-\n static int vmxnet3_post_rx_bufs(vmxnet3_rx_queue_t*, uint8_t);\n static void vmxnet3_tq_tx_complete(vmxnet3_tx_queue_t *);\n #ifdef RTE_LIBRTE_VMXNET3_DEBUG_DRIVER_NOT_USED\n@@ -577,7 +575,7 @@ vmxnet3_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,\n \tif (deferred >= rte_le_to_cpu_32(txq_ctrl->txThreshold)) {\n \t\ttxq_ctrl->txNumDeferred = 0;\n \t\t/* Notify vSwitch that packets are available. */\n-\t\tVMXNET3_WRITE_BAR0_REG(hw, (VMXNET3_REG_TXPROD + txq->queue_id * VMXNET3_REG_ALIGN),\n+\t\tVMXNET3_WRITE_BAR0_REG(hw, (hw->tx_prod_offset + txq->queue_id * VMXNET3_REG_ALIGN),\n \t\t\t\t txq->cmd_ring.next2fill);\n \t}\n \n@@ -1000,7 +998,8 @@ vmxnet3_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)\n \t\t/* It's time to renew descriptors */\n \t\tvmxnet3_renew_desc(rxq, ring_idx, newm);\n \t\tif (unlikely(rxq->shared->ctrl.updateRxProd)) {\n-\t\t\tVMXNET3_WRITE_BAR0_REG(hw, rxprod_reg[ring_idx] + (rxq->queue_id * VMXNET3_REG_ALIGN),\n+\t\t\tVMXNET3_WRITE_BAR0_REG(hw, hw->rx_prod_offset[ring_idx] +\n+\t\t\t\t\t (rxq->queue_id * VMXNET3_REG_ALIGN),\n \t\t\t\t\t rxq->cmd_ring[ring_idx].next2fill);\n \t\t}\n \n@@ -1027,7 +1026,8 @@ vmxnet3_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)\n \t\t}\n \t\tif (unlikely(rxq->shared->ctrl.updateRxProd)) {\n \t\t\tfor (ring_idx = 0; ring_idx < VMXNET3_RX_CMDRING_SIZE; ring_idx++) {\n-\t\t\t\tVMXNET3_WRITE_BAR0_REG(hw, rxprod_reg[ring_idx] + (rxq->queue_id * VMXNET3_REG_ALIGN),\n+\t\t\t\tVMXNET3_WRITE_BAR0_REG(hw, hw->rx_prod_offset[ring_idx] +\n+\t\t\t\t\t\t (rxq->queue_id * VMXNET3_REG_ALIGN),\n \t\t\t\t\t\t rxq->cmd_ring[ring_idx].next2fill);\n \t\t\t}\n \t\t}\n@@ -1322,7 +1322,8 @@ vmxnet3_dev_rxtx_init(struct rte_eth_dev *dev)\n \t\t\t * mbufs for coming packets.\n \t\t\t */\n \t\t\tif (unlikely(rxq->shared->ctrl.updateRxProd)) {\n-\t\t\t\tVMXNET3_WRITE_BAR0_REG(hw, rxprod_reg[j] + (rxq->queue_id * VMXNET3_REG_ALIGN),\n+\t\t\t\tVMXNET3_WRITE_BAR0_REG(hw, hw->rx_prod_offset[j] +\n+\t\t\t\t\t\t (rxq->queue_id * VMXNET3_REG_ALIGN),\n \t\t\t\t\t\t rxq->cmd_ring[j].next2fill);\n \t\t\t}\n \t\t}\n", "prefixes": [ "next", "3/7" ] }