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GET /api/patches/126160/?format=api
{ "id": 126160, "url": "http://patches.dpdk.org/api/patches/126160/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20230412162636.30843-3-doshir@vmware.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20230412162636.30843-3-doshir@vmware.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20230412162636.30843-3-doshir@vmware.com", "date": "2023-04-12T16:26:31", "name": "[next,2/7] vmxnet3: add support for capability registers", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": true, "hash": "9e5994aed15b49f9abd22158bfb6c4b3f402d4d6", "submitter": { "id": 3045, "url": "http://patches.dpdk.org/api/people/3045/?format=api", "name": "Ronak Doshi", "email": "doshir@vmware.com" }, "delegate": { "id": 319, "url": "http://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20230412162636.30843-3-doshir@vmware.com/mbox/", "series": [ { "id": 27734, "url": "http://patches.dpdk.org/api/series/27734/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=27734", "date": "2023-04-12T16:26:29", "name": "vmxnet3: upgrade to version 7", "version": 1, "mbox": "http://patches.dpdk.org/series/27734/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/126160/comments/", "check": "warning", "checks": "http://patches.dpdk.org/api/patches/126160/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 81EEC4296B;\n\tMon, 17 Apr 2023 10:15:14 +0200 (CEST)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 4A44642BC9;\n\tMon, 17 Apr 2023 10:15:05 +0200 (CEST)", "from EX-PRD-EDGE01.vmware.com (EX-PRD-EDGE01.vmware.com\n [208.91.3.33]) by mails.dpdk.org (Postfix) with ESMTP id 19FE9406A2\n for <dev@dpdk.org>; Wed, 12 Apr 2023 18:26:46 +0200 (CEST)", "from sc9-mailhost1.vmware.com (10.113.161.71) by\n EX-PRD-EDGE01.vmware.com (10.188.245.6) with Microsoft SMTP Server id\n 15.1.2375.34; Wed, 12 Apr 2023 09:26:32 -0700", "from htb-1n-eng-dhcp122.eng.vmware.com (unknown [10.20.114.216])\n by sc9-mailhost1.vmware.com (Postfix) with ESMTP id D050B201E4;\n Wed, 12 Apr 2023 09:26:38 -0700 (PDT)", "by htb-1n-eng-dhcp122.eng.vmware.com (Postfix, from userid 0)\n id CBB79A8385; Wed, 12 Apr 2023 09:26:38 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; s=s1024; d=vmware.com;\n h=from:to:cc:subject:date:message-id:in-reply-to:mime-version:\n content-type; bh=NrgzHrSPp6YU+i+DprmHDW5ojvMEQYJjO0Xd1GRIsx0=;\n b=Q/c8m9ipQlCRFILWCijzp3RNcKYrVGXG0oSw8aUvCyI5S8GP16QGZSSvxY+kjR\n HpmpZUO3umitOXLC6qY06yzX5Dor70BX4j/TKrzDpQZ7NjBaphoaaHEnIjwVX2\n fPl02UDelkL5tphX10grw8wCwpUBqSygTdUU+IYtkKwQBAI=", "From": "Ronak Doshi <doshir@vmware.com>", "To": "Jochen Behrens <jbehrens@vmware.com>, Thomas Monjalon\n <thomas@monjalon.net>, Ferruh Yigit <ferruh.yigit@amd.com>, Andrew Rybchenko\n <andrew.rybchenko@oktetlabs.ru>", "CC": "<dev@dpdk.org>, Ronak Doshi <doshir@vmware.com>", "Subject": "[PATCH next 2/7] vmxnet3: add support for capability registers", "Date": "Wed, 12 Apr 2023 09:26:31 -0700", "Message-ID": "<20230412162636.30843-3-doshir@vmware.com>", "X-Mailer": "git-send-email 2.11.0", "In-Reply-To": "<20230412162636.30843-1-doshir@vmware.com>", "References": "<20230412162636.30843-1-doshir@vmware.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "Received-SPF": "None (EX-PRD-EDGE01.vmware.com: doshir@vmware.com does not\n designate permitted sender hosts)", "X-Mailman-Approved-At": "Mon, 17 Apr 2023 10:15:01 +0200", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "This patch enhances vmxnet3 to suuport capability registers which\nallows it to enable features selectively. The DCR register tracks\nthe capabilities vmxnet3 device supports. The PTCR register states\nthe capabilities that the passthrough device supports.\n\nWith the help of these registers, vmxnet3 can enable only those\nfeatures which the passthrough device supoprts. This allows\nsmooth trasition to Uniform-Passthrough (UPT) mode if the virtual\nnic requests it. If PTCR register returns nothing or error it means\nUPT is not being requested and vnic will continue in emulation mode.\n\nSigned-off-by: Ronak Doshi <doshir@vmware.com>\nAcked-by: Jochen Behrens <jbehrens@vmware.com>\n---\n drivers/net/vmxnet3/base/vmxnet3_defs.h | 44 +++++++++++++++++---\n drivers/net/vmxnet3/vmxnet3_ethdev.c | 71 +++++++++++++++++++++++++++++++++\n drivers/net/vmxnet3/vmxnet3_ethdev.h | 11 +++++\n lib/ethdev/rte_ethdev.h | 2 +\n 4 files changed, 123 insertions(+), 5 deletions(-)", "diff": "diff --git a/drivers/net/vmxnet3/base/vmxnet3_defs.h b/drivers/net/vmxnet3/base/vmxnet3_defs.h\nindex bd6695e69d..759fdb6e4a 100644\n--- a/drivers/net/vmxnet3/base/vmxnet3_defs.h\n+++ b/drivers/net/vmxnet3/base/vmxnet3_defs.h\n@@ -26,6 +26,12 @@\n #define VMXNET3_REG_MACH 0x30 /* MAC Address High */\n #define VMXNET3_REG_ICR 0x38 /* Interrupt Cause Register */\n #define VMXNET3_REG_ECR 0x40 /* Event Cause Register */\n+#define VMXNET3_REG_DCR 0x48 /* Device capability register,\n+\t\t\t\t * from 0x48 to 0x80\n+\t\t\t\t */\n+#define VMXNET3_REG_PTCR 0x88 /* Passthru capbility register\n+\t\t\t\t * from 0x88 to 0xb0\n+\t\t\t\t */\n \n #define VMXNET3_REG_WSAL 0xF00 /* Wireless Shared Address Lo */\n #define VMXNET3_REG_WSAH 0xF08 /* Wireless Shared Address Hi */\n@@ -103,11 +109,13 @@ typedef enum {\n VMXNET3_CMD_GET_CONF_INTR,\n VMXNET3_CMD_GET_ADAPTIVE_RING_INFO,\n VMXNET3_CMD_GET_TXDATA_DESC_SIZE,\n-\tVMXNET3_CMD_RESERVED5,\n-\tVMXNET3_CMD_RESERVED6,\n-\tVMXNET3_CMD_RESERVED7,\n-\tVMXNET3_CMD_RESERVED8,\n-\tVMXNET3_CMD_GET_MAX_QUEUES_CONF,\n+ VMXNET3_CMD_RESERVED5,\n+ VMXNET3_CMD_RESERVED6,\n+ VMXNET3_CMD_RESERVED7,\n+ VMXNET3_CMD_RESERVED8,\n+ VMXNET3_CMD_GET_MAX_QUEUES_CONF,\n+ VMXNET3_CMD_GET_MAX_CAPABILITIES,\n+ VMXNET3_CMD_GET_DCR0_REG,\n } Vmxnet3_Cmd;\n \n /* Adaptive Ring Info Flags */\n@@ -877,4 +885,30 @@ do {\\\n \n #define VMXNET3_DID_PASSTHRU 0xFFFF\n \n+#define VMXNET3_DCR_ERROR 31 /* error when bit 31 of DCR is set */\n+#define VMXNET3_CAP_UDP_RSS 0 /* bit 0 of DCR 0 */\n+#define VMXNET3_CAP_ESP_RSS_IPV4 1 /* bit 1 of DCR 0 */\n+#define VMXNET3_CAP_GENEVE_CHECKSUM_OFFLOAD 2 /* bit 2 of DCR 0 */\n+#define VMXNET3_CAP_GENEVE_TSO 3 /* bit 3 of DCR 0 */\n+#define VMXNET3_CAP_VXLAN_CHECKSUM_OFFLOAD 4 /* bit 4 of DCR 0 */\n+#define VMXNET3_CAP_VXLAN_TSO 5 /* bit 5 of DCR 0 */\n+#define VMXNET3_CAP_GENEVE_OUTER_CHECKSUM_OFFLOAD 6 /* bit 6 of DCR 0 */\n+#define VMXNET3_CAP_VXLAN_OUTER_CHECKSUM_OFFLOAD 7 /* bit 7 of DCR 0 */\n+#define VMXNET3_CAP_PKT_STEERING_IPV4 8 /* bit 8 of DCR 0 */\n+#define VMXNET3_CAP_VERSION_4_MAX VMXNET3_CAP_PKT_STEERING_IPV4\n+#define VMXNET3_CAP_ESP_RSS_IPV6 9 /* bit 9 of DCR 0 */\n+#define VMXNET3_CAP_VERSION_5_MAX VMXNET3_CAP_ESP_RSS_IPV6\n+#define VMXNET3_CAP_ESP_OVER_UDP_RSS 10 /* bit 10 of DCR 0 */\n+#define VMXNET3_CAP_INNER_RSS 11 /* bit 11 of DCR 0 */\n+#define VMXNET3_CAP_INNER_ESP_RSS 12 /* bit 12 of DCR 0 */\n+#define VMXNET3_CAP_CRC32_HASH_FUNC 13 /* bit 13 of DCR 0 */\n+#define VMXNET3_CAP_VERSION_6_MAX VMXNET3_CAP_CRC32_HASH_FUNC\n+#define VMXNET3_CAP_OAM_FILTER 14 /* bit 14 of DCR 0 */\n+#define VMXNET3_CAP_ESP_QS 15 /* bit 15 of DCR 0 */\n+#define VMXNET3_CAP_LARGE_BAR 16 /* bit 16 of DCR 0 */\n+#define VMXNET3_CAP_OOORX_COMP 17 /* bit 17 of DCR 0 */\n+#define VMXNET3_CAP_VERSION_7_MAX 18\n+/* when new capability is introduced, update VMXNET3_CAP_MAX */\n+#define VMXNET3_CAP_MAX VMXNET3_CAP_VERSION_7_MAX\n+\n #endif /* _VMXNET3_DEFS_H_ */\ndiff --git a/drivers/net/vmxnet3/vmxnet3_ethdev.c b/drivers/net/vmxnet3/vmxnet3_ethdev.c\nindex fd946dec5c..8d656ffaf8 100644\n--- a/drivers/net/vmxnet3/vmxnet3_ethdev.c\n+++ b/drivers/net/vmxnet3/vmxnet3_ethdev.c\n@@ -299,6 +299,61 @@ eth_vmxnet3_txdata_get(struct vmxnet3_hw *hw)\n \t\tsizeof(struct Vmxnet3_TxDataDesc) : txdata_desc_size;\n }\n \n+static int\n+eth_vmxnet3_setup_capabilities(struct vmxnet3_hw *hw,\n+\t\t\t struct rte_eth_dev *eth_dev)\n+{\n+\tuint32_t dcr, ptcr, value;\n+\tstruct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);\n+\n+\tVMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD,\n+\t\t\t VMXNET3_CMD_GET_MAX_CAPABILITIES);\n+\tvalue = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_CMD);\n+\thw->max_capabilities[0] = value;\n+\tdcr = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_DCR);\n+\thw->DCR_capabilities[0] = dcr;\n+\thw->used_DCR_capabilities[0] = 0;\n+\tptcr = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_PTCR);\n+\thw->PTCR_capabilities[0] = ptcr;\n+\thw->used_PTCR_capabilities[0] = 0;\n+\n+\tif (hw->uptv2_enabled && !(ptcr & (1 << VMXNET3_DCR_ERROR))) {\n+\t\tPMD_DRV_LOG(NOTICE, \"UPTv2 enabled\");\n+\t\thw->used_PTCR_capabilities[0] = ptcr;\n+\t} else {\n+\t\t/* Use all DCR capabilities, but disable large bar */\n+\t\thw->used_DCR_capabilities[0] = dcr &\n+\t\t\t\t\t(~(1UL << VMXNET3_CAP_LARGE_BAR));\n+\t\tPMD_DRV_LOG(NOTICE, \"UPTv2 disabled\");\n+\t}\n+\tif (hw->DCR_capabilities[0] & (1UL << VMXNET3_CAP_OOORX_COMP) &&\n+\t hw->PTCR_capabilities[0] & (1UL << VMXNET3_CAP_OOORX_COMP)) {\n+\t\tif (hw->uptv2_enabled) {\n+\t\t\thw->used_PTCR_capabilities[0] |=\n+\t\t\t\t(1UL << VMXNET3_CAP_OOORX_COMP);\n+\t\t}\n+\t}\n+\tif (hw->used_PTCR_capabilities[0]) {\n+\t\tVMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_DCR,\n+\t\t\t\t hw->used_PTCR_capabilities[0]);\n+\t} else if (hw->used_DCR_capabilities[0]) {\n+\t\tVMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_DCR,\n+\t\t\t\t hw->used_DCR_capabilities[0]);\n+\t}\n+\tVMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_GET_DCR0_REG);\n+\tdcr = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_CMD);\n+\thw->used_DCR_capabilities[0] = dcr;\n+\tPMD_DRV_LOG(NOTICE, \"Dev \"PCI_PRI_FMT\", vmxnet3 v%d, UPT enabled: %s, \"\n+\t\t \"DCR0=0x%08x, used DCR=0x%08x, \"\n+\t\t \"PTCR=0x%08x, used PTCR=0x%08x\",\n+\t\t pci_dev->addr.domain, pci_dev->addr.bus,\n+\t\t pci_dev->addr.devid, pci_dev->addr.function, hw->version,\n+\t\t hw->uptv2_enabled ? \"true\" : \"false\",\n+\t\t hw->DCR_capabilities[0], hw->used_DCR_capabilities[0],\n+\t\t hw->PTCR_capabilities[0], hw->used_PTCR_capabilities[0]);\n+\treturn 0;\n+}\n+\n /*\n * It returns 0 on success.\n */\n@@ -396,6 +451,11 @@ eth_vmxnet3_dev_init(struct rte_eth_dev *eth_dev)\n \t\treturn -EIO;\n \t}\n \n+\tif (VMXNET3_VERSION_GE_7(hw)) {\n+\t\t/* start with UPTv2 enabled to avoid ESXi issues */\n+\t\thw->uptv2_enabled = TRUE;\n+\t\teth_vmxnet3_setup_capabilities(hw, eth_dev);\n+\t}\n \t/* Getting MAC Address */\n \tmac_lo = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_MACL);\n \tmac_hi = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_MACH);\n@@ -1433,6 +1493,17 @@ vmxnet3_dev_info_get(struct rte_eth_dev *dev,\n {\n \tstruct vmxnet3_hw *hw = dev->data->dev_private;\n \tint queues = 0;\n+\tuint32_t dcr, ptcr;\n+\n+\tif (VMXNET3_VERSION_GE_7(hw)) {\n+\t\tdcr = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_DCR);\n+\t\tif (dcr & (1 << VMXNET3_CAP_LARGE_BAR)) {\n+\t\t\tptcr = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_PTCR);\n+\t\t\tif (!(ptcr & (1 << VMXNET3_DCR_ERROR))) {\n+\t\t\t\tdev_info->dev_capa = RTE_ETH_DEV_CAPA_PASS_THRU;\n+\t\t\t}\n+\t\t}\n+\t}\n \n \tif (VMXNET3_VERSION_GE_6(hw)) {\n \t\tVMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD,\ndiff --git a/drivers/net/vmxnet3/vmxnet3_ethdev.h b/drivers/net/vmxnet3/vmxnet3_ethdev.h\nindex fc976707fd..1bbf2b4465 100644\n--- a/drivers/net/vmxnet3/vmxnet3_ethdev.h\n+++ b/drivers/net/vmxnet3/vmxnet3_ethdev.h\n@@ -122,6 +122,17 @@ struct vmxnet3_hw {\n \tUPT1_RxStats\t saved_rx_stats[VMXNET3_EXT_MAX_RX_QUEUES];\n \tUPT1_TxStats snapshot_tx_stats[VMXNET3_MAX_TX_QUEUES];\n \tUPT1_RxStats snapshot_rx_stats[VMXNET3_MAX_RX_QUEUES];\n+\t/* device capability bit map */\n+\tuint32_t\t DCR_capabilities[8];\n+\t/* pass-through capability bit map */\n+\tuint32_t\t PTCR_capabilities[8];\n+\t/* max number of capabilities */\n+\tuint32_t\t max_capabilities[8];\n+\t/* used device capability bit map */\n+\tuint32_t\t used_DCR_capabilities[8];\n+\t/* used pass-through capability bit map */\n+\tuint32_t\t used_PTCR_capabilities[8];\n+\tbool uptv2_enabled;\n };\n \n #define VMXNET3_REV_7\t\t6\t\t/* Vmxnet3 Rev. 7 */\ndiff --git a/lib/ethdev/rte_ethdev.h b/lib/ethdev/rte_ethdev.h\nindex 049641d57c..fd0bc30cfd 100644\n--- a/lib/ethdev/rte_ethdev.h\n+++ b/lib/ethdev/rte_ethdev.h\n@@ -1606,6 +1606,8 @@ struct rte_eth_conf {\n #define RTE_ETH_DEV_CAPA_FLOW_RULE_KEEP RTE_BIT64(3)\n /** Device supports keeping shared flow objects across restart. */\n #define RTE_ETH_DEV_CAPA_FLOW_SHARED_OBJECT_KEEP RTE_BIT64(4)\n+/**< (vmxnet3) Device supports smart NIC pass through queues */\n+#define RTE_ETH_DEV_CAPA_PASS_THRU RTE_BIT64(5)\n /**@}*/\n \n /*\n", "prefixes": [ "next", "2/7" ] }