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GET /api/patches/126027/?format=api
{ "id": 126027, "url": "http://patches.dpdk.org/api/patches/126027/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20230413115334.43172-3-sivaprasad.tummala@amd.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20230413115334.43172-3-sivaprasad.tummala@amd.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20230413115334.43172-3-sivaprasad.tummala@amd.com", "date": "2023-04-13T11:53:34", "name": "[v2,3/3] power: amd power monitor support", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "fe1b63ad17f9f8a1875a050e1ee8aa5dbc8087ee", "submitter": { "id": 2510, "url": "http://patches.dpdk.org/api/people/2510/?format=api", "name": "Sivaprasad Tummala", "email": "Sivaprasad.Tummala@amd.com" }, "delegate": { "id": 1, "url": "http://patches.dpdk.org/api/users/1/?format=api", "username": "tmonjalo", "first_name": "Thomas", "last_name": "Monjalon", "email": "thomas@monjalon.net" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20230413115334.43172-3-sivaprasad.tummala@amd.com/mbox/", "series": [ { "id": 27695, "url": "http://patches.dpdk.org/api/series/27695/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=27695", "date": "2023-04-13T11:53:32", "name": "[v2,1/3] eal: add x86 cpuid support for monitorx", "version": 2, "mbox": "http://patches.dpdk.org/series/27695/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/126027/comments/", "check": "fail", "checks": "http://patches.dpdk.org/api/patches/126027/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id C8A1242932;\n\tThu, 13 Apr 2023 13:54:31 +0200 (CEST)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id E2F084114B;\n\tThu, 13 Apr 2023 13:54:30 +0200 (CEST)", "from NAM11-DM6-obe.outbound.protection.outlook.com\n (mail-dm6nam11on2081.outbound.protection.outlook.com [40.107.223.81])\n by mails.dpdk.org (Postfix) with ESMTP id 6B4A14114B\n for <dev@dpdk.org>; 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helo=SATLEXMB04.amd.com; pr=C", "From": "Sivaprasad Tummala <sivaprasad.tummala@amd.com>", "To": "<david.hunt@intel.com>", "CC": "<dev@dpdk.org>", "Subject": "[PATCH v2 3/3] power: amd power monitor support", "Date": "Thu, 13 Apr 2023 04:53:34 -0700", "Message-ID": "<20230413115334.43172-3-sivaprasad.tummala@amd.com>", "X-Mailer": "git-send-email 2.34.1", "In-Reply-To": "<20230413115334.43172-1-sivaprasad.tummala@amd.com>", "References": "<20230413115334.43172-1-sivaprasad.tummala@amd.com>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"UTF-8\"", "Content-Transfer-Encoding": "8bit", "X-Originating-IP": "[10.180.168.240]", "X-ClientProxiedBy": "SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com\n (10.181.40.145)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "DM6NAM11FT075:EE_|MN6PR12MB8592:EE_", "X-MS-Office365-Filtering-Correlation-Id": "634f7fd0-e102-4394-6070-08db3c15d4e4", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n JlcedJ8AJzAJ+s9XZkarAojOZD/kSUErK5OeZEVOf0eB5+iIDaseXj8cGroPq8d4rZz/8fwTjC7fMNg5zb6IfIeydBoCeMJfBgmz+zO1DG6xhE2H1jrr6Cyzel/7E3GV3cKmdrjHDEdX5PoEEzsLaxRuECkN4k2sEhsgGPFvJRy/yQnMLO+7ucQyf0OYEj1oWndqrextUeOkCyJRJjVBVBkFwDbnoeo82O6FhPHP4Rq54AvM01YeWU/AtXWy3frEx7KoHgKs3ZSWP9qRi3IW4i2psLbAEbTQY1JXkglzVEr4VLeVoVsp0bkV0IZJr/n3ca83+vvoGeLOVTwR870kz8KJrZlmo31fYhbnpdudL71bUSQriRosDcMuJ+nJXoGifzRxzJiId1Z7ZCOieB+oqVaupVSnYED9mQyksd54WGP7PN7uQBIG84Ki1PLAPxy9YZ8ya+8RFF+8JghpaF275RHSC05cn16/v6ECLi/g+VxxWCOsL/2zodxAZPULs9y7Q4DQGWarU6+63lVpC+5S7s1ZK9u22UTS0o++++gE5KhH0Ec7Rw43WDWxQaZzZ4RDIYipuvzyeiEx7TtgjcJ5UXYzXykQNOPBeFaqN333hbn+TYdZScGDGNHpS3TbJiU1lKlWubPmz37Nm7JdvSCN2W8FVRw/vYUGnxOla5MO12FBfmQyB7CHiwlScT8cHs19b/7a9yRFoOdQn6h/H0xvdmMobswImTGOlfwyT+yLVJA=", "X-Forefront-Antispam-Report": "CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:;\n IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE;\n SFS:(13230028)(4636009)(376002)(136003)(39860400002)(346002)(396003)(451199021)(46966006)(36840700001)(40470700004)(86362001)(44832011)(40460700003)(478600001)(356005)(81166007)(316002)(41300700001)(82740400003)(8676002)(8936002)(5660300002)(6916009)(70206006)(40480700001)(70586007)(36756003)(1076003)(26005)(426003)(336012)(16526019)(186003)(36860700001)(4326008)(6666004)(83380400001)(2906002)(7696005)(2616005)(82310400005)(47076005)(36900700001);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "amd.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "13 Apr 2023 11:54:26.5992 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 634f7fd0-e102-4394-6070-08db3c15d4e4", "X-MS-Exchange-CrossTenant-Id": "3dd8961f-e488-4e60-8e11-a82d994e183d", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17];\n Helo=[SATLEXMB04.amd.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n DM6NAM11FT075.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "MN6PR12MB8592", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "mwaitx allows epyc processors to enter a implementation dependent\npower/performance optimized state (C1 state) for a specific period\nor until a store to the monitored address range.\n\nSigned-off-by: Sivaprasad Tummala <sivaprasad.tummala@amd.com>\n---\n lib/eal/x86/rte_power_intrinsics.c | 83 ++++++++++++++++++++++++++++--\n lib/power/rte_power_pmd_mgmt.c | 3 +-\n 2 files changed, 82 insertions(+), 4 deletions(-)", "diff": "diff --git a/lib/eal/x86/rte_power_intrinsics.c b/lib/eal/x86/rte_power_intrinsics.c\nindex f749da9b85..d688066b3a 100644\n--- a/lib/eal/x86/rte_power_intrinsics.c\n+++ b/lib/eal/x86/rte_power_intrinsics.c\n@@ -30,6 +30,7 @@ __umwait_wakeup(volatile void *addr)\n \n static bool wait_supported;\n static bool wait_multi_supported;\n+static bool amd_mwaitx_supported;\n \n static inline uint64_t\n __get_umwait_val(const volatile void *p, const uint8_t sz)\n@@ -65,6 +66,76 @@ __check_val_size(const uint8_t sz)\n \t}\n }\n \n+/**\n+ * This function uses MONITORX/MWAITX instructions and will enter C1 state.\n+ * For more information about usage of these instructions, please refer to\n+ * AMD64 Architecture Programmer’s Manual.\n+ */\n+static inline int\n+amd_power_monitorx(const struct rte_power_monitor_cond *pmc,\n+\t\tconst uint64_t tsc_timestamp)\n+{\n+\tconst unsigned int lcore_id = rte_lcore_id();\n+\tstruct power_wait_status *s;\n+\tuint64_t cur_value;\n+\n+\tRTE_SET_USED(tsc_timestamp);\n+\n+\t/* prevent non-EAL thread from using this API */\n+\tif (lcore_id >= RTE_MAX_LCORE)\n+\t\treturn -EINVAL;\n+\n+\tif (pmc == NULL)\n+\t\treturn -EINVAL;\n+\n+\tif (__check_val_size(pmc->size) < 0)\n+\t\treturn -EINVAL;\n+\n+\tif (pmc->fn == NULL)\n+\t\treturn -EINVAL;\n+\n+\ts = &wait_status[lcore_id];\n+\n+\t/* update sleep address */\n+\trte_spinlock_lock(&s->lock);\n+\ts->monitor_addr = pmc->addr;\n+\n+\t/*\n+\t * we're using raw byte codes for now as only the newest compiler\n+\t * versions support this instruction natively.\n+\t */\n+\t/* set address for MONITORX */\n+\tasm volatile(\".byte 0x0f, 0x01, 0xfa;\"\n+\t\t\t:\n+\t\t\t: \"a\"(pmc->addr),\n+\t\t\t\"c\"(0), /* no extensions */\n+\t\t\t\"d\"(0)); /* no hints */\n+\n+\t/* now that we've put this address into monitor, we can unlock */\n+\trte_spinlock_unlock(&s->lock);\n+\n+\tcur_value = __get_umwait_val(pmc->addr, pmc->size);\n+\n+\t/* check if callback indicates we should abort */\n+\tif (pmc->fn(cur_value, pmc->opaque) != 0)\n+\t\tgoto end;\n+\n+\t/* execute MWAITX */\n+\tasm volatile(\".byte 0x0f, 0x01, 0xfb;\"\n+\t\t\t: /* ignore rflags */\n+\t\t\t: \"a\"(0), /* enter C1 */\n+\t\t\t\"c\"(0), /* no time-out */\n+\t\t\t\"b\"(0));\n+\n+end:\n+ /* erase sleep address */\n+\trte_spinlock_lock(&s->lock);\n+\ts->monitor_addr = NULL;\n+\trte_spinlock_unlock(&s->lock);\n+\n+\treturn 0;\n+}\n+\n /**\n * This function uses UMONITOR/UMWAIT instructions and will enter C0.2 state.\n * For more information about usage of these instructions, please refer to\n@@ -81,8 +152,12 @@ rte_power_monitor(const struct rte_power_monitor_cond *pmc,\n \tuint64_t cur_value;\n \n \t/* prevent user from running this instruction if it's not supported */\n-\tif (!wait_supported)\n-\t\treturn -ENOTSUP;\n+\tif (!wait_supported) {\n+\t\tif (amd_mwaitx_supported)\n+\t\t\treturn amd_power_monitorx(pmc, tsc_timestamp);\n+\t\telse\n+\t\t\treturn -ENOTSUP;\n+\t}\n \n \t/* prevent non-EAL thread from using this API */\n \tif (lcore_id >= RTE_MAX_LCORE)\n@@ -170,6 +245,8 @@ RTE_INIT(rte_power_intrinsics_init) {\n \t\twait_supported = 1;\n \tif (i.power_monitor_multi)\n \t\twait_multi_supported = 1;\n+\tif (i.amd_power_monitorx)\n+\t\tamd_mwaitx_supported = 1;\n }\n \n int\n@@ -178,7 +255,7 @@ rte_power_monitor_wakeup(const unsigned int lcore_id)\n \tstruct power_wait_status *s;\n \n \t/* prevent user from running this instruction if it's not supported */\n-\tif (!wait_supported)\n+\tif (!wait_supported && !amd_mwaitx_supported)\n \t\treturn -ENOTSUP;\n \n \t/* prevent buffer overrun */\ndiff --git a/lib/power/rte_power_pmd_mgmt.c b/lib/power/rte_power_pmd_mgmt.c\nindex ca1840387c..048a41dc29 100644\n--- a/lib/power/rte_power_pmd_mgmt.c\n+++ b/lib/power/rte_power_pmd_mgmt.c\n@@ -447,7 +447,8 @@ check_monitor(struct pmd_core_cfg *cfg, const union queue *qdata)\n \tbool multimonitor_supported;\n \n \t/* check if rte_power_monitor is supported */\n-\tif (!global_data.intrinsics_support.power_monitor) {\n+\tif ((!global_data.intrinsics_support.power_monitor) &&\n+\t\t(!global_data.intrinsics_support.amd_power_monitorx)) {\n \t\tRTE_LOG(DEBUG, POWER, \"Monitoring intrinsics are not supported\\n\");\n \t\treturn -ENOTSUP;\n \t}\n", "prefixes": [ "v2", "3/3" ] }