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{
    "id": 126014,
    "url": "http://patches.dpdk.org/api/patches/126014/?format=api",
    "web_url": "http://patches.dpdk.org/project/dpdk/patch/20230413094502.1714755-13-wenjing.qiao@intel.com/",
    "project": {
        "id": 1,
        "url": "http://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<20230413094502.1714755-13-wenjing.qiao@intel.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/20230413094502.1714755-13-wenjing.qiao@intel.com",
    "date": "2023-04-13T09:44:56",
    "name": "[12/18] common/idpf: add SyncE support over VF",
    "commit_ref": null,
    "pull_url": null,
    "state": "superseded",
    "archived": true,
    "hash": "ab0ae6d56aab84b04013b964eed99dd1484c0d8b",
    "submitter": {
        "id": 2680,
        "url": "http://patches.dpdk.org/api/people/2680/?format=api",
        "name": "Wenjing Qiao",
        "email": "wenjing.qiao@intel.com"
    },
    "delegate": {
        "id": 1540,
        "url": "http://patches.dpdk.org/api/users/1540/?format=api",
        "username": "qzhan15",
        "first_name": "Qi",
        "last_name": "Zhang",
        "email": "qi.z.zhang@intel.com"
    },
    "mbox": "http://patches.dpdk.org/project/dpdk/patch/20230413094502.1714755-13-wenjing.qiao@intel.com/mbox/",
    "series": [
        {
            "id": 27692,
            "url": "http://patches.dpdk.org/api/series/27692/?format=api",
            "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=27692",
            "date": "2023-04-13T09:44:44",
            "name": "update idpf shared code",
            "version": 1,
            "mbox": "http://patches.dpdk.org/series/27692/mbox/"
        }
    ],
    "comments": "http://patches.dpdk.org/api/patches/126014/comments/",
    "check": "success",
    "checks": "http://patches.dpdk.org/api/patches/126014/checks/",
    "tags": {},
    "related": [],
    "headers": {
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        "X-ExtLoop1": "1",
        "From": "Wenjing Qiao <wenjing.qiao@intel.com>",
        "To": "jingjing.wu@intel.com,\n\tbeilei.xing@intel.com,\n\tqi.z.zhang@intel.com",
        "Cc": "dev@dpdk.org, Wenjing Qiao <wenjing.qiao@intel.com>,\n Piotr Gardocki <piotrx.gardocki@intel.com>",
        "Subject": "[PATCH 12/18] common/idpf: add SyncE support over VF",
        "Date": "Thu, 13 Apr 2023 05:44:56 -0400",
        "Message-Id": "<20230413094502.1714755-13-wenjing.qiao@intel.com>",
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        "References": "<20230413094502.1714755-1-wenjing.qiao@intel.com>",
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    },
    "content": "This patch enables to VF access to all SyncE related operations.\n\nMost of the opcodes in this implementation map directly to the\nAQ commands. Additionally there is a VIRTCHNL_OP_SYNCE_GET_HW_INFO\nopcode which should be used by VF to discover all hardware\nrelated details required for Synce operations.\n\nThe goal of this implementation is to provide device agnostic\ninterface to the VF, but due to the feature design the VF will\nget the minimum HW details via VIRTCHNL_OP_SYNCE_GET_HW_INFO\nopcode.\n\nSigned-off-by: Piotr Gardocki <piotrx.gardocki@intel.com>\nSigned-off-by: Wenjing Qiao <wenjing.qiao@intel.com>\n---\n drivers/common/idpf/base/virtchnl.h | 582 ++++++++++++++++++++++++++++\n 1 file changed, 582 insertions(+)",
    "diff": "diff --git a/drivers/common/idpf/base/virtchnl.h b/drivers/common/idpf/base/virtchnl.h\nindex 3008802c4a..54d66c4913 100644\n--- a/drivers/common/idpf/base/virtchnl.h\n+++ b/drivers/common/idpf/base/virtchnl.h\n@@ -184,6 +184,19 @@ enum virtchnl_ops {\n \tVIRTCHNL_OP_CONFIG_QUANTA = 113,\n \tVIRTCHNL_OP_FLOW_SUBSCRIBE = 114,\n \tVIRTCHNL_OP_FLOW_UNSUBSCRIBE = 115,\n+\tVIRTCHNL_OP_SYNCE_GET_PHY_REC_CLK_OUT = 116,\n+\tVIRTCHNL_OP_SYNCE_SET_PHY_REC_CLK_OUT = 117,\n+\tVIRTCHNL_OP_SYNCE_GET_CGU_REF_PRIO = 118,\n+\tVIRTCHNL_OP_SYNCE_SET_CGU_REF_PRIO = 119,\n+\tVIRTCHNL_OP_SYNCE_GET_INPUT_PIN_CFG = 120,\n+\tVIRTCHNL_OP_SYNCE_SET_INPUT_PIN_CFG = 121,\n+\tVIRTCHNL_OP_SYNCE_GET_OUTPUT_PIN_CFG = 122,\n+\tVIRTCHNL_OP_SYNCE_SET_OUTPUT_PIN_CFG = 123,\n+\tVIRTCHNL_OP_SYNCE_GET_CGU_ABILITIES = 124,\n+\tVIRTCHNL_OP_SYNCE_GET_CGU_DPLL_STATUS = 125,\n+\tVIRTCHNL_OP_SYNCE_SET_CGU_DPLL_CONFIG = 126,\n+\tVIRTCHNL_OP_SYNCE_GET_CGU_INFO = 127,\n+\tVIRTCHNL_OP_SYNCE_GET_HW_INFO = 128,\n \tVIRTCHNL_OP_MAX,\n };\n \n@@ -294,6 +307,32 @@ static inline const char *virtchnl_op_str(enum virtchnl_ops v_opcode)\n \t\treturn \"VIRTCHNL_OP_1588_PTP_SET_PIN_CFG\";\n \tcase VIRTCHNL_OP_1588_PTP_EXT_TIMESTAMP:\n \t\treturn \"VIRTCHNL_OP_1588_PTP_EXT_TIMESTAMP\";\n+\tcase VIRTCHNL_OP_SYNCE_GET_PHY_REC_CLK_OUT:\n+\t\treturn \"VIRTCHNL_OP_SYNCE_GET_PHY_REC_CLK_OUT\";\n+\tcase VIRTCHNL_OP_SYNCE_SET_PHY_REC_CLK_OUT:\n+\t\treturn \"VIRTCHNL_OP_SYNCE_SET_PHY_REC_CLK_OUT\";\n+\tcase VIRTCHNL_OP_SYNCE_GET_CGU_REF_PRIO:\n+\t\treturn \"VIRTCHNL_OP_SYNCE_GET_CGU_REF_PRIO\";\n+\tcase VIRTCHNL_OP_SYNCE_SET_CGU_REF_PRIO:\n+\t\treturn \"VIRTCHNL_OP_SYNCE_SET_CGU_REF_PRIO\";\n+\tcase VIRTCHNL_OP_SYNCE_GET_INPUT_PIN_CFG:\n+\t\treturn \"VIRTCHNL_OP_SYNCE_GET_INPUT_PIN_CFG\";\n+\tcase VIRTCHNL_OP_SYNCE_SET_INPUT_PIN_CFG:\n+\t\treturn \"VIRTCHNL_OP_SYNCE_SET_INPUT_PIN_CFG\";\n+\tcase VIRTCHNL_OP_SYNCE_GET_OUTPUT_PIN_CFG:\n+\t\treturn \"VIRTCHNL_OP_SYNCE_GET_OUTPUT_PIN_CFG\";\n+\tcase VIRTCHNL_OP_SYNCE_SET_OUTPUT_PIN_CFG:\n+\t\treturn \"VIRTCHNL_OP_SYNCE_SET_OUTPUT_PIN_CFG\";\n+\tcase VIRTCHNL_OP_SYNCE_GET_CGU_ABILITIES:\n+\t\treturn \"VIRTCHNL_OP_SYNCE_GET_CGU_ABILITIES\";\n+\tcase VIRTCHNL_OP_SYNCE_GET_CGU_DPLL_STATUS:\n+\t\treturn \"VIRTCHNL_OP_SYNCE_GET_CGU_DPLL_STATUS\";\n+\tcase VIRTCHNL_OP_SYNCE_SET_CGU_DPLL_CONFIG:\n+\t\treturn \"VIRTCHNL_OP_SYNCE_SET_CGU_DPLL_CONFIG\";\n+\tcase VIRTCHNL_OP_SYNCE_GET_CGU_INFO:\n+\t\treturn \"VIRTCHNL_OP_SYNCE_GET_CGU_INFO\";\n+\tcase VIRTCHNL_OP_SYNCE_GET_HW_INFO:\n+\t\treturn \"VIRTCHNL_OP_SYNCE_GET_HW_INFO\";\n \tcase VIRTCHNL_OP_ENABLE_QUEUES_V2:\n \t\treturn \"VIRTCHNL_OP_ENABLE_QUEUES_V2\";\n \tcase VIRTCHNL_OP_DISABLE_QUEUES_V2:\n@@ -2065,6 +2104,19 @@ VIRTCHNL_CHECK_STRUCT_LEN(12, virtchnl_quanta_cfg);\n  *   VIRTCHNL_OP_1588_PTP_GET_PIN_CFGS\n  *   VIRTCHNL_OP_1588_PTP_SET_PIN_CFG\n  *   VIRTCHNL_OP_1588_PTP_EXT_TIMESTAMP\n+ *   VIRTCHNL_OP_SYNCE_GET_PHY_REC_CLK_OUT\n+ *   VIRTCHNL_OP_SYNCE_SET_PHY_REC_CLK_OUT\n+ *   VIRTCHNL_OP_SYNCE_GET_CGU_REF_PRIO\n+ *   VIRTCHNL_OP_SYNCE_SET_CGU_REF_PRIO\n+ *   VIRTCHNL_OP_SYNCE_GET_INPUT_PIN_CFG\n+ *   VIRTCHNL_OP_SYNCE_SET_INPUT_PIN_CFG\n+ *   VIRTCHNL_OP_SYNCE_GET_OUTPUT_PIN_CFG\n+ *   VIRTCHNL_OP_SYNCE_SET_OUTPUT_PIN_CFG\n+ *   VIRTCHNL_OP_SYNCE_GET_CGU_ABILITIES\n+ *   VIRTCHNL_OP_SYNCE_GET_CGU_DPLL_STATUS\n+ *   VIRTCHNL_OP_SYNCE_SET_CGU_DPLL_CONFIG\n+ *   VIRTCHNL_OP_SYNCE_GET_CGU_INFO\n+ *   VIRTCHNL_OP_SYNCE_GET_HW_INFO\n  *\n  * Support for offloading control of the device PTP hardware clock (PHC) is enabled\n  * by VIRTCHNL_VF_CAP_PTP. This capability allows a VF to request that PF\n@@ -2085,6 +2137,7 @@ VIRTCHNL_CHECK_STRUCT_LEN(12, virtchnl_quanta_cfg);\n #define VIRTCHNL_1588_PTP_CAP_WRITE_PHC\t\tBIT(3)\n #define VIRTCHNL_1588_PTP_CAP_PHC_REGS\t\tBIT(4)\n #define VIRTCHNL_1588_PTP_CAP_PIN_CFG\t\tBIT(5)\n+#define VIRTCHNL_1588_PTP_CAP_SYNCE\t\tBIT(6)\n \n /**\n  * virtchnl_phc_regs\n@@ -2222,6 +2275,11 @@ enum virtchnl_ptp_tstamp_format {\n  * input to timestamp external events, or as an output to cause a periodic\n  * signal output.\n  *\n+ * VIRTCHNL_1588_PTP_CAP_SYNCE indicates that the VF has access to SyncE related\n+ * capabilities. The first command the VF should issue is the\n+ * VIRTCHNL_OP_SYNCE_GET_HW_INFO. It returns to VF all required HW details\n+ * needed for further processing.\n+ *\n  * Note that in the future, additional capability flags may be added which\n  * indicate additional extended support. All fields marked as reserved by this\n  * header will be set to zero. VF implementations should verify this to ensure\n@@ -2600,6 +2658,494 @@ struct virtchnl_phc_ext_tstamp {\n \n VIRTCHNL_CHECK_STRUCT_LEN(24, virtchnl_phc_ext_tstamp);\n \n+/**\n+ * virtchnl_synce_get_phy_rec_clk_out\n+ * @phy_output: PHY reference clock output pin\n+ * @port_num: Port number\n+ * @flags: PHY flags\n+ * @rsvd: Reserved for future extension\n+ *\n+ * Structure sent with VIRTCHNL_OP_SYNCE_GET_PHY_REC_CLK_OUT. This command reads\n+ * the mapping of the Ethernet lanes to the recovered clocks. The request is\n+ * acceptable only when VF negotiated VIRTCHNL_1588_PTP_CAP_SYNCE capability\n+ * with PF.\n+ *\n+ * The VF driver sets phy_output to choose CGU pin. In response the PF driver\n+ * sends the same structure with the same opcode.\n+ *\n+ * The VF driver can also set port_num to 0xFF to check if the PHY output is\n+ * driven by the PF that sends that command.\n+ *\n+ * If the Admin Queue command returns an error the PF will return\n+ * VIRTCHNL_STATUS_ERR_ADMIN_QUEUE_ERROR with unchanged structure to VF.\n+ */\n+struct virtchnl_synce_get_phy_rec_clk_out {\n+\tu8 phy_output;\n+\tu8 port_num;\n+#define VIRTCHNL_GET_PHY_REC_CLK_OUT_CURR_PORT\t0xFF\n+\tu8 flags;\n+#define VIRTCHNL_GET_PHY_REC_CLK_OUT_OUT_EN\tBIT(0)\n+\tu8 rsvd[13];\n+};\n+\n+VIRTCHNL_CHECK_STRUCT_LEN(16, virtchnl_synce_get_phy_rec_clk_out);\n+\n+/**\n+ * virtchnl_synce_set_phy_rec_clk_out\n+ * @phy_output: PHY reference clock output pin\n+ * @enable: GPIO state to be applied\n+ * @rsvd: Reserved for future extension\n+ *\n+ * Structure sent with VIRTCHNL_OP_SYNCE_SET_PHY_REC_CLK_OUT. The command maps\n+ * any of the four Ethernet lanes (PHY Port number) onto the two recovered\n+ * clocks (Phy output). The request is acceptable only when VF negotiated\n+ * VIRTCHNL_1588_PTP_CAP_SYNCE capability with PF.\n+ *\n+ * The VF driver specifies either SCL or SDA pin in phy_output and whether to\n+ * enable(1) or disable(0) the given pin in enable variable.\n+ * In response the PF driver sends back the same structure with the same opcode.\n+ *\n+ * If the Admin Queue command returns an error the PF will return\n+ * VIRTCHNL_STATUS_ERR_ADMIN_QUEUE_ERROR with unchanged structure to VF.\n+ */\n+struct virtchnl_synce_set_phy_rec_clk_out {\n+\tu8 phy_output;\n+\tu8 enable;\n+\tu8 rsvd[14];\n+};\n+\n+VIRTCHNL_CHECK_STRUCT_LEN(16, virtchnl_synce_set_phy_rec_clk_out);\n+\n+/**\n+ * virtchnl_synce_get_cgu_ref_prio\n+ * @dpll_num: DPLL index\n+ * @ref_idx: Reference pin index\n+ * @ref_priority: Reference input priority\n+ * @rsvd: Reserved for future extension\n+ *\n+ * Structure sent with VIRTCHNL_OP_SYNCE_GET_CGU_REF_PRIO. The command reads\n+ * the currently configured priority of the selected reference clock for a given\n+ * DPLL block within a given Clock Controller (DPLL) node. The request is\n+ * acceptable only when VF negotiated VIRTCHNL_1588_PTP_CAP_SYNCE capability\n+ * with PF.\n+ *\n+ * The VF driver should set dpll_num and ref_idx to choose the pin for which\n+ * the ref_priority will be returned. In response the PF driver sends the same\n+ * structure with the same opcode with ref_priority filled.\n+ *\n+ * If the Admin Queue command returns an error the PF will return\n+ * VIRTCHNL_STATUS_ERR_ADMIN_QUEUE_ERROR with unchanged structure to VF.\n+ */\n+struct virtchnl_synce_get_cgu_ref_prio {\n+\tu8 dpll_num;\n+\tu8 ref_idx;\n+\tu8 ref_priority;\n+\tu8 rsvd[13];\n+};\n+\n+VIRTCHNL_CHECK_STRUCT_LEN(16, virtchnl_synce_get_cgu_ref_prio);\n+\n+/**\n+ * virtchnl_synce_set_cgu_ref_prio\n+ * @dpll_num: DPLL index\n+ * @ref_idx: Reference pin index\n+ * @ref_priority: Reference input priority\n+ * @rsvd: Reserved for future extension\n+ *\n+ * Structure sent with VIRTCHNL_OP_SYNCE_SET_CGU_REF_PRIO. The command\n+ * configures the priority of the selected Input Index within a given DPLL block\n+ * of CCU node. The request is acceptable only when VF negotiated\n+ * VIRTCHNL_1588_PTP_CAP_SYNCE capability with PF.\n+ *\n+ * The VF driver should set dpll_num and ref_idx to choose the pin and\n+ * ref_priority to be applied to given pin. In response the PF driver sends the\n+ * same structure with the same opcode.\n+ *\n+ * If the Admin Queue command returns an error the PF will return\n+ * VIRTCHNL_STATUS_ERR_ADMIN_QUEUE_ERROR with unchanged structure to VF.\n+ */\n+struct virtchnl_synce_set_cgu_ref_prio {\n+\tu8 dpll_num;\n+\tu8 ref_idx;\n+\tu8 ref_priority;\n+\tu8 rsvd[13];\n+};\n+\n+VIRTCHNL_CHECK_STRUCT_LEN(16, virtchnl_synce_set_cgu_ref_prio);\n+\n+/**\n+ * virtchnl_synce_get_input_pin_cfg\n+ * @freq: Frequency of the reference clock input\n+ * @phase_delay: Phase compensation for the reference clock input\n+ * @input_idx: CGU pin index\n+ * @status: Status flags\n+ * @type: Input type flags\n+ * @flags1: First set of flags\n+ * @flags2: Second set of flags\n+ * @rsvd: Reserved for future extension\n+ *\n+ * Structure sent with VIRTCHNL_OP_SYNCE_GET_INPUT_PIN_CFG. The command reads\n+ * the current configuration of the specified reference clock input of a given\n+ * Clock Controller (DPLL) node. The request is acceptable only when VF\n+ * negotiated VIRTCHNL_1588_PTP_CAP_SYNCE capability with PF.\n+ *\n+ * The VF driver should set input_idx to choose CGU pin for which the\n+ * configuration will be returned. In response the PF driver sends the same\n+ * structure with the same opcode with the remaining fields filled.\n+ *\n+ * If the Admin Queue command returns an error the PF will return\n+ * VIRTCHNL_STATUS_ERR_ADMIN_QUEUE_ERROR with unchanged structure to VF.\n+ */\n+struct virtchnl_synce_get_input_pin_cfg {\n+\tu32 freq;\n+\tu32 phase_delay;\n+\tu8 input_idx;\n+\tu8 status;\n+#define VIRTCHNL_GET_CGU_IN_CFG_STATUS_LOS\t\tBIT(0)\n+#define VIRTCHNL_GET_CGU_IN_CFG_STATUS_SCM_FAIL\t\tBIT(1)\n+#define VIRTCHNL_GET_CGU_IN_CFG_STATUS_CFM_FAIL\t\tBIT(2)\n+#define VIRTCHNL_GET_CGU_IN_CFG_STATUS_GST_FAIL\t\tBIT(3)\n+#define VIRTCHNL_GET_CGU_IN_CFG_STATUS_PFM_FAIL\t\tBIT(4)\n+#define VIRTCHNL_GET_CGU_IN_CFG_STATUS_ESYNC_FAIL\tBIT(6)\n+#define VIRTCHNL_GET_CGU_IN_CFG_STATUS_ESYNC_CAP\tBIT(7)\n+\tu8 type;\n+#define VIRTCHNL_GET_CGU_IN_CFG_TYPE_READ_ONLY\t\tBIT(0)\n+#define VIRTCHNL_GET_CGU_IN_CFG_TYPE_GPS\t\tBIT(4)\n+#define VIRTCHNL_GET_CGU_IN_CFG_TYPE_EXTERNAL\t\tBIT(5)\n+#define VIRTCHNL_GET_CGU_IN_CFG_TYPE_PHY\t\tBIT(6)\n+\tu8 flags1;\n+#define VIRTCHNL_GET_CGU_IN_CFG_FLG1_PHASE_DELAY_SUPP\tBIT(0)\n+#define VIRTCHNL_GET_CGU_IN_CFG_FLG1_1PPS_SUPP\t\tBIT(2)\n+#define VIRTCHNL_GET_CGU_IN_CFG_FLG1_10MHZ_SUPP\t\tBIT(3)\n+#define VIRTCHNL_GET_CGU_IN_CFG_FLG1_ANYFREQ\t\tBIT(7)\n+\tu8 flags2;\n+#define VIRTCHNL_GET_CGU_IN_CFG_FLG2_INPUT_EN\t\tBIT(5)\n+#define VIRTCHNL_GET_CGU_IN_CFG_FLG2_ESYNC_EN\t\tBIT(6)\n+\tu8 rsvd[3];\n+};\n+\n+VIRTCHNL_CHECK_STRUCT_LEN(16, virtchnl_synce_get_input_pin_cfg);\n+\n+/**\n+ * virtchnl_synce_set_input_pin_cfg\n+ * @freq: Frequency of the reference clock input\n+ * @phase_delay: Phase compensation for the reference clock input\n+ * @input_idx: CGU pin index\n+ * @flags1: First set of flags\n+ * @flags2: Second set of flags\n+ * @rsvd: Reserved for future extension\n+ *\n+ * Structure sent with VIRTCHNL_OP_SYNCE_SET_INPUT_PIN_CFG. The command\n+ * configures the specified reference clock input of a given Clock Controller\n+ * (DPLL) node. The request is acceptable only when VF negotiated\n+ * VIRTCHNL_1588_PTP_CAP_SYNCE capability with PF.\n+ *\n+ * The VF driver should set input_idx to choose CGU pin and the rest of fields\n+ * according to the required configuration. In response the PF driver sends the\n+ * same structure with the same opcode.\n+ *\n+ * If the Admin Queue command returns an error the PF will return\n+ * VIRTCHNL_STATUS_ERR_ADMIN_QUEUE_ERROR with unchanged structure to VF.\n+ */\n+struct virtchnl_synce_set_input_pin_cfg {\n+\tu32 freq;\n+\tu32 phase_delay;\n+\tu8 input_idx;\n+\tu8 flags1;\n+#define VIRTCHNL_SET_CGU_IN_CFG_FLG1_UPDATE_FREQ\tBIT(6)\n+#define VIRTCHNL_SET_CGU_IN_CFG_FLG1_UPDATE_DELAY\tBIT(7)\n+\tu8 flags2;\n+#define VIRTCHNL_SET_CGU_IN_CFG_FLG2_INPUT_EN\t\tBIT(5)\n+#define VIRTCHNL_SET_CGU_IN_CFG_FLG2_ESYNC_EN\t\tBIT(6)\n+\tu8 rsvd[5];\n+};\n+\n+VIRTCHNL_CHECK_STRUCT_LEN(16, virtchnl_synce_set_input_pin_cfg);\n+\n+/**\n+ * virtchnl_synce_get_output_pin_cfg\n+ * @freq: Output frequency\n+ * @src_freq: Source frequency\n+ * @output_idx: Output pin index\n+ * @flags: Output flags\n+ * @src_sel: Internal DPLL source\n+ * @rsvd: Reserved for future extension\n+ *\n+ * Structure sent with VIRTCHNL_OP_SYNCE_GET_OUTPUT_PIN_CFG. The command reads\n+ * the current frequency, phase compensation and embedded sync configuration\n+ * of the specified clock output of a given Clock Controller (DPLL) node.\n+ * The request is acceptable only when VF negotiated\n+ * VIRTCHNL_1588_PTP_CAP_SYNCE capability with PF.\n+ *\n+ * The VF driver should set output_idx to choose CGU pin and the rest of fields\n+ * according to the required configuration. In response the PF driver sends the\n+ * same structure with the same opcode.\n+ *\n+ * If the Admin Queue command returns an error the PF will return\n+ * VIRTCHNL_STATUS_ERR_ADMIN_QUEUE_ERROR with unchanged structure to VF.\n+ */\n+struct virtchnl_synce_get_output_pin_cfg {\n+\tu32 freq;\n+\tu32 src_freq;\n+\tu8 output_idx;\n+\tu8 flags;\n+#define VIRTCHNL_GET_CGU_OUT_CFG_OUT_EN\t\tBIT(0)\n+#define VIRTCHNL_GET_CGU_OUT_CFG_ESYNC_EN\tBIT(1)\n+#define VIRTCHNL_GET_CGU_OUT_CFG_ESYNC_ABILITY\tBIT(2)\n+\tu8 src_sel;\n+#define VIRTCHNL_GET_CGU_OUT_CFG_DPLL_SRC_SEL_SHIFT\t0\n+#define VIRTCHNL_GET_CGU_OUT_CFG_DPLL_SRC_SEL \\\n+\t(0x1F << VIRTCHNL_GET_CGU_OUT_CFG_DPLL_SRC_SEL_SHIFT)\n+#define VIRTCHNL_GET_CGU_OUT_CFG_DPLL_MODE_SHIFT\t5\n+#define VIRTCHNL_GET_CGU_OUT_CFG_DPLL_MODE \\\n+\t(0x7 << VIRTCHNL_GET_CGU_OUT_CFG_DPLL_MODE_SHIFT)\n+\tu8 rsvd[5];\n+};\n+\n+VIRTCHNL_CHECK_STRUCT_LEN(16, virtchnl_synce_get_output_pin_cfg);\n+\n+/**\n+ * virtchnl_synce_set_output_pin_cfg\n+ * @freq: Output frequency\n+ * @phase_delay: Output phase compensation\n+ * @output_idx: Output pin index\n+ * @flags: Output flags\n+ * @src_sel: Internal DPLL source\n+ * @rsvd: Reserved for future extension\n+ *\n+ * Structure sent with VIRTCHNL_OP_SYNCE_SET_OUTPUT_PIN_CFG. The command\n+ * configures the specified reference clock input of a given Clock Controller\n+ * (DPLL) node. The request is acceptable only when VF negotiated\n+ * VIRTCHNL_1588_PTP_CAP_SYNCE capability with PF.\n+ *\n+ * The VF driver should set output_idx to choose CGU pin and the rest of fields\n+ * according to the required configuration. In response the PF driver sends the\n+ * same structure with the same opcode.\n+ *\n+ * If the Admin Queue command returns an error the PF will return\n+ * VIRTCHNL_STATUS_ERR_ADMIN_QUEUE_ERROR with unchanged structure to VF.\n+ */\n+struct virtchnl_synce_set_output_pin_cfg {\n+\tu32 freq;\n+\tu32 phase_delay;\n+\tu8 output_idx;\n+\tu8 flags;\n+#define VIRTCHNL_SET_CGU_OUT_CFG_OUT_EN\t\tBIT(0)\n+#define VIRTCHNL_SET_CGU_OUT_CFG_ESYNC_EN\tBIT(1)\n+#define VIRTCHNL_SET_CGU_OUT_CFG_UPDATE_FREQ\tBIT(2)\n+#define VIRTCHNL_SET_CGU_OUT_CFG_UPDATE_PHASE\tBIT(3)\n+#define VIRTCHNL_SET_CGU_OUT_CFG_UPDATE_SRC_SEL\tBIT(4)\n+\tu8 src_sel;\n+#define VIRTCHNL_SET_CGU_OUT_CFG_DPLL_SRC_SEL\t0x1F\n+\tu8 rsvd[5];\n+};\n+\n+VIRTCHNL_CHECK_STRUCT_LEN(16, virtchnl_synce_set_output_pin_cfg);\n+\n+/**\n+ * virtchnl_synce_get_cgu_abilities\n+ * @num_inputs: Number of Clock Controller inputs\n+ * @num_outputs: Number of Clock Controller outputs\n+ * @pps_dpll_idx: The index of a PPS DPLL block in the CCU\n+ * @synce_dpll_idx: The index of a SyncE DPLL block in the CCU\n+ * @max_in_freq: Maximum Input Frequency\n+ * @max_in_phase_adj: Maximum Input Phase Adjustment\n+ * @max_out_freq: Maximum Output Frequency\n+ * @max_out_phase_adj: Maximum Output Phase Adjustment\n+ * @cgu_part_num: Clock Controller Part Number\n+ * @rsvd: Reserved for future extension\n+ *\n+ * Structure sent with VIRTCHNL_OP_SYNCE_GET_CGU_ABILITIES. The command reads\n+ * the capabilities of the CC. If the value is not defined or cannot be\n+ * evaluated, then it shall be 0xFF for 8-bit fields and 0xFFFFFFFF for 32-bit\n+ * fields. The request is acceptable only when VF negotiated\n+ * VIRTCHNL_1588_PTP_CAP_SYNCE capability with PF.\n+ *\n+ * The VF driver sends an empty message to the PF driver. In response the PF\n+ * driver sends the virtchnl_synce_get_cgu_abilities structure.\n+ *\n+ * If the Admin Queue command returns an error the PF will return\n+ * VIRTCHNL_STATUS_ERR_ADMIN_QUEUE_ERROR with unchanged structure to VF.\n+ */\n+struct virtchnl_synce_get_cgu_abilities {\n+\tu8 num_inputs;\n+\tu8 num_outputs;\n+\tu8 pps_dpll_idx;\n+\tu8 synce_dpll_idx;\n+\tu32 max_in_freq;\n+\tu32 max_in_phase_adj;\n+\tu32 max_out_freq;\n+\tu32 max_out_phase_adj;\n+\tu8 cgu_part_num;\n+\tu8 rsvd[3];\n+};\n+\n+VIRTCHNL_CHECK_STRUCT_LEN(24, virtchnl_synce_get_cgu_abilities);\n+\n+/**\n+ * virtchnl_synce_get_cgu_dpll_status\n+ * @phase_offset: Phase offset in ns\n+ * @dpll_state: DPLL state\n+ * @dpll_num: DPLL index\n+ * @ref_state: Reference clock state\n+ * @eec_mode: EEC Mode - The configured clock quality level\n+ * @rsvd: Reserved for future extension\n+ *\n+ * Structure sent with VIRTCHNL_OP_SYNCE_GET_CGU_DPLL_STATUS. The command reads\n+ * the selected DPLL block status within the selected CCU node. The request is\n+ * acceptable only when VF negotiated VIRTCHNL_1588_PTP_CAP_SYNCE capability\n+ * with PF.\n+ *\n+ * The VF driver chooses in dpll_num which DPLL block it wants to read.\n+ * In response the PF driver fills the remaining fields in structure and sends\n+ * to VF with the same opcode.\n+ *\n+ * If the Admin Queue command returns an error the PF will return\n+ * VIRTCHNL_STATUS_ERR_ADMIN_QUEUE_ERROR with unchanged structure to VF.\n+ */\n+struct virtchnl_synce_get_cgu_dpll_status {\n+\ts64 phase_offset;\n+\tu16 dpll_state;\n+#define VIRTCHNL_GET_CGU_DPLL_STATUS_STATE_LOCK\t\t\tBIT(0)\n+#define VIRTCHNL_GET_CGU_DPLL_STATUS_STATE_HO\t\t\tBIT(1)\n+#define VIRTCHNL_GET_CGU_DPLL_STATUS_STATE_HO_READY\t\tBIT(2)\n+#define VIRTCHNL_GET_CGU_DPLL_STATUS_STATE_FLHIT\t\tBIT(5)\n+#define VIRTCHNL_GET_CGU_DPLL_STATUS_STATE_PSLHIT\t\tBIT(7)\n+#define VIRTCHNL_GET_CGU_DPLL_STATUS_STATE_CLK_REF_SHIFT\t8\n+#define VIRTCHNL_GET_CGU_DPLL_STATUS_STATE_CLK_REF_SEL\t\\\n+\t(0x1F << VIRTCHNL_GET_CGU_DPLL_STATUS_STATE_CLK_REF_SHIFT)\n+#define VIRTCHNL_GET_CGU_DPLL_STATUS_STATE_MODE_SHIFT\t\t13\n+#define VIRTCHNL_GET_CGU_DPLL_STATUS_STATE_MODE \\\n+\t(0x7 << VIRTCHNL_GET_CGU_DPLL_STATUS_STATE_MODE_SHIFT)\n+\tu8 dpll_num;\n+\tu8 ref_state;\n+#define VIRTCHNL_GET_CGU_DPLL_STATUS_REF_SW_LOS\t\t\tBIT(0)\n+#define VIRTCHNL_GET_CGU_DPLL_STATUS_REF_SW_SCM\t\t\tBIT(1)\n+#define VIRTCHNL_GET_CGU_DPLL_STATUS_REF_SW_CFM\t\t\tBIT(2)\n+#define VIRTCHNL_GET_CGU_DPLL_STATUS_REF_SW_GST\t\t\tBIT(3)\n+#define VIRTCHNL_GET_CGU_DPLL_STATUS_REF_SW_PFM\t\t\tBIT(4)\n+#define VIRTCHNL_GET_CGU_DPLL_STATUS_FAST_LOCK_EN\t\tBIT(5)\n+#define VIRTCHNL_GET_CGU_DPLL_STATUS_REF_SW_ESYNC\t\tBIT(6)\n+\tu8 eec_mode;\n+#define VIRTCHNL_GET_CGU_DPLL_STATUS_EEC_MODE_1\t\t\t0xA\n+#define VIRTCHNL_GET_CGU_DPLL_STATUS_EEC_MODE_2\t\t\t0xB\n+#define VIRTCHNL_GET_CGU_DPLL_STATUS_EEC_MODE_UNKNOWN\t\t0xF\n+\tu8 rsvd[11];\n+};\n+\n+VIRTCHNL_CHECK_STRUCT_LEN(24, virtchnl_synce_get_cgu_dpll_status);\n+\n+/**\n+ * virtchnl_synce_set_cgu_dpll_config\n+ * @dpll_num: DPLL index\n+ * @ref_state: Reference clock state\n+ * @config: DPLL config\n+ * @eec_mode: EEC Mode - The configured clock quality level\n+ * @rsvd: Reserved for future extension\n+ *\n+ * Structure sent with VIRTCHNL_OP_SYNCE_SET_CGU_DPLL_CONFIG. The command\n+ * configures the selected DPLL block within the selected CCU node. The request\n+ * is acceptable only when VF negotiated VIRTCHNL_1588_PTP_CAP_SYNCE\n+ * capability with PF.\n+ *\n+ * The VF driver chooses in dpll_num which DPLL block it wants to configure.\n+ * The PF driver applies the given configuration and returns unchanged structure\n+ * to the VF.\n+ *\n+ * If the Admin Queue command returns an error the PF will return\n+ * VIRTCHNL_STATUS_ERR_ADMIN_QUEUE_ERROR with unchanged structure to VF.\n+ */\n+struct virtchnl_synce_set_cgu_dpll_config {\n+\tu8 dpll_num;\n+\tu8 ref_state;\n+#define VIRTCHNL_SET_CGU_DPLL_CONFIG_REF_SW_LOS\t\tBIT(0)\n+#define VIRTCHNL_SET_CGU_DPLL_CONFIG_REF_SW_SCM\t\tBIT(1)\n+#define VIRTCHNL_SET_CGU_DPLL_CONFIG_REF_SW_CFM\t\tBIT(2)\n+#define VIRTCHNL_SET_CGU_DPLL_CONFIG_REF_SW_GST\t\tBIT(3)\n+#define VIRTCHNL_SET_CGU_DPLL_CONFIG_REF_SW_PFM\t\tBIT(4)\n+#define VIRTCHNL_SET_CGU_DPLL_CONFIG_REF_FLOCK_EN\tBIT(5)\n+#define VIRTCHNL_SET_CGU_DPLL_CONFIG_REF_SW_ESYNC\tBIT(6)\n+\tu8 config;\n+#define VIRTCHNL_SET_CGU_DPLL_CONFIG_CLK_REF_SEL\t0x1F\n+#define VIRTCHNL_SET_CGU_DPLL_CONFIG_MODE\t\t(0x7 << 5)\n+\tu8 eec_mode;\n+\tu8 rsvd[12];\n+};\n+\n+VIRTCHNL_CHECK_STRUCT_LEN(16, virtchnl_synce_set_cgu_dpll_config);\n+\n+/**\n+ * virtchnl_synce_get_cgu_info\n+ * @cgu_id: CGU ID\n+ * @cgu_cfg_ver: CGU config version\n+ * @cgu_fw_ver: CGU firmware version\n+ * @rsvd: Reserved for future extension\n+ *\n+ * Structure sent with VIRTCHNL_OP_SYNCE_GET_CGU_INFO. The command retrieves\n+ * information about CCU. If parameter is unsupported, then it should contain\n+ * 0xFFFFFFFF for 32-bit values or 0xFF for 8-bit values. The request is\n+ * acceptable only when VF negotiated VIRTCHNL_1588_PTP_CAP_SYNCE capability\n+ * with PF.\n+ *\n+ * The VF driver sends an empty message to the PF driver. In response the PF\n+ * driver sends the virtchnl_synce_get_cgu_info structure.\n+ *\n+ * If the Admin Queue command returns an error the PF will return\n+ * VIRTCHNL_STATUS_ERR_ADMIN_QUEUE_ERROR with unchanged structure to VF.\n+ */\n+struct virtchnl_synce_get_cgu_info {\n+\tu32 cgu_id;\n+\tu32 cgu_cfg_ver;\n+\tu32 cgu_fw_ver;\n+\tu8 rsvd[4];\n+};\n+\n+VIRTCHNL_CHECK_STRUCT_LEN(16, virtchnl_synce_get_cgu_info);\n+\n+/**\n+ * virtchnl_cgu_pin\n+ * @pin_index: Pin index to use in all functions\n+ * @name: Human readable pin name\n+ *\n+ * Structure used as a part of VIRTCHNL_OP_SYNCE_GET_HW_INFO request.\n+ * The VF issues a VIRTCHNL_OP_SYNCE_GET_HW_INFO request to the PF in\n+ * order to obtain the list of available CGU pins.\n+ */\n+struct virtchnl_cgu_pin {\n+\tu8 pin_index;\n+\tchar name[63];\n+};\n+\n+VIRTCHNL_CHECK_STRUCT_LEN(64, virtchnl_cgu_pin);\n+\n+/**\n+ * virtchnl_synce_get_hw_info\n+ * @cgu_present: True if CGU is present\n+ * @rclk_present: True is PHY recovered clock is present\n+ * @c827_idx: C827 index for the current port\n+ * @len: Length of the variable CGU pins array\n+ * @rsvd: Reserved for future extension\n+ * @pins: Variable length CGU pins array\n+ *\n+ * Variable structure sent by the PF in reply to VIRTCHNL_OP_SYNCE_GET_HW_INFO.\n+ * The VF does not send this structure with its request of the operation.\n+ * The request is acceptable only when VF negotiated\n+ * VIRTCHNL_1588_PTP_CAP_SYNCE capability with PF.\n+ *\n+ * If this opcode returns error status the VF should assume it does not have\n+ * access to any other SyncE commands.\n+ */\n+struct virtchnl_synce_get_hw_info {\n+\tu8 cgu_present;\n+\tu8 rclk_present;\n+\tu8 c827_idx;\n+\tu8 len;\n+\tu8 rsvd[4];\n+\tstruct virtchnl_cgu_pin pins[1];\n+};\n+\n+VIRTCHNL_CHECK_STRUCT_LEN(72, virtchnl_synce_get_hw_info);\n+\n /* Since VF messages are limited by u16 size, precalculate the maximum possible\n  * values of nested elements in virtchnl structures that virtual channel can\n  * possibly handle in a single message.\n@@ -2918,6 +3464,42 @@ virtchnl_vc_validate_vf_msg(struct virtchnl_version_info *ver, u32 v_opcode,\n \tcase VIRTCHNL_OP_1588_PTP_EXT_TIMESTAMP:\n \t\tvalid_len = sizeof(struct virtchnl_phc_ext_tstamp);\n \t\tbreak;\n+\tcase VIRTCHNL_OP_SYNCE_GET_PHY_REC_CLK_OUT:\n+\t\tvalid_len = sizeof(struct virtchnl_synce_get_phy_rec_clk_out);\n+\t\tbreak;\n+\tcase VIRTCHNL_OP_SYNCE_SET_PHY_REC_CLK_OUT:\n+\t\tvalid_len = sizeof(struct virtchnl_synce_set_phy_rec_clk_out);\n+\t\tbreak;\n+\tcase VIRTCHNL_OP_SYNCE_GET_CGU_REF_PRIO:\n+\t\tvalid_len = sizeof(struct virtchnl_synce_get_cgu_ref_prio);\n+\t\tbreak;\n+\tcase VIRTCHNL_OP_SYNCE_SET_CGU_REF_PRIO:\n+\t\tvalid_len = sizeof(struct virtchnl_synce_set_cgu_ref_prio);\n+\t\tbreak;\n+\tcase VIRTCHNL_OP_SYNCE_GET_INPUT_PIN_CFG:\n+\t\tvalid_len = sizeof(struct virtchnl_synce_get_input_pin_cfg);\n+\t\tbreak;\n+\tcase VIRTCHNL_OP_SYNCE_SET_INPUT_PIN_CFG:\n+\t\tvalid_len = sizeof(struct virtchnl_synce_set_input_pin_cfg);\n+\t\tbreak;\n+\tcase VIRTCHNL_OP_SYNCE_GET_OUTPUT_PIN_CFG:\n+\t\tvalid_len = sizeof(struct virtchnl_synce_get_output_pin_cfg);\n+\t\tbreak;\n+\tcase VIRTCHNL_OP_SYNCE_SET_OUTPUT_PIN_CFG:\n+\t\tvalid_len = sizeof(struct virtchnl_synce_set_output_pin_cfg);\n+\t\tbreak;\n+\tcase VIRTCHNL_OP_SYNCE_GET_CGU_ABILITIES:\n+\t\tbreak;\n+\tcase VIRTCHNL_OP_SYNCE_GET_CGU_DPLL_STATUS:\n+\t\tvalid_len = sizeof(struct virtchnl_synce_get_cgu_dpll_status);\n+\t\tbreak;\n+\tcase VIRTCHNL_OP_SYNCE_SET_CGU_DPLL_CONFIG:\n+\t\tvalid_len = sizeof(struct virtchnl_synce_set_cgu_dpll_config);\n+\t\tbreak;\n+\tcase VIRTCHNL_OP_SYNCE_GET_CGU_INFO:\n+\t\tbreak;\n+\tcase VIRTCHNL_OP_SYNCE_GET_HW_INFO:\n+\t\tbreak;\n \tcase VIRTCHNL_OP_ENABLE_QUEUES_V2:\n \tcase VIRTCHNL_OP_DISABLE_QUEUES_V2:\n \t\tvalid_len = sizeof(struct virtchnl_del_ena_dis_queues);\n",
    "prefixes": [
        "12/18"
    ]
}