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GET /api/patches/125952/?format=api
{ "id": 125952, "url": "http://patches.dpdk.org/api/patches/125952/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20230412064948.3352867-1-zhichaox.zeng@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20230412064948.3352867-1-zhichaox.zeng@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20230412064948.3352867-1-zhichaox.zeng@intel.com", "date": "2023-04-12T06:49:48", "name": "[v2,2/3] net/iavf: support Rx timestamp offload on AVX2", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "e0208e4ad441efd7da1ddd000f83046c566b78c8", "submitter": { "id": 2644, "url": "http://patches.dpdk.org/api/people/2644/?format=api", "name": "Zhichao Zeng", "email": "zhichaox.zeng@intel.com" }, "delegate": { "id": 1540, "url": "http://patches.dpdk.org/api/users/1540/?format=api", "username": "qzhan15", "first_name": "Qi", "last_name": "Zhang", "email": "qi.z.zhang@intel.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20230412064948.3352867-1-zhichaox.zeng@intel.com/mbox/", "series": [ { "id": 27668, "url": "http://patches.dpdk.org/api/series/27668/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=27668", "date": "2023-04-12T06:48:33", "name": "Enable iavf Rx Timestamp offload on vector path", "version": 2, "mbox": "http://patches.dpdk.org/series/27668/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/125952/comments/", "check": "warning", "checks": "http://patches.dpdk.org/api/patches/125952/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id EAF3B42923;\n\tWed, 12 Apr 2023 08:44:37 +0200 (CEST)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id D9AAF40FAE;\n\tWed, 12 Apr 2023 08:44:37 +0200 (CEST)", "from mga05.intel.com (mga05.intel.com [192.55.52.43])\n by mails.dpdk.org (Postfix) with ESMTP id 2D4664067B\n for <dev@dpdk.org>; Wed, 12 Apr 2023 08:44:36 +0200 (CEST)", "from orsmga005.jf.intel.com ([10.7.209.41])\n by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 11 Apr 2023 23:44:35 -0700", "from unknown (HELO localhost.localdomain) ([10.239.252.103])\n by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 11 Apr 2023 23:44:31 -0700" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1681281876; x=1712817876;\n h=from:to:cc:subject:date:message-id:in-reply-to:\n references:mime-version:content-transfer-encoding;\n bh=BPfnWUlPEKwQz6brIGMIyngqRR4HVwfvytLJYkZcm2E=;\n b=bMpkE2aqe1Jn+HM8e7gSHvAMN/Gemx/f7vKp70UiLeSD761xHawIKLDq\n 3EMH87jHKxQ1FuafhVzLVxDACpUFwBhNr04U6tIL27PHhmMEcjLkkw/9D\n Rh+V9Mf5zAYQ+NgWSFv+tDMwJFN/UdT/dGMK4mwwN2I26EZdZon8lzxuJ\n vpWYTdnA69kLnVZZKZi8E6NQpFad1ZsLCBvhYY8BzudjYM/V3K7Z09bIB\n Y3WVHE8COE8BsJfZjsiGgFdV4VGIBhTi8lSvAc0jwH3KC6flp3W55PJOv\n qhLelVi9t0OFo679PqASiKZRiydXvq6OJCE0rwMVssWZeZYbReaFk4l5t A==;", "X-IronPort-AV": [ "E=McAfee;i=\"6600,9927,10677\"; a=\"430102955\"", "E=Sophos;i=\"5.98,338,1673942400\"; d=\"scan'208\";a=\"430102955\"", "E=McAfee;i=\"6600,9927,10677\"; a=\"863187501\"", "E=Sophos;i=\"5.98,338,1673942400\"; d=\"scan'208\";a=\"863187501\"" ], "X-ExtLoop1": "1", "From": "Zhichao Zeng <zhichaox.zeng@intel.com>", "To": "dev@dpdk.org", "Cc": "qi.z.zhang@intel.com, yaqi.tang@intel.com, yingyax.han@intel.com,\n Zhichao Zeng <zhichaox.zeng@intel.com>,\n Bruce Richardson <bruce.richardson@intel.com>,\n Konstantin Ananyev <konstantin.v.ananyev@yandex.ru>,\n Jingjing Wu <jingjing.wu@intel.com>, Beilei Xing <beilei.xing@intel.com>", "Subject": "[PATCH v2 2/3] net/iavf: support Rx timestamp offload on AVX2", "Date": "Wed, 12 Apr 2023 14:49:48 +0800", "Message-Id": "<20230412064948.3352867-1-zhichaox.zeng@intel.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20230410073621.2493087-1-zhichaox.zeng@intel.com>", "References": "<20230410073621.2493087-1-zhichaox.zeng@intel.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "This patch enables Rx timestamp offload on AVX2 data path.\n\nEnable timestamp offload with the command '--enable-rx-timestamp',\npay attention that getting Rx timestamp offload will drop the performance.\n\nSigned-off-by: Zhichao Zeng <zhichaox.zeng@intel.com>\n\n---\nv2: fix compile warning\n---\n drivers/net/iavf/iavf_rxtx_vec_avx2.c | 193 +++++++++++++++++++++++++-\n 1 file changed, 187 insertions(+), 6 deletions(-)", "diff": "diff --git a/drivers/net/iavf/iavf_rxtx_vec_avx2.c b/drivers/net/iavf/iavf_rxtx_vec_avx2.c\nindex b4ebac9d34..affa44a2b1 100644\n--- a/drivers/net/iavf/iavf_rxtx_vec_avx2.c\n+++ b/drivers/net/iavf/iavf_rxtx_vec_avx2.c\n@@ -553,6 +553,22 @@ _iavf_recv_raw_pkts_vec_avx2_flex_rxd(struct iavf_rx_queue *rxq,\n \t\t\trte_cpu_to_le_32(1 << IAVF_RX_FLEX_DESC_STATUS0_DD_S)))\n \t\treturn 0;\n \n+#ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC\n+\tbool is_tsinit = false;\n+\tuint8_t inflection_point = 0;\n+\t__m256i hw_low_last;\n+\tif (rxq->offloads & RTE_ETH_RX_OFFLOAD_TIMESTAMP) {\n+\t\tuint64_t sw_cur_time = rte_get_timer_cycles() / (rte_get_timer_hz() / 1000);\n+\n+\t\tif (unlikely(sw_cur_time - rxq->hw_time_update > 4)) {\n+\t\t\thw_low_last = _mm256_setzero_si256();\n+\t\t\tis_tsinit = 1;\n+\t\t} else {\n+\t\t\thw_low_last = _mm256_set_epi32(0, 0, 0, 0, 0, 0, 0, rxq->phc_time);\n+\t\t}\n+\t}\n+#endif\n+\n \t/* constants used in processing loop */\n \tconst __m256i crc_adjust =\n \t\t_mm256_set_epi16\n@@ -957,11 +973,12 @@ _iavf_recv_raw_pkts_vec_avx2_flex_rxd(struct iavf_rx_queue *rxq,\n \n #ifndef RTE_LIBRTE_IAVF_16BYTE_RX_DESC\n \t\t/**\n-\t\t * needs to load 2nd 16B of each desc for RSS hash parsing,\n+\t\t * needs to load 2nd 16B of each desc,\n \t\t * will cause performance drop to get into this context.\n \t\t */\n-\t\tif (offloads & RTE_ETH_RX_OFFLOAD_RSS_HASH ||\n-\t\t rxq->rx_flags & IAVF_RX_FLAGS_VLAN_TAG_LOC_L2TAG2_2) {\n+\t\tif (offloads & (RTE_ETH_RX_OFFLOAD_RSS_HASH |\n+\t\t\t\t\tRTE_ETH_RX_OFFLOAD_TIMESTAMP) ||\n+\t\t\t\trxq->rx_flags & IAVF_RX_FLAGS_VLAN_TAG_LOC_L2TAG2_2) {\n \t\t\t/* load bottom half of every 32B desc */\n \t\t\tconst __m128i raw_desc_bh7 =\n \t\t\t\t_mm_load_si128\n@@ -1043,7 +1060,7 @@ _iavf_recv_raw_pkts_vec_avx2_flex_rxd(struct iavf_rx_queue *rxq,\n \t\t\t\tmb4_5 = _mm256_or_si256(mb4_5, rss_hash4_5);\n \t\t\t\tmb2_3 = _mm256_or_si256(mb2_3, rss_hash2_3);\n \t\t\t\tmb0_1 = _mm256_or_si256(mb0_1, rss_hash0_1);\n-\t\t\t}\n+\t\t\t} /* if() on RSS hash parsing */\n \n \t\t\tif (rxq->rx_flags & IAVF_RX_FLAGS_VLAN_TAG_LOC_L2TAG2_2) {\n \t\t\t\t/* merge the status/error-1 bits into one register */\n@@ -1122,8 +1139,121 @@ _iavf_recv_raw_pkts_vec_avx2_flex_rxd(struct iavf_rx_queue *rxq,\n \t\t\t\tmb4_5 = _mm256_or_si256(mb4_5, vlan_tci4_5);\n \t\t\t\tmb2_3 = _mm256_or_si256(mb2_3, vlan_tci2_3);\n \t\t\t\tmb0_1 = _mm256_or_si256(mb0_1, vlan_tci0_1);\n-\t\t\t}\n-\t\t} /* if() on RSS hash parsing */\n+\t\t\t} /* if() on Vlan parsing */\n+\n+\t\t\tif (rxq->offloads & RTE_ETH_RX_OFFLOAD_TIMESTAMP) {\n+\t\t\t\tuint32_t mask = 0xFFFFFFFF;\n+\t\t\t\t__m256i ts;\n+\t\t\t\t__m256i ts_low = _mm256_setzero_si256();\n+\t\t\t\t__m256i ts_low1;\n+\t\t\t\t__m256i ts_low2;\n+\t\t\t\t__m256i max_ret;\n+\t\t\t\t__m256i cmp_ret;\n+\t\t\t\tuint8_t ret = 0;\n+\t\t\t\tuint8_t shift = 8;\n+\t\t\t\t__m256i ts_desp_mask = _mm256_set_epi32(mask, 0, 0, 0, mask, 0, 0, 0);\n+\t\t\t\t__m256i cmp_mask = _mm256_set1_epi32(mask);\n+\t\t\t\t__m256i ts_permute_mask = _mm256_set_epi32(7, 3, 6, 2, 5, 1, 4, 0);\n+\n+\t\t\t\tts = _mm256_and_si256(raw_desc_bh0_1, ts_desp_mask);\n+\t\t\t\tts_low = _mm256_or_si256(ts_low, _mm256_srli_si256(ts, 3 * 4));\n+\t\t\t\tts = _mm256_and_si256(raw_desc_bh2_3, ts_desp_mask);\n+\t\t\t\tts_low = _mm256_or_si256(ts_low, _mm256_srli_si256(ts, 2 * 4));\n+\t\t\t\tts = _mm256_and_si256(raw_desc_bh4_5, ts_desp_mask);\n+\t\t\t\tts_low = _mm256_or_si256(ts_low, _mm256_srli_si256(ts, 4));\n+\t\t\t\tts = _mm256_and_si256(raw_desc_bh6_7, ts_desp_mask);\n+\t\t\t\tts_low = _mm256_or_si256(ts_low, ts);\n+\n+\t\t\t\tts_low1 = _mm256_permutevar8x32_epi32(ts_low, ts_permute_mask);\n+\t\t\t\tts_low2 = _mm256_permutevar8x32_epi32(ts_low1,\n+\t\t\t\t\t\t\t_mm256_set_epi32(6, 5, 4, 3, 2, 1, 0, 7));\n+\t\t\t\tts_low2 = _mm256_and_si256(ts_low2,\n+\t\t\t\t\t\t\t_mm256_set_epi32(mask, mask, mask, mask, mask, mask, mask, 0));\n+\t\t\t\tts_low2 = _mm256_or_si256(ts_low2, hw_low_last);\n+\t\t\t\thw_low_last = _mm256_and_si256(ts_low1,\n+\t\t\t\t\t\t\t_mm256_set_epi32(0, 0, 0, 0, 0, 0, 0, mask));\n+\n+\t\t\t\t*RTE_MBUF_DYNFIELD(rx_pkts[i + 0],\n+\t\t\t\t\tiavf_timestamp_dynfield_offset, uint32_t *) = _mm256_extract_epi32(ts_low1, 0);\n+\t\t\t\t*RTE_MBUF_DYNFIELD(rx_pkts[i + 1],\n+\t\t\t\t\tiavf_timestamp_dynfield_offset, uint32_t *) = _mm256_extract_epi32(ts_low1, 1);\n+\t\t\t\t*RTE_MBUF_DYNFIELD(rx_pkts[i + 2],\n+\t\t\t\t\tiavf_timestamp_dynfield_offset, uint32_t *) = _mm256_extract_epi32(ts_low1, 2);\n+\t\t\t\t*RTE_MBUF_DYNFIELD(rx_pkts[i + 3],\n+\t\t\t\t\tiavf_timestamp_dynfield_offset, uint32_t *) = _mm256_extract_epi32(ts_low1, 3);\n+\t\t\t\t*RTE_MBUF_DYNFIELD(rx_pkts[i + 4],\n+\t\t\t\t\tiavf_timestamp_dynfield_offset, uint32_t *) = _mm256_extract_epi32(ts_low1, 4);\n+\t\t\t\t*RTE_MBUF_DYNFIELD(rx_pkts[i + 5],\n+\t\t\t\t\tiavf_timestamp_dynfield_offset, uint32_t *) = _mm256_extract_epi32(ts_low1, 5);\n+\t\t\t\t*RTE_MBUF_DYNFIELD(rx_pkts[i + 6],\n+\t\t\t\t\tiavf_timestamp_dynfield_offset, uint32_t *) = _mm256_extract_epi32(ts_low1, 6);\n+\t\t\t\t*RTE_MBUF_DYNFIELD(rx_pkts[i + 7],\n+\t\t\t\t\tiavf_timestamp_dynfield_offset, uint32_t *) = _mm256_extract_epi32(ts_low1, 7);\n+\n+\t\t\t\tif (unlikely(is_tsinit)) {\n+\t\t\t\t\tuint32_t in_timestamp;\n+\t\t\t\t\tif (iavf_get_phc_time(rxq))\n+\t\t\t\t\t\tPMD_DRV_LOG(ERR, \"get physical time failed\");\n+\t\t\t\t\tin_timestamp = *RTE_MBUF_DYNFIELD(rx_pkts[i + 0],\n+\t\t\t\t\t\t\tiavf_timestamp_dynfield_offset, uint32_t *);\n+\t\t\t\t\trxq->phc_time = iavf_tstamp_convert_32b_64b(rxq->phc_time, in_timestamp);\n+\t\t\t\t}\n+\n+\t\t\t\t*RTE_MBUF_DYNFIELD(rx_pkts[i + 0],\n+\t\t\t\t\tiavf_timestamp_dynfield_offset + 4, uint32_t *) = (uint32_t)(rxq->phc_time >> 32);\n+\t\t\t\t*RTE_MBUF_DYNFIELD(rx_pkts[i + 1],\n+\t\t\t\t\tiavf_timestamp_dynfield_offset + 4, uint32_t *) = (uint32_t)(rxq->phc_time >> 32);\n+\t\t\t\t*RTE_MBUF_DYNFIELD(rx_pkts[i + 2],\n+\t\t\t\t\tiavf_timestamp_dynfield_offset + 4, uint32_t *) = (uint32_t)(rxq->phc_time >> 32);\n+\t\t\t\t*RTE_MBUF_DYNFIELD(rx_pkts[i + 3],\n+\t\t\t\t\tiavf_timestamp_dynfield_offset + 4, uint32_t *) = (uint32_t)(rxq->phc_time >> 32);\n+\t\t\t\t*RTE_MBUF_DYNFIELD(rx_pkts[i + 4],\n+\t\t\t\t\tiavf_timestamp_dynfield_offset + 4, uint32_t *) = (uint32_t)(rxq->phc_time >> 32);\n+\t\t\t\t*RTE_MBUF_DYNFIELD(rx_pkts[i + 5],\n+\t\t\t\t\tiavf_timestamp_dynfield_offset + 4, uint32_t *) = (uint32_t)(rxq->phc_time >> 32);\n+\t\t\t\t*RTE_MBUF_DYNFIELD(rx_pkts[i + 6],\n+\t\t\t\t\tiavf_timestamp_dynfield_offset + 4, uint32_t *) = (uint32_t)(rxq->phc_time >> 32);\n+\t\t\t\t*RTE_MBUF_DYNFIELD(rx_pkts[i + 7],\n+\t\t\t\t\tiavf_timestamp_dynfield_offset + 4, uint32_t *) = (uint32_t)(rxq->phc_time >> 32);\n+\n+\t\t\t\tmax_ret = _mm256_max_epu32(ts_low2, ts_low1);\n+\t\t\t\tcmp_ret = _mm256_andnot_si256(_mm256_cmpeq_epi32(max_ret, ts_low1), cmp_mask);\n+\n+\t\t\t\tif (_mm256_testz_si256(cmp_ret, cmp_mask)) {\n+\t\t\t\t\tinflection_point = 0;\n+\t\t\t\t} else {\n+\t\t\t\t\tinflection_point = 1;\n+\t\t\t\t\twhile (shift > 1) {\n+\t\t\t\t\t\tshift = shift >> 1;\n+\t\t\t\t\t\t__m256i mask_low;\n+\t\t\t\t\t\t__m256i mask_high;\n+\t\t\t\t\t\tswitch (shift) {\n+\t\t\t\t\t\tcase 4:\n+\t\t\t\t\t\t\tmask_low = _mm256_set_epi32(0, 0, 0, 0, mask, mask, mask, mask);\n+\t\t\t\t\t\t\tmask_high = _mm256_set_epi32(mask, mask, mask, mask, 0, 0, 0, 0);\n+\t\t\t\t\t\t\tbreak;\n+\t\t\t\t\t\tcase 2:\n+\t\t\t\t\t\t\tmask_low = _mm256_srli_si256(cmp_mask, 2 * 4);\n+\t\t\t\t\t\t\tmask_high = _mm256_slli_si256(cmp_mask, 2 * 4);\n+\t\t\t\t\t\t\tbreak;\n+\t\t\t\t\t\tcase 1:\n+\t\t\t\t\t\t\tmask_low = _mm256_srli_si256(cmp_mask, 1 * 4);\n+\t\t\t\t\t\t\tmask_high = _mm256_slli_si256(cmp_mask, 1 * 4);\n+\t\t\t\t\t\t\tbreak;\n+\t\t\t\t\t\t}\n+\t\t\t\t\t\tret = _mm256_testz_si256(cmp_ret, mask_low);\n+\t\t\t\t\t\tif (ret) {\n+\t\t\t\t\t\t\tret = _mm256_testz_si256(cmp_ret, mask_high);\n+\t\t\t\t\t\t\tinflection_point += ret ? 0 : shift;\n+\t\t\t\t\t\t\tcmp_mask = mask_high;\n+\t\t\t\t\t\t} else {\n+\t\t\t\t\t\t\tcmp_mask = mask_low;\n+\t\t\t\t\t\t}\n+\t\t\t\t\t}\n+\t\t\t\t}\n+\t\t\t\tmbuf_flags = _mm256_or_si256(mbuf_flags, _mm256_set1_epi32(iavf_timestamp_dynflag));\n+\t\t\t} /* if() on Timestamp parsing */\n+\t\t}\n #endif\n \n \t\t/**\n@@ -1254,10 +1384,61 @@ _iavf_recv_raw_pkts_vec_avx2_flex_rxd(struct iavf_rx_queue *rxq,\n \t\t\t\t(_mm_cvtsi128_si64\n \t\t\t\t\t(_mm256_castsi256_si128(status0_7)));\n \t\treceived += burst;\n+\n+#ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC\n+#pragma GCC diagnostic push\n+#pragma GCC diagnostic ignored \"-Wimplicit-fallthrough\"\n+\t\tif (rxq->offloads && (rxq->offloads & RTE_ETH_RX_OFFLOAD_TIMESTAMP)) {\n+\t\t\tinflection_point = (inflection_point <= burst) ? inflection_point : 0;\n+\t\t\tswitch (inflection_point) {\n+\t\t\tcase 1:\n+\t\t\t\t*RTE_MBUF_DYNFIELD(rx_pkts[i + 0],\n+\t\t\t\t\tiavf_timestamp_dynfield_offset + 4, uint32_t *) += 1;\n+\t\t\tcase 2:\n+\t\t\t\t*RTE_MBUF_DYNFIELD(rx_pkts[i + 1],\n+\t\t\t\t\tiavf_timestamp_dynfield_offset + 4, uint32_t *) += 1;\n+\t\t\tcase 3:\n+\t\t\t\t*RTE_MBUF_DYNFIELD(rx_pkts[i + 2],\n+\t\t\t\t\tiavf_timestamp_dynfield_offset + 4, uint32_t *) += 1;\n+\t\t\tcase 4:\n+\t\t\t\t*RTE_MBUF_DYNFIELD(rx_pkts[i + 3],\n+\t\t\t\t\tiavf_timestamp_dynfield_offset + 4, uint32_t *) += 1;\n+\t\t\tcase 5:\n+\t\t\t\t*RTE_MBUF_DYNFIELD(rx_pkts[i + 4],\n+\t\t\t\t\tiavf_timestamp_dynfield_offset + 4, uint32_t *) += 1;\n+\t\t\tcase 6:\n+\t\t\t\t*RTE_MBUF_DYNFIELD(rx_pkts[i + 5],\n+\t\t\t\t\tiavf_timestamp_dynfield_offset + 4, uint32_t *) += 1;\n+\t\t\tcase 7:\n+\t\t\t\t*RTE_MBUF_DYNFIELD(rx_pkts[i + 6],\n+\t\t\t\t\tiavf_timestamp_dynfield_offset + 4, uint32_t *) += 1;\n+\t\t\tcase 8:\n+\t\t\t\t*RTE_MBUF_DYNFIELD(rx_pkts[i + 7],\n+\t\t\t\t\tiavf_timestamp_dynfield_offset + 4, uint32_t *) += 1;\n+\t\t\t\trxq->phc_time += (uint64_t)1 << 32;\n+\t\t\tcase 0:\n+\t\t\t\tbreak;\n+\t\t\tdefault:\n+\t\t\t\tprintf(\"invalid inflection point for rx timestamp\\n\");\n+\t\t\t\tbreak;\n+\t\t\t}\n+\n+\t\t\trxq->hw_time_update = rte_get_timer_cycles() / (rte_get_timer_hz() / 1000);\n+\t\t}\n+#pragma GCC diagnostic pop\n+#endif\n+\n \t\tif (burst != IAVF_DESCS_PER_LOOP_AVX)\n \t\t\tbreak;\n \t}\n \n+#ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC\n+#ifdef IAVF_RX_TS_OFFLOAD\n+\tif (received > 0 && (rxq->offloads & RTE_ETH_RX_OFFLOAD_TIMESTAMP))\n+\t\trxq->phc_time = *RTE_MBUF_DYNFIELD(rx_pkts[received - 1], iavf_timestamp_dynfield_offset, rte_mbuf_timestamp_t *);\n+#endif\n+#endif\n+\n \t/* update tail pointers */\n \trxq->rx_tail += received;\n \trxq->rx_tail &= (rxq->nb_rx_desc - 1);\n", "prefixes": [ "v2", "2/3" ] }