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GET /api/patches/125926/?format=api
{ "id": 125926, "url": "http://patches.dpdk.org/api/patches/125926/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20230411091144.1087887-21-ndabilpuram@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20230411091144.1087887-21-ndabilpuram@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20230411091144.1087887-21-ndabilpuram@marvell.com", "date": "2023-04-11T09:11:44", "name": "[21/21] common/cnxk: support of 1:n pool:aura per NIX LF", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": true, "hash": "9bef735e0371a6fe2ebaa079209b220dc5e15aae", "submitter": { "id": 1202, "url": "http://patches.dpdk.org/api/people/1202/?format=api", "name": "Nithin Dabilpuram", "email": "ndabilpuram@marvell.com" }, "delegate": { "id": 310, "url": "http://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20230411091144.1087887-21-ndabilpuram@marvell.com/mbox/", "series": [ { "id": 27660, "url": "http://patches.dpdk.org/api/series/27660/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=27660", "date": "2023-04-11T09:11:24", "name": "[01/21] common/cnxk: allocate dynamic BPIDs", "version": 1, "mbox": "http://patches.dpdk.org/series/27660/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/125926/comments/", "check": "warning", "checks": "http://patches.dpdk.org/api/patches/125926/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id C97C44291B;\n\tTue, 11 Apr 2023 11:14:17 +0200 (CEST)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 1900F42D77;\n\tTue, 11 Apr 2023 11:13:07 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com\n [67.231.148.174])\n by mails.dpdk.org (Postfix) with ESMTP id 2254742BB1\n for <dev@dpdk.org>; Tue, 11 Apr 2023 11:13:05 +0200 (CEST)", "from pps.filterd (m0045849.ppops.net [127.0.0.1])\n by mx0a-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id\n 33B8UBiB021423 for <dev@dpdk.org>; Tue, 11 Apr 2023 02:13:05 -0700", "from dc5-exch01.marvell.com ([199.233.59.181])\n by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3pvt73b1x2-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Tue, 11 Apr 2023 02:13:05 -0700", "from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.48;\n Tue, 11 Apr 2023 02:13:03 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.48 via Frontend\n Transport; Tue, 11 Apr 2023 02:13:03 -0700", "from hyd1588t430.caveonetworks.com (unknown [10.29.52.204])\n by maili.marvell.com (Postfix) with ESMTP id 5390A3F706F;\n Tue, 11 Apr 2023 02:13:00 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-transfer-encoding : content-type; s=pfpt0220;\n bh=gHYRezTmMtFHiSprPPAV58g1ee5+XIF+VT5LoekY4AU=;\n b=TWtN3YsAcK+AL2Gy3Zx7Mge3cBqDyMB3WunTHADgR6KooGwyzp5/H0Su3BF4e3UZ4C+1\n xVgCoUm+kIV/bUJyB2mTsZum0LJxzzJ0ct9RAiBhze3bC46kByFyN/l7dUA+qrdmCwPI\n KrHrtW/fsBWROU/z2OTp/EF4QrMbPPJAYuxS/UVgFP2XK1ru2UIePCrbPatthwyZ4wRV\n b9Hebjv+a2iWfeAaI1+LqLPUwtod1PaJXqm0lcpAhY+gB9JePt19bXbXbWYCPOl5i3r0\n XSed5cR59CQqNw5zf6KQHtzFfQ0xwXst4hriAxYVG5i09Xbaf1ze7xsRm+V7SGJCUYNw kg==", "From": "Nithin Dabilpuram <ndabilpuram@marvell.com>", "To": "Nithin Kumar Dabilpuram <ndabilpuram@marvell.com>, Kiran Kumar K\n <kirankumark@marvell.com>, Sunil Kumar Kori <skori@marvell.com>, Satha Rao\n <skoteshwar@marvell.com>, Pavan Nikhilesh <pbhagavatula@marvell.com>,\n \"Shijith Thotton\" <sthotton@marvell.com>", "CC": "<jerinj@marvell.com>, <dev@dpdk.org>, Rahul Bhansali\n <rbhansali@marvell.com>", "Subject": "[PATCH 21/21] common/cnxk: support of 1:n pool:aura per NIX LF", "Date": "Tue, 11 Apr 2023 14:41:44 +0530", "Message-ID": "<20230411091144.1087887-21-ndabilpuram@marvell.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20230411091144.1087887-1-ndabilpuram@marvell.com>", "References": "<20230411091144.1087887-1-ndabilpuram@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-GUID": "_x8DBdFDqrIYSCKZejXRsGVToeRAgnfq", "X-Proofpoint-ORIG-GUID": "_x8DBdFDqrIYSCKZejXRsGVToeRAgnfq", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.254,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22\n definitions=2023-04-11_05,2023-04-06_03,2023-02-09_01", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "From: Rahul Bhansali <rbhansali@marvell.com>\n\nThis will add the support of 1:n pool:aura per NIX LF when\ninl_cpt_channel devargs is set to inline device, otherwise\nit will create 1:1 pool:aura for CN103/CN106B0 SOCs.\n\nWith 1:N, global pool will be created with Aura 0, and per NIX\nindividual aura will be created and mapped to this global pool.\n\nSigned-off-by: Rahul Bhansali <rbhansali@marvell.com>\n---\n drivers/common/cnxk/roc_idev_priv.h | 1 +\n drivers/common/cnxk/roc_nix.h | 1 +\n drivers/common/cnxk/roc_nix_inl.c | 178 ++++++++++++++++++++++++----\n drivers/common/cnxk/roc_nix_inl.h | 4 +\n drivers/common/cnxk/version.map | 1 +\n drivers/event/cnxk/cn10k_worker.h | 9 +-\n drivers/net/cnxk/cn10k_rx_select.c | 5 +-\n drivers/net/cnxk/cnxk_ethdev.c | 3 +\n drivers/net/cnxk/cnxk_ethdev.h | 3 +\n drivers/net/cnxk/cnxk_ethdev_sec.c | 62 ++++++++++\n 10 files changed, 240 insertions(+), 27 deletions(-)", "diff": "diff --git a/drivers/common/cnxk/roc_idev_priv.h b/drivers/common/cnxk/roc_idev_priv.h\nindex d83522799f..4983578fc6 100644\n--- a/drivers/common/cnxk/roc_idev_priv.h\n+++ b/drivers/common/cnxk/roc_idev_priv.h\n@@ -13,6 +13,7 @@ struct nix_inl_dev;\n \n struct idev_nix_inl_cfg {\n \tuint64_t meta_aura;\n+\tuintptr_t meta_mempool;\n \tuint32_t nb_bufs;\n \tuint32_t buf_sz;\n \tuint32_t refs;\ndiff --git a/drivers/common/cnxk/roc_nix.h b/drivers/common/cnxk/roc_nix.h\nindex 37d0ed5ebe..548854952b 100644\n--- a/drivers/common/cnxk/roc_nix.h\n+++ b/drivers/common/cnxk/roc_nix.h\n@@ -470,6 +470,7 @@ struct roc_nix {\n \tbool local_meta_aura_ena;\n \tuint32_t meta_buf_sz;\n \tbool force_rx_aura_bp;\n+\tbool custom_meta_aura_ena;\n \t/* End of input parameters */\n \t/* LMT line base for \"Per Core Tx LMT line\" mode*/\n \tuintptr_t lmt_base;\ndiff --git a/drivers/common/cnxk/roc_nix_inl.c b/drivers/common/cnxk/roc_nix_inl.c\nindex 67f8ce9aa0..69f658ba87 100644\n--- a/drivers/common/cnxk/roc_nix_inl.c\n+++ b/drivers/common/cnxk/roc_nix_inl.c\n@@ -7,6 +7,7 @@\n \n uint32_t soft_exp_consumer_cnt;\n roc_nix_inl_meta_pool_cb_t meta_pool_cb;\n+roc_nix_inl_custom_meta_pool_cb_t custom_meta_pool_cb;\n \n PLT_STATIC_ASSERT(ROC_NIX_INL_ON_IPSEC_INB_SA_SZ ==\n \t\t 1UL << ROC_NIX_INL_ON_IPSEC_INB_SA_SZ_LOG2);\n@@ -33,13 +34,14 @@ nix_inl_meta_aura_destroy(struct roc_nix *roc_nix)\n \t\treturn -EINVAL;\n \n \tinl_cfg = &idev->inl_cfg;\n-\tif (roc_nix->local_meta_aura_ena) {\n+\n+\tif (!roc_nix->local_meta_aura_ena || roc_nix->custom_meta_aura_ena) {\n+\t\tmeta_aura = &inl_cfg->meta_aura;\n+\t} else {\n \t\tmeta_aura = &roc_nix->meta_aura_handle;\n \t\tsnprintf(mempool_name, sizeof(mempool_name), \"NIX_INL_META_POOL_%d\",\n \t\t\t roc_nix->port_id + 1);\n \t\tmp_name = mempool_name;\n-\t} else {\n-\t\tmeta_aura = &inl_cfg->meta_aura;\n \t}\n \n \t/* Destroy existing Meta aura */\n@@ -72,7 +74,7 @@ nix_inl_meta_aura_destroy(struct roc_nix *roc_nix)\n \n static int\n nix_inl_meta_aura_create(struct idev_cfg *idev, struct roc_nix *roc_nix, uint16_t first_skip,\n-\t\t\t uint64_t *meta_aura)\n+\t\t\t uint64_t *meta_aura, bool is_local_metaaura)\n {\n \tuint64_t mask = BIT_ULL(ROC_NPA_BUF_TYPE_PACKET_IPSEC);\n \tstruct idev_nix_inl_cfg *inl_cfg;\n@@ -89,7 +91,7 @@ nix_inl_meta_aura_create(struct idev_cfg *idev, struct roc_nix *roc_nix, uint16_\n \tinl_cfg = &idev->inl_cfg;\n \tnix_inl_dev = idev->nix_inl_dev;\n \n-\tif (roc_nix->local_meta_aura_ena) {\n+\tif (is_local_metaaura) {\n \t\t/* Per LF Meta Aura */\n \t\tinl_rq_id = nix_inl_dev->nb_rqs > 1 ? port_id : 0;\n \t\tinl_rq = &nix_inl_dev->rqs[inl_rq_id];\n@@ -134,15 +136,107 @@ nix_inl_meta_aura_create(struct idev_cfg *idev, struct roc_nix *roc_nix, uint16_\n \tplt_nix_dbg(\"Created meta aura %p(%s)for port %d\", (void *)*meta_aura, mp_name,\n \t\t roc_nix->port_id);\n \n-\tif (!roc_nix->local_meta_aura_ena) {\n+\tif (!is_local_metaaura) {\n \t\tinl_cfg->buf_sz = buf_sz;\n \t\tinl_cfg->nb_bufs = nb_bufs;\n+\t\tinl_cfg->meta_mempool = mp;\n \t} else\n \t\troc_nix->buf_sz = buf_sz;\n \n \treturn 0;\n }\n \n+static int\n+nix_inl_custom_meta_aura_destroy(struct roc_nix *roc_nix)\n+{\n+\tstruct idev_cfg *idev = idev_get_cfg();\n+\tstruct idev_nix_inl_cfg *inl_cfg;\n+\tchar mempool_name[24] = {'\\0'};\n+\tchar *mp_name = NULL;\n+\tuint64_t *meta_aura;\n+\tint rc;\n+\n+\tif (!idev)\n+\t\treturn -EINVAL;\n+\n+\tinl_cfg = &idev->inl_cfg;\n+\tmeta_aura = &roc_nix->meta_aura_handle;\n+\tsnprintf(mempool_name, sizeof(mempool_name), \"NIX_INL_META_POOL_%d\",\n+\t\t roc_nix->port_id + 1);\n+\tmp_name = mempool_name;\n+\n+\t/* Destroy existing Meta aura */\n+\tif (*meta_aura) {\n+\t\tuint64_t avail, limit;\n+\n+\t\t/* Check if all buffers are back to pool */\n+\t\tavail = roc_npa_aura_op_available(*meta_aura);\n+\t\tlimit = roc_npa_aura_op_limit_get(*meta_aura);\n+\t\tif (avail != limit)\n+\t\t\tplt_warn(\"Not all buffers are back to meta pool,\"\n+\t\t\t\t \" %\" PRIu64 \" != %\" PRIu64, avail, limit);\n+\n+\t\trc = custom_meta_pool_cb(inl_cfg->meta_mempool, &roc_nix->meta_mempool, mp_name,\n+\t\t\t\t\t meta_aura, 0, 0, true);\n+\t\tif (rc) {\n+\t\t\tplt_err(\"Failed to destroy meta aura, rc=%d\", rc);\n+\t\t\treturn rc;\n+\t\t}\n+\n+\t\troc_nix->buf_sz = 0;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int\n+nix_inl_custom_meta_aura_create(struct idev_cfg *idev, struct roc_nix *roc_nix, uint16_t first_skip,\n+\t\t\t\tuint64_t *meta_aura)\n+{\n+\tuint64_t mask = BIT_ULL(ROC_NPA_BUF_TYPE_PACKET_IPSEC);\n+\tstruct idev_nix_inl_cfg *inl_cfg;\n+\tstruct nix_inl_dev *nix_inl_dev;\n+\tchar mempool_name[24] = {'\\0'};\n+\tuint32_t nb_bufs, buf_sz;\n+\tchar *mp_name = NULL;\n+\tuintptr_t mp;\n+\tint rc;\n+\n+\tinl_cfg = &idev->inl_cfg;\n+\tnix_inl_dev = idev->nix_inl_dev;\n+\n+\t/* Override meta buf count from devargs if present */\n+\tif (nix_inl_dev && nix_inl_dev->nb_meta_bufs)\n+\t\tnb_bufs = nix_inl_dev->nb_meta_bufs;\n+\telse\n+\t\tnb_bufs = roc_npa_buf_type_limit_get(mask);\n+\n+\t/* Override meta buf size from devargs if present */\n+\tif (nix_inl_dev && nix_inl_dev->meta_buf_sz)\n+\t\tbuf_sz = nix_inl_dev->meta_buf_sz;\n+\telse\n+\t\tbuf_sz = first_skip + NIX_INL_META_SIZE;\n+\n+\t/* Create Metapool name */\n+\tsnprintf(mempool_name, sizeof(mempool_name), \"NIX_INL_META_POOL_%d\",\n+\t\t roc_nix->port_id + 1);\n+\tmp_name = mempool_name;\n+\n+\t/* Allocate meta aura */\n+\trc = custom_meta_pool_cb(inl_cfg->meta_mempool, &mp, mp_name, meta_aura,\n+\t\t\t\t buf_sz, nb_bufs, false);\n+\tif (rc) {\n+\t\tplt_err(\"Failed to allocate meta aura, rc=%d\", rc);\n+\t\treturn rc;\n+\t}\n+\n+\t/* Overwrite */\n+\troc_nix->meta_mempool = mp;\n+\troc_nix->buf_sz = buf_sz;\n+\n+\treturn 0;\n+}\n+\n static int\n nix_inl_global_meta_buffer_validate(struct idev_cfg *idev, struct roc_nix_rq *rq)\n {\n@@ -228,6 +322,7 @@ roc_nix_inl_meta_aura_check(struct roc_nix *roc_nix, struct roc_nix_rq *rq)\n \tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n \tstruct idev_cfg *idev = idev_get_cfg();\n \tstruct idev_nix_inl_cfg *inl_cfg;\n+\tbool is_local_metaaura;\n \tbool aura_setup = false;\n \tuint64_t *meta_aura;\n \tint rc;\n@@ -238,18 +333,39 @@ roc_nix_inl_meta_aura_check(struct roc_nix *roc_nix, struct roc_nix_rq *rq)\n \tinl_cfg = &idev->inl_cfg;\n \n \t/* Create meta aura if not present */\n-\tif (roc_nix->local_meta_aura_ena)\n-\t\tmeta_aura = &roc_nix->meta_aura_handle;\n-\telse\n+\tif (!roc_nix->local_meta_aura_ena || roc_nix->custom_meta_aura_ena) {\n \t\tmeta_aura = &inl_cfg->meta_aura;\n+\t\tis_local_metaaura = false;\n+\t} else {\n+\t\tmeta_aura = &roc_nix->meta_aura_handle;\n+\t\tis_local_metaaura = true;\n+\t}\n \n \tif (!(*meta_aura)) {\n-\t\trc = nix_inl_meta_aura_create(idev, roc_nix, rq->first_skip, meta_aura);\n+\t\trc = nix_inl_meta_aura_create(idev, roc_nix, rq->first_skip, meta_aura,\n+\t\t\t\t\t is_local_metaaura);\n \t\tif (rc)\n \t\t\treturn rc;\n \n \t\taura_setup = true;\n \t}\n+\n+\tif (roc_nix->custom_meta_aura_ena) {\n+\t\t/* Create metaura for 1:N pool:aura */\n+\t\tif (!custom_meta_pool_cb)\n+\t\t\treturn -EFAULT;\n+\n+\t\tmeta_aura = &roc_nix->meta_aura_handle;\n+\t\tif (!(*meta_aura)) {\n+\t\t\trc = nix_inl_custom_meta_aura_create(idev, roc_nix, rq->first_skip,\n+\t\t\t\t\t\t\t meta_aura);\n+\t\t\tif (rc)\n+\t\t\t\treturn rc;\n+\n+\t\t\taura_setup = true;\n+\t\t}\n+\t}\n+\n \t/* Update rq meta aura handle */\n \trq->meta_aura_handle = *meta_aura;\n \n@@ -698,6 +814,7 @@ roc_nix_inl_inb_init(struct roc_nix *roc_nix)\n \tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n \tstruct roc_cpt_inline_ipsec_inb_cfg cfg;\n \tstruct idev_cfg *idev = idev_get_cfg();\n+\tstruct nix_inl_dev *inl_dev;\n \tuint16_t bpids[ROC_NIX_MAX_BPID_CNT];\n \tstruct roc_cpt *roc_cpt;\n \tint rc;\n@@ -749,9 +866,13 @@ roc_nix_inl_inb_init(struct roc_nix *roc_nix)\n \tif (rc)\n \t\treturn rc;\n \n+\tinl_dev = idev->nix_inl_dev;\n+\n+\troc_nix->custom_meta_aura_ena = (roc_nix->local_meta_aura_ena &&\n+\t\t\t\t\t (inl_dev->is_multi_channel || roc_nix->custom_sa_action));\n \tif (!roc_model_is_cn9k() && !roc_errata_nix_no_meta_aura()) {\n \t\tnix->need_meta_aura = true;\n-\t\tif (!roc_nix->local_meta_aura_ena)\n+\t\tif (!roc_nix->local_meta_aura_ena || roc_nix->custom_meta_aura_ena)\n \t\t\tidev->inl_cfg.refs++;\n \t}\n \n@@ -773,15 +894,17 @@ roc_nix_inl_inb_fini(struct roc_nix *roc_nix)\n \t\treturn -EFAULT;\n \n \tnix->inl_inb_ena = false;\n+\n \tif (nix->need_meta_aura) {\n \t\tnix->need_meta_aura = false;\n-\t\tif (roc_nix->local_meta_aura_ena) {\n-\t\t\tnix_inl_meta_aura_destroy(roc_nix);\n-\t\t} else {\n+\t\tif (!roc_nix->local_meta_aura_ena || roc_nix->custom_meta_aura_ena)\n \t\t\tidev->inl_cfg.refs--;\n-\t\t\tif (!idev->inl_cfg.refs)\n-\t\t\t\tnix_inl_meta_aura_destroy(roc_nix);\n-\t\t}\n+\n+\t\tif (roc_nix->custom_meta_aura_ena)\n+\t\t\tnix_inl_custom_meta_aura_destroy(roc_nix);\n+\n+\t\tif (!idev->inl_cfg.refs)\n+\t\t\tnix_inl_meta_aura_destroy(roc_nix);\n \t}\n \n \tif (roc_feature_nix_has_inl_rq_mask()) {\n@@ -1309,17 +1432,18 @@ roc_nix_inl_inb_set(struct roc_nix *roc_nix, bool ena)\n \n \tif (ena) {\n \t\tnix->need_meta_aura = true;\n-\t\tif (!roc_nix->local_meta_aura_ena)\n+\t\tif (!roc_nix->local_meta_aura_ena || roc_nix->custom_meta_aura_ena)\n \t\t\tidev->inl_cfg.refs++;\n \t} else if (nix->need_meta_aura) {\n \t\tnix->need_meta_aura = false;\n-\t\tif (roc_nix->local_meta_aura_ena) {\n-\t\t\tnix_inl_meta_aura_destroy(roc_nix);\n-\t\t} else {\n+\t\tif (!roc_nix->local_meta_aura_ena || roc_nix->custom_meta_aura_ena)\n \t\t\tidev->inl_cfg.refs--;\n-\t\t\tif (!idev->inl_cfg.refs)\n-\t\t\t\tnix_inl_meta_aura_destroy(roc_nix);\n-\t\t}\n+\n+\t\tif (roc_nix->custom_meta_aura_ena)\n+\t\t\tnix_inl_custom_meta_aura_destroy(roc_nix);\n+\n+\t\tif (!idev->inl_cfg.refs)\n+\t\t\tnix_inl_meta_aura_destroy(roc_nix);\n \t}\n }\n \n@@ -1672,3 +1796,9 @@ roc_nix_inl_eng_caps_get(struct roc_nix *roc_nix)\n \n \treturn nix->cpt_eng_caps;\n }\n+\n+void\n+roc_nix_inl_custom_meta_pool_cb_register(roc_nix_inl_custom_meta_pool_cb_t cb)\n+{\n+\tcustom_meta_pool_cb = cb;\n+}\ndiff --git a/drivers/common/cnxk/roc_nix_inl.h b/drivers/common/cnxk/roc_nix_inl.h\nindex daa21a941a..885d95335e 100644\n--- a/drivers/common/cnxk/roc_nix_inl.h\n+++ b/drivers/common/cnxk/roc_nix_inl.h\n@@ -121,6 +121,9 @@ typedef void (*roc_nix_inl_sso_work_cb_t)(uint64_t *gw, void *args,\n typedef int (*roc_nix_inl_meta_pool_cb_t)(uint64_t *aura_handle, uintptr_t *mpool,\n \t\t\t\t\t uint32_t blk_sz, uint32_t nb_bufs, bool destroy,\n \t\t\t\t\t const char *mempool_name);\n+typedef int (*roc_nix_inl_custom_meta_pool_cb_t)(uintptr_t pmpool, uintptr_t *mpool,\n+\t\t\t\t\t\t const char *mempool_name, uint64_t *aura_handle,\n+\t\t\t\t\t\t uint32_t blk_sz, uint32_t nb_bufs, bool destroy);\n \n struct roc_nix_inl_dev {\n \t/* Input parameters */\n@@ -199,6 +202,7 @@ int __roc_api roc_nix_inl_outb_soft_exp_poll_switch(struct roc_nix *roc_nix,\n \t\t\t\t\t\t bool poll);\n uint64_t *__roc_api roc_nix_inl_outb_ring_base_get(struct roc_nix *roc_nix);\n void __roc_api roc_nix_inl_meta_pool_cb_register(roc_nix_inl_meta_pool_cb_t cb);\n+void __roc_api roc_nix_inl_custom_meta_pool_cb_register(roc_nix_inl_custom_meta_pool_cb_t cb);\n \n /* NIX Inline/Outbound API */\n enum roc_nix_inl_sa_sync_op {\ndiff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map\nindex 809fd81b20..c76564b46e 100644\n--- a/drivers/common/cnxk/version.map\n+++ b/drivers/common/cnxk/version.map\n@@ -199,6 +199,7 @@ INTERNAL {\n \troc_nix_inb_is_with_inl_dev;\n \troc_nix_inl_meta_aura_check;\n \troc_nix_inl_meta_pool_cb_register;\n+\troc_nix_inl_custom_meta_pool_cb_register;\n \troc_nix_inb_mode_set;\n \troc_nix_inl_outb_fini;\n \troc_nix_inl_outb_init;\ndiff --git a/drivers/event/cnxk/cn10k_worker.h b/drivers/event/cnxk/cn10k_worker.h\nindex 06c71c6092..07f0dad97d 100644\n--- a/drivers/event/cnxk/cn10k_worker.h\n+++ b/drivers/event/cnxk/cn10k_worker.h\n@@ -167,6 +167,10 @@ cn10k_sso_hws_post_process(struct cn10k_sso_hws *ws, uint64_t *u64,\n \t\tmbuf = u64[1] - sizeof(struct rte_mbuf);\n \t\trte_prefetch0((void *)mbuf);\n \t\tif (flags & NIX_RX_OFFLOAD_SECURITY_F) {\n+\t\t\tvoid *lookup_mem = ws->lookup_mem;\n+\t\t\tstruct rte_mempool *mp = NULL;\n+\t\t\tuint64_t meta_aura;\n+\n \t\t\tconst uint64_t mbuf_init =\n \t\t\t\t0x100010000ULL | RTE_PKTMBUF_HEADROOM |\n \t\t\t\t(flags & NIX_RX_OFFLOAD_TSTAMP_F ? 8 : 0);\n@@ -191,8 +195,11 @@ cn10k_sso_hws_post_process(struct cn10k_sso_hws *ws, uint64_t *u64,\n \t\t\t\tcq_w1, cq_w5, sa_base, (uintptr_t)&iova, &loff,\n \t\t\t\t(struct rte_mbuf *)mbuf, d_off, flags,\n \t\t\t\tmbuf_init | ((uint64_t)port) << 48);\n+\t\t\tmp = (struct rte_mempool *)cnxk_nix_inl_metapool_get(port, lookup_mem);\n+\t\t\tmeta_aura = mp ? mp->pool_id : m->pool->pool_id;\n+\n \t\t\tif (loff)\n-\t\t\t\troc_npa_aura_op_free(m->pool->pool_id, 0, iova);\n+\t\t\t\troc_npa_aura_op_free(meta_aura, 0, iova);\n \t\t}\n \n \t\tu64[0] = CNXK_CLR_SUB_EVENT(u64[0]);\ndiff --git a/drivers/net/cnxk/cn10k_rx_select.c b/drivers/net/cnxk/cn10k_rx_select.c\nindex b906f6725a..1e0de1b7ac 100644\n--- a/drivers/net/cnxk/cn10k_rx_select.c\n+++ b/drivers/net/cnxk/cn10k_rx_select.c\n@@ -79,9 +79,10 @@ cn10k_eth_set_rx_function(struct rte_eth_dev *eth_dev)\n #undef R\n \t};\n \n-\t/* Copy multi seg version with no offload for tear down sequence */\n+\t/* Copy multi seg version with security for tear down sequence */\n \tif (rte_eal_process_type() == RTE_PROC_PRIMARY)\n-\t\tdev->rx_pkt_burst_no_offload = nix_eth_rx_burst_mseg[0];\n+\t\tdev->rx_pkt_burst_no_offload =\n+\t\t\tnix_eth_rx_burst_mseg_reas[NIX_RX_OFFLOAD_SECURITY_F];\n \n \tif (dev->scalar_ena) {\n \t\tif (dev->rx_offloads & RTE_ETH_RX_OFFLOAD_SCATTER) {\ndiff --git a/drivers/net/cnxk/cnxk_ethdev.c b/drivers/net/cnxk/cnxk_ethdev.c\nindex 6b45ccd0f7..677539c35a 100644\n--- a/drivers/net/cnxk/cnxk_ethdev.c\n+++ b/drivers/net/cnxk/cnxk_ethdev.c\n@@ -1883,6 +1883,9 @@ cnxk_eth_dev_init(struct rte_eth_dev *eth_dev)\n \t/* Register callback for inline meta pool create */\n \troc_nix_inl_meta_pool_cb_register(cnxk_nix_inl_meta_pool_cb);\n \n+\t/* Register callback for inline meta pool create 1:N pool:aura */\n+\troc_nix_inl_custom_meta_pool_cb_register(cnxk_nix_inl_custom_meta_pool_cb);\n+\n \tdev->eth_dev = eth_dev;\n \tdev->configured = 0;\n \tdev->ptype_disable = 0;\ndiff --git a/drivers/net/cnxk/cnxk_ethdev.h b/drivers/net/cnxk/cnxk_ethdev.h\nindex d76f5486e6..85287dd66c 100644\n--- a/drivers/net/cnxk/cnxk_ethdev.h\n+++ b/drivers/net/cnxk/cnxk_ethdev.h\n@@ -608,6 +608,9 @@ cnxk_eth_sec_sess_get_by_sess(struct cnxk_eth_dev *dev,\n \t\t\t struct rte_security_session *sess);\n int cnxk_nix_inl_meta_pool_cb(uint64_t *aura_handle, uintptr_t *mpool, uint32_t buf_sz,\n \t\t\t uint32_t nb_bufs, bool destroy, const char *mempool_name);\n+int cnxk_nix_inl_custom_meta_pool_cb(uintptr_t pmpool, uintptr_t *mpool, const char *mempool_name,\n+\t\t\t\t uint64_t *aura_handle, uint32_t buf_sz, uint32_t nb_bufs,\n+\t\t\t\t bool destroy);\n \n /* Congestion Management */\n int cnxk_nix_cman_info_get(struct rte_eth_dev *dev, struct rte_eth_cman_info *info);\ndiff --git a/drivers/net/cnxk/cnxk_ethdev_sec.c b/drivers/net/cnxk/cnxk_ethdev_sec.c\nindex cd64daacc0..a66d58ca61 100644\n--- a/drivers/net/cnxk/cnxk_ethdev_sec.c\n+++ b/drivers/net/cnxk/cnxk_ethdev_sec.c\n@@ -6,6 +6,7 @@\n #include <cnxk_mempool.h>\n \n #define CNXK_NIX_INL_META_POOL_NAME \"NIX_INL_META_POOL\"\n+#define CN10K_HW_POOL_OPS_NAME \"cn10k_hwpool_ops\"\n \n #define CNXK_NIX_INL_SELFTEST\t \"selftest\"\n #define CNXK_NIX_INL_IPSEC_IN_MIN_SPI \"ipsec_in_min_spi\"\n@@ -114,6 +115,67 @@ cnxk_nix_inl_meta_pool_cb(uint64_t *aura_handle, uintptr_t *mpool, uint32_t buf_\n \treturn rc;\n }\n \n+/* Create Aura and link with Global mempool for 1:N Pool:Aura case */\n+int\n+cnxk_nix_inl_custom_meta_pool_cb(uintptr_t pmpool, uintptr_t *mpool, const char *mempool_name,\n+\t\t\t\t uint64_t *aura_handle, uint32_t buf_sz, uint32_t nb_bufs,\n+\t\t\t\t bool destroy)\n+{\n+\tstruct rte_mempool *hp;\n+\tint rc;\n+\n+\t/* Destroy the mempool if requested */\n+\tif (destroy) {\n+\t\thp = rte_mempool_lookup(mempool_name);\n+\t\tif (!hp)\n+\t\t\treturn -ENOENT;\n+\n+\t\tif (hp->pool_id != *aura_handle) {\n+\t\t\tplt_err(\"Meta pool aura mismatch\");\n+\t\t\treturn -EINVAL;\n+\t\t}\n+\n+\t\trte_mempool_free(hp);\n+\t\tplt_free(hp->pool_config);\n+\n+\t\t*aura_handle = 0;\n+\t\t*mpool = 0;\n+\t\treturn 0;\n+\t}\n+\n+\t/* Need to make it similar to rte_pktmbuf_pool() for sake of OOP\n+\t * support.\n+\t */\n+\thp = rte_mempool_create_empty(mempool_name, nb_bufs, buf_sz, 0,\n+\t\t\t\t sizeof(struct rte_pktmbuf_pool_private),\n+\t\t\t\t SOCKET_ID_ANY, 0);\n+\tif (!hp) {\n+\t\tplt_err(\"Failed to create inline meta pool\");\n+\t\treturn -EIO;\n+\t}\n+\n+\trc = rte_mempool_set_ops_byname(hp, CN10K_HW_POOL_OPS_NAME, (void *)pmpool);\n+\n+\tif (rc) {\n+\t\tplt_err(\"Failed to setup ops, rc=%d\", rc);\n+\t\tgoto free_hp;\n+\t}\n+\n+\t/* Populate buffer */\n+\trc = rte_mempool_populate_default(hp);\n+\tif (rc < 0) {\n+\t\tplt_err(\"Failed to populate pool, rc=%d\", rc);\n+\t\tgoto free_hp;\n+\t}\n+\n+\t*aura_handle = hp->pool_id;\n+\t*mpool = (uintptr_t)hp;\n+\treturn 0;\n+free_hp:\n+\trte_mempool_free(hp);\n+\treturn rc;\n+}\n+\n static int\n parse_max_ipsec_rules(const char *key, const char *value, void *extra_args)\n {\n", "prefixes": [ "21/21" ] }