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GET /api/patches/125914/?format=api
{ "id": 125914, "url": "http://patches.dpdk.org/api/patches/125914/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20230411091144.1087887-9-ndabilpuram@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20230411091144.1087887-9-ndabilpuram@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20230411091144.1087887-9-ndabilpuram@marvell.com", "date": "2023-04-11T09:11:32", "name": "[09/21] common/cnxk: fetch eng caps for inl outb inst format", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": true, "hash": "b029243f89f2510b2a62e86c126d3c904312e060", "submitter": { "id": 1202, "url": "http://patches.dpdk.org/api/people/1202/?format=api", "name": "Nithin Dabilpuram", "email": "ndabilpuram@marvell.com" }, "delegate": { "id": 310, "url": "http://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20230411091144.1087887-9-ndabilpuram@marvell.com/mbox/", "series": [ { "id": 27660, "url": "http://patches.dpdk.org/api/series/27660/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=27660", "date": "2023-04-11T09:11:24", "name": "[01/21] common/cnxk: allocate dynamic BPIDs", "version": 1, "mbox": "http://patches.dpdk.org/series/27660/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/125914/comments/", "check": "warning", "checks": "http://patches.dpdk.org/api/patches/125914/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 0767B4291B;\n\tTue, 11 Apr 2023 11:13:03 +0200 (CEST)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 88E9F42D2C;\n\tTue, 11 Apr 2023 11:12:30 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com\n [67.231.148.174])\n by mails.dpdk.org (Postfix) with ESMTP id 9992342D16\n for <dev@dpdk.org>; Tue, 11 Apr 2023 11:12:29 +0200 (CEST)", "from pps.filterd (m0045849.ppops.net [127.0.0.1])\n by mx0a-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id\n 33B8S2oh021558 for <dev@dpdk.org>; Tue, 11 Apr 2023 02:12:28 -0700", "from dc5-exch01.marvell.com ([199.233.59.181])\n by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3pvt73b1tw-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Tue, 11 Apr 2023 02:12:28 -0700", "from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.48;\n Tue, 11 Apr 2023 02:12:26 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.48 via Frontend\n Transport; Tue, 11 Apr 2023 02:12:26 -0700", "from hyd1588t430.caveonetworks.com (unknown [10.29.52.204])\n by maili.marvell.com (Postfix) with ESMTP id BD9D23F706A;\n Tue, 11 Apr 2023 02:12:24 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-transfer-encoding : content-type; s=pfpt0220;\n bh=2TkopDAp1mbYKV1nFdILeFSWEfW64qN75y0HbHuESA0=;\n b=HDTDv8+GrdhwzCC8S38fAEWRAmOmEhgXCQaO1zecnPgNbl98AQgEbNWAre3NE8rYIm45\n qpEZ0ySNzrdGEaAdcBCfx3GSu/NibCqNlRisF4VPgVukOwrWUvYB2RhOsqFjkP/pdyp2\n TqgE7/MA5G7eVH5s1OzK4jFTsiRE1xDPYzgqhhn0Qr242AVELsfx8+5tBkE623WzMKRF\n AlZEM1f2FUKYPsnShy62XgREfefkToOxyneqCE0/0auOdFMX2ku90butzlePo6R4klLo\n TA6VIj+ZLAbWBBNrco/5kv2IEjvY+bhCwj3tnIC/qHMJqkXqMf2VDvkH8yeZ7Zr3fsut LQ==", "From": "Nithin Dabilpuram <ndabilpuram@marvell.com>", "To": "Nithin Kumar Dabilpuram <ndabilpuram@marvell.com>, Kiran Kumar K\n <kirankumark@marvell.com>, Sunil Kumar Kori <skori@marvell.com>, Satha Rao\n <skoteshwar@marvell.com>", "CC": "<jerinj@marvell.com>, <dev@dpdk.org>", "Subject": "[PATCH 09/21] common/cnxk: fetch eng caps for inl outb inst format", "Date": "Tue, 11 Apr 2023 14:41:32 +0530", "Message-ID": "<20230411091144.1087887-9-ndabilpuram@marvell.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20230411091144.1087887-1-ndabilpuram@marvell.com>", "References": "<20230411091144.1087887-1-ndabilpuram@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-GUID": "IXYhjsQ4Ob0_q8RS1yrfXThXTxv6hBSf", "X-Proofpoint-ORIG-GUID": "IXYhjsQ4Ob0_q8RS1yrfXThXTxv6hBSf", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.254,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22\n definitions=2023-04-11_05,2023-04-06_03,2023-02-09_01", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Fetch engine caps and use it along with model check\nto determine inline outbound instruction format\nwith NIX Tx offset or address.\n\nSigned-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>\n---\n drivers/common/cnxk/roc_cpt.h | 3 +\n drivers/common/cnxk/roc_nix_inl.c | 101 ++++++++++++++++++++++++++++\n drivers/common/cnxk/roc_nix_inl.h | 1 +\n drivers/common/cnxk/roc_nix_priv.h | 1 +\n drivers/common/cnxk/version.map | 1 +\n drivers/net/cnxk/cn10k_ethdev_sec.c | 3 +-\n drivers/net/cnxk/cnxk_ethdev.c | 2 +\n drivers/net/cnxk/cnxk_ethdev.h | 3 +\n 8 files changed, 114 insertions(+), 1 deletion(-)", "diff": "diff --git a/drivers/common/cnxk/roc_cpt.h b/drivers/common/cnxk/roc_cpt.h\nindex 92a18711dc..910bd37a0c 100644\n--- a/drivers/common/cnxk/roc_cpt.h\n+++ b/drivers/common/cnxk/roc_cpt.h\n@@ -12,6 +12,9 @@\n #define ROC_AE_CPT_BLOCK_TYPE1 0\n #define ROC_AE_CPT_BLOCK_TYPE2 1\n \n+#define ROC_LOADFVC_MAJOR_OP 0x01UL\n+#define ROC_LOADFVC_MINOR_OP 0x08UL\n+\n /* Default engine groups */\n #define ROC_CPT_DFLT_ENG_GRP_SE\t 0UL\n #define ROC_CPT_DFLT_ENG_GRP_SE_IE 1UL\ndiff --git a/drivers/common/cnxk/roc_nix_inl.c b/drivers/common/cnxk/roc_nix_inl.c\nindex 8592e1cb0b..67f8ce9aa0 100644\n--- a/drivers/common/cnxk/roc_nix_inl.c\n+++ b/drivers/common/cnxk/roc_nix_inl.c\n@@ -602,6 +602,96 @@ nix_inl_rq_mask_cfg(struct roc_nix *roc_nix, bool enable)\n \treturn rc;\n }\n \n+static void\n+nix_inl_eng_caps_get(struct nix *nix)\n+{\n+\tstruct roc_cpt_lf *lf = nix->cpt_lf_base;\n+\tuintptr_t lmt_base = lf->lmt_base;\n+\tunion cpt_res_s res, *hw_res;\n+\tstruct cpt_inst_s inst;\n+\tuint64_t *rptr;\n+\n+\thw_res = plt_zmalloc(sizeof(*hw_res), ROC_CPT_RES_ALIGN);\n+\tif (hw_res == NULL) {\n+\t\tplt_err(\"Couldn't allocate memory for result address\");\n+\t\treturn;\n+\t}\n+\n+\trptr = plt_zmalloc(ROC_ALIGN, 0);\n+\tif (rptr == NULL) {\n+\t\tplt_err(\"Couldn't allocate memory for rptr\");\n+\t\tplt_free(hw_res);\n+\t\treturn;\n+\t}\n+\n+\t/* Fill CPT_INST_S for LOAD_FVC/HW_CRYPTO_SUPPORT microcode op */\n+\tmemset(&inst, 0, sizeof(struct cpt_inst_s));\n+\tinst.res_addr = (uint64_t)hw_res;\n+\tinst.rptr = (uint64_t)rptr;\n+\tinst.w4.s.opcode_major = ROC_LOADFVC_MAJOR_OP;\n+\tinst.w4.s.opcode_minor = ROC_LOADFVC_MINOR_OP;\n+\tinst.w7.s.egrp = ROC_CPT_DFLT_ENG_GRP_SE;\n+\n+\t/* Use 1 min timeout for the poll */\n+\tconst uint64_t timeout = plt_tsc_cycles() + 60 * plt_tsc_hz();\n+\n+\tif (roc_model_is_cn9k()) {\n+\t\tuint64_t lmt_status;\n+\n+\t\thw_res->cn9k.compcode = CPT_COMP_NOT_DONE;\n+\t\tplt_io_wmb();\n+\n+\t\tdo {\n+\t\t\troc_lmt_mov_seg((void *)lmt_base, &inst, 4);\n+\t\t\tlmt_status = roc_lmt_submit_ldeor(lf->io_addr);\n+\t\t} while (lmt_status != 0);\n+\n+\t\t/* Wait until CPT instruction completes */\n+\t\tdo {\n+\t\t\tres.u64[0] = __atomic_load_n(&hw_res->u64[0], __ATOMIC_RELAXED);\n+\t\t\tif (unlikely(plt_tsc_cycles() > timeout))\n+\t\t\t\tbreak;\n+\t\t} while (res.cn9k.compcode == CPT_COMP_NOT_DONE);\n+\n+\t\tif (res.cn9k.compcode != CPT_COMP_GOOD) {\n+\t\t\tplt_err(\"LOAD FVC operation timed out\");\n+\t\t\treturn;\n+\t\t}\n+\t} else {\n+\t\tuint64_t lmt_arg, io_addr;\n+\t\tuint16_t lmt_id;\n+\n+\t\thw_res->cn10k.compcode = CPT_COMP_NOT_DONE;\n+\n+\t\t/* Use this lcore's LMT line as no one else is using it */\n+\t\tROC_LMT_BASE_ID_GET(lmt_base, lmt_id);\n+\t\tmemcpy((void *)lmt_base, &inst, sizeof(inst));\n+\n+\t\tlmt_arg = ROC_CN10K_CPT_LMT_ARG | (uint64_t)lmt_id;\n+\t\tio_addr = lf->io_addr | ROC_CN10K_CPT_INST_DW_M1 << 4;\n+\n+\t\troc_lmt_submit_steorl(lmt_arg, io_addr);\n+\t\tplt_io_wmb();\n+\n+\t\t/* Wait until CPT instruction completes */\n+\t\tdo {\n+\t\t\tres.u64[0] = __atomic_load_n(&hw_res->u64[0], __ATOMIC_RELAXED);\n+\t\t\tif (unlikely(plt_tsc_cycles() > timeout))\n+\t\t\t\tbreak;\n+\t\t} while (res.cn10k.compcode == CPT_COMP_NOT_DONE);\n+\n+\t\tif (res.cn10k.compcode != CPT_COMP_GOOD || res.cn10k.uc_compcode) {\n+\t\t\tplt_err(\"LOAD FVC operation timed out\");\n+\t\t\tgoto exit;\n+\t\t}\n+\t}\n+\n+\tnix->cpt_eng_caps = plt_be_to_cpu_64(*rptr);\n+exit:\n+\tplt_free(rptr);\n+\tplt_free(hw_res);\n+}\n+\n int\n roc_nix_inl_inb_init(struct roc_nix *roc_nix)\n {\n@@ -652,6 +742,7 @@ roc_nix_inl_inb_init(struct roc_nix *roc_nix)\n \t\tplt_err(\"Failed to setup inbound lf, rc=%d\", rc);\n \t\treturn rc;\n \t}\n+\tnix->cpt_eng_caps = roc_cpt->hw_caps[CPT_ENG_TYPE_SE].u;\n \n \t/* Setup Inbound SA table */\n \trc = nix_inl_inb_sa_tbl_setup(roc_nix);\n@@ -871,6 +962,8 @@ roc_nix_inl_outb_init(struct roc_nix *roc_nix)\n \t\t}\n \t}\n \n+\t/* Fetch engine capabilities */\n+\tnix_inl_eng_caps_get(nix);\n \treturn 0;\n \n lf_fini:\n@@ -1571,3 +1664,11 @@ roc_nix_inl_meta_pool_cb_register(roc_nix_inl_meta_pool_cb_t cb)\n {\n \tmeta_pool_cb = cb;\n }\n+\n+uint64_t\n+roc_nix_inl_eng_caps_get(struct roc_nix *roc_nix)\n+{\n+\tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n+\n+\treturn nix->cpt_eng_caps;\n+}\ndiff --git a/drivers/common/cnxk/roc_nix_inl.h b/drivers/common/cnxk/roc_nix_inl.h\nindex 6220ba6773..daa21a941a 100644\n--- a/drivers/common/cnxk/roc_nix_inl.h\n+++ b/drivers/common/cnxk/roc_nix_inl.h\n@@ -212,5 +212,6 @@ int __roc_api roc_nix_inl_sa_sync(struct roc_nix *roc_nix, void *sa, bool inb,\n int __roc_api roc_nix_inl_ctx_write(struct roc_nix *roc_nix, void *sa_dptr,\n \t\t\t\t void *sa_cptr, bool inb, uint16_t sa_len);\n void __roc_api roc_nix_inl_outb_cpt_lfs_dump(struct roc_nix *roc_nix, FILE *file);\n+uint64_t __roc_api roc_nix_inl_eng_caps_get(struct roc_nix *roc_nix);\n \n #endif /* _ROC_NIX_INL_H_ */\ndiff --git a/drivers/common/cnxk/roc_nix_priv.h b/drivers/common/cnxk/roc_nix_priv.h\nindex f900a81d8a..6872630dc8 100644\n--- a/drivers/common/cnxk/roc_nix_priv.h\n+++ b/drivers/common/cnxk/roc_nix_priv.h\n@@ -209,6 +209,7 @@ struct nix {\n \tuint16_t outb_se_ring_base;\n \tuint16_t cpt_lbpid;\n \tuint16_t cpt_nixbpid;\n+\tuint64_t cpt_eng_caps;\n \tbool need_meta_aura;\n \t/* Mode provided by driver */\n \tbool inb_inl_dev;\ndiff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map\nindex d740d9df81..809fd81b20 100644\n--- a/drivers/common/cnxk/version.map\n+++ b/drivers/common/cnxk/version.map\n@@ -186,6 +186,7 @@ INTERNAL {\n \troc_nix_inl_dev_rq_put;\n \troc_nix_inl_dev_unlock;\n \troc_nix_inl_dev_xaq_realloc;\n+\troc_nix_inl_eng_caps_get;\n \troc_nix_inl_inb_is_enabled;\n \troc_nix_inl_inb_init;\n \troc_nix_inl_inb_sa_base_get;\ndiff --git a/drivers/net/cnxk/cn10k_ethdev_sec.c b/drivers/net/cnxk/cn10k_ethdev_sec.c\nindex 3c32de0f94..9625704ec1 100644\n--- a/drivers/net/cnxk/cn10k_ethdev_sec.c\n+++ b/drivers/net/cnxk/cn10k_ethdev_sec.c\n@@ -809,7 +809,8 @@ cn10k_eth_sec_session_create(void *device,\n \t\tsess_priv.chksum = (!ipsec->options.ip_csum_enable << 1 |\n \t\t\t\t !ipsec->options.l4_csum_enable);\n \t\tsess_priv.dec_ttl = ipsec->options.dec_ttl;\n-\t\tif (roc_feature_nix_has_inl_ipsec_mseg())\n+\t\tif (roc_feature_nix_has_inl_ipsec_mseg() &&\n+\t\t dev->outb.cpt_eng_caps & BIT_ULL(35))\n \t\t\tsess_priv.nixtx_off = 1;\n \n \t\t/* Pointer from eth_sec -> outb_sa */\ndiff --git a/drivers/net/cnxk/cnxk_ethdev.c b/drivers/net/cnxk/cnxk_ethdev.c\nindex 3bccc34d79..ff0c3b8ed1 100644\n--- a/drivers/net/cnxk/cnxk_ethdev.c\n+++ b/drivers/net/cnxk/cnxk_ethdev.c\n@@ -203,6 +203,8 @@ nix_security_setup(struct cnxk_eth_dev *dev)\n \t\t\tplt_err(\"Outbound fc sw mem alloc failed\");\n \t\t\tgoto sa_bmap_free;\n \t\t}\n+\n+\t\tdev->outb.cpt_eng_caps = roc_nix_inl_eng_caps_get(nix);\n \t}\n \treturn 0;\n \ndiff --git a/drivers/net/cnxk/cnxk_ethdev.h b/drivers/net/cnxk/cnxk_ethdev.h\nindex 62a06e5d03..d76f5486e6 100644\n--- a/drivers/net/cnxk/cnxk_ethdev.h\n+++ b/drivers/net/cnxk/cnxk_ethdev.h\n@@ -285,6 +285,9 @@ struct cnxk_eth_dev_sec_outb {\n \n \t/* Lock to synchronize sa setup/release */\n \trte_spinlock_t lock;\n+\n+\t/* Engine caps */\n+\tuint64_t cpt_eng_caps;\n };\n \n struct cnxk_eth_dev {\n", "prefixes": [ "09/21" ] }