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GET /api/patches/125875/?format=api
{ "id": 125875, "url": "http://patches.dpdk.org/api/patches/125875/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20230410102149.198389-1-Sivaprasad.Tummala@amd.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20230410102149.198389-1-Sivaprasad.Tummala@amd.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20230410102149.198389-1-Sivaprasad.Tummala@amd.com", "date": "2023-04-10T10:21:49", "name": "[v1] power: amd power monitor support", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "93144950636b40ac045d3f5585fd7a181b278226", "submitter": { "id": 2510, "url": "http://patches.dpdk.org/api/people/2510/?format=api", "name": "Sivaprasad Tummala", "email": "Sivaprasad.Tummala@amd.com" }, "delegate": { "id": 1, "url": "http://patches.dpdk.org/api/users/1/?format=api", "username": "tmonjalo", "first_name": "Thomas", "last_name": "Monjalon", "email": "thomas@monjalon.net" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20230410102149.198389-1-Sivaprasad.Tummala@amd.com/mbox/", "series": [ { "id": 27650, "url": "http://patches.dpdk.org/api/series/27650/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=27650", "date": "2023-04-10T10:21:49", "name": "[v1] power: amd power monitor support", "version": 1, "mbox": "http://patches.dpdk.org/series/27650/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/125875/comments/", "check": "fail", "checks": "http://patches.dpdk.org/api/patches/125875/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", 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BN8NAM11FT052.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "CY8PR12MB7148", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "mwaitx allows epyc processors to enter a implementation dependent\npower/performance optimized state (C1 state) for a specific period\nor until a store to the monitored address range.\n\nSigned-off-by: Sivaprasad Tummala <Sivaprasad.Tummala@amd.com>\n---\n lib/eal/include/generic/rte_cpuflags.h | 2 +\n lib/eal/x86/include/rte_cpuflags.h | 1 +\n lib/eal/x86/rte_cpuflags.c | 3 +\n lib/eal/x86/rte_power_intrinsics.c | 80 +++++++++++++++++++++++++-\n lib/power/rte_power_pmd_mgmt.c | 3 +-\n 5 files changed, 86 insertions(+), 3 deletions(-)", "diff": "diff --git a/lib/eal/include/generic/rte_cpuflags.h b/lib/eal/include/generic/rte_cpuflags.h\nindex d35551e931..db653a8dd7 100644\n--- a/lib/eal/include/generic/rte_cpuflags.h\n+++ b/lib/eal/include/generic/rte_cpuflags.h\n@@ -26,6 +26,8 @@ struct rte_cpu_intrinsics {\n \t/**< indicates support for rte_power_pause function */\n \tuint32_t power_monitor_multi : 1;\n \t/**< indicates support for rte_power_monitor_multi function */\n+\tuint32_t amd_power_monitorx : 1;\n+\t/**< indicates amd support for rte_power_monitor function */\n };\n \n /**\ndiff --git a/lib/eal/x86/include/rte_cpuflags.h b/lib/eal/x86/include/rte_cpuflags.h\nindex 92e90fb6e0..d3e608533a 100644\n--- a/lib/eal/x86/include/rte_cpuflags.h\n+++ b/lib/eal/x86/include/rte_cpuflags.h\n@@ -133,6 +133,7 @@ enum rte_cpu_flag_t {\n \tRTE_CPUFLAG_AVX512VP2INTERSECT, /**< AVX512 Two Register Intersection */\n \n \tRTE_CPUFLAG_WAITPKG, /**< UMONITOR/UMWAIT/TPAUSE */\n+\tRTE_CPUFLAG_MONITORX, /**< MONITORX */\n \n \t/* The last item */\n \tRTE_CPUFLAG_NUMFLAGS, /**< This should always be the last! */\ndiff --git a/lib/eal/x86/rte_cpuflags.c b/lib/eal/x86/rte_cpuflags.c\nindex d6b518251b..ae2e0a8470 100644\n--- a/lib/eal/x86/rte_cpuflags.c\n+++ b/lib/eal/x86/rte_cpuflags.c\n@@ -133,6 +133,7 @@ const struct feature_entry rte_cpu_feature_table[] = {\n \n \tFEAT_DEF(LAHF_SAHF, 0x80000001, 0, RTE_REG_ECX, 0)\n \tFEAT_DEF(LZCNT, 0x80000001, 0, RTE_REG_ECX, 4)\n+\tFEAT_DEF(MONITORX, 0x80000001, 0, RTE_REG_ECX, 29)\n \n \tFEAT_DEF(SYSCALL, 0x80000001, 0, RTE_REG_EDX, 11)\n \tFEAT_DEF(XD, 0x80000001, 0, RTE_REG_EDX, 20)\n@@ -191,5 +192,7 @@ rte_cpu_get_intrinsics_support(struct rte_cpu_intrinsics *intrinsics)\n \t\tintrinsics->power_pause = 1;\n \t\tif (rte_cpu_get_flag_enabled(RTE_CPUFLAG_RTM))\n \t\t\tintrinsics->power_monitor_multi = 1;\n+\t} else if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_MONITORX)) {\n+\t\tintrinsics->amd_power_monitorx = 1;\n \t}\n }\ndiff --git a/lib/eal/x86/rte_power_intrinsics.c b/lib/eal/x86/rte_power_intrinsics.c\nindex f749da9b85..4e81870387 100644\n--- a/lib/eal/x86/rte_power_intrinsics.c\n+++ b/lib/eal/x86/rte_power_intrinsics.c\n@@ -30,6 +30,7 @@ __umwait_wakeup(volatile void *addr)\n \n static bool wait_supported;\n static bool wait_multi_supported;\n+static bool amd_mwaitx_supported;\n \n static inline uint64_t\n __get_umwait_val(const volatile void *p, const uint8_t sz)\n@@ -65,6 +66,76 @@ __check_val_size(const uint8_t sz)\n \t}\n }\n \n+/**\n+ * This function uses MONITORX/MWAITX instructions and will enter C1 state.\n+ * For more information about usage of these instructions, please refer to\n+ * AMD64 Architecture Programmer’s Manual.\n+ */\n+static inline int\n+amd_power_monitorx(const struct rte_power_monitor_cond *pmc,\n+\t\tconst uint64_t tsc_timestamp)\n+{\n+\tconst unsigned int lcore_id = rte_lcore_id();\n+\tstruct power_wait_status *s;\n+\tuint64_t cur_value;\n+\n+\tRTE_SET_USED(tsc_timestamp);\n+\n+\t/* prevent non-EAL thread from using this API */\n+\tif (lcore_id >= RTE_MAX_LCORE)\n+\t\treturn -EINVAL;\n+\n+\tif (pmc == NULL)\n+\t\treturn -EINVAL;\n+\n+\tif (__check_val_size(pmc->size) < 0)\n+\t\treturn -EINVAL;\n+\n+\tif (pmc->fn == NULL)\n+\t\treturn -EINVAL;\n+\n+\ts = &wait_status[lcore_id];\n+\n+\t/* update sleep address */\n+\trte_spinlock_lock(&s->lock);\n+\ts->monitor_addr = pmc->addr;\n+\n+\t/*\n+\t * we're using raw byte codes for now as only the newest compiler\n+\t * versions support this instruction natively.\n+\t */\n+\t/* set address for MONITORX */\n+\tasm volatile(\".byte 0x0f, 0x01, 0xfa;\"\n+\t\t\t:\n+\t\t\t: \"a\"(pmc->addr),\n+\t\t\t\"c\"(0), /* no extensions */\n+\t\t\t\"d\"(0)); /* no hints */\n+\n+\t/* now that we've put this address into monitor, we can unlock */\n+\trte_spinlock_unlock(&s->lock);\n+\n+\tcur_value = __get_umwait_val(pmc->addr, pmc->size);\n+\n+\t/* check if callback indicates we should abort */\n+\tif (pmc->fn(cur_value, pmc->opaque) != 0)\n+\t\tgoto end;\n+\n+\t/* execute MWAITX */\n+\tasm volatile(\".byte 0x0f, 0x01, 0xfb;\"\n+\t\t\t: /* ignore rflags */\n+\t\t\t: \"a\"(0), /* enter C1 */\n+\t\t\t\"c\"(0), /* no time-out */\n+\t\t\t\"b\"(0));\n+\n+end:\n+\t/* erase sleep address */\n+\trte_spinlock_lock(&s->lock);\n+\ts->monitor_addr = NULL;\n+\trte_spinlock_unlock(&s->lock);\n+\n+\treturn 0;\n+}\n+\n /**\n * This function uses UMONITOR/UMWAIT instructions and will enter C0.2 state.\n * For more information about usage of these instructions, please refer to\n@@ -80,6 +151,9 @@ rte_power_monitor(const struct rte_power_monitor_cond *pmc,\n \tstruct power_wait_status *s;\n \tuint64_t cur_value;\n \n+\tif (amd_mwaitx_supported)\n+\t\treturn amd_power_monitorx(pmc, tsc_timestamp);\n+\n \t/* prevent user from running this instruction if it's not supported */\n \tif (!wait_supported)\n \t\treturn -ENOTSUP;\n@@ -126,7 +200,7 @@ rte_power_monitor(const struct rte_power_monitor_cond *pmc,\n \tasm volatile(\".byte 0xf2, 0x0f, 0xae, 0xf7;\"\n \t\t\t: /* ignore rflags */\n \t\t\t: \"D\"(0), /* enter C0.2 */\n-\t\t\t \"a\"(tsc_l), \"d\"(tsc_h));\n+\t\t\t\"a\"(tsc_l), \"d\"(tsc_h));\n \n end:\n \t/* erase sleep address */\n@@ -170,6 +244,8 @@ RTE_INIT(rte_power_intrinsics_init) {\n \t\twait_supported = 1;\n \tif (i.power_monitor_multi)\n \t\twait_multi_supported = 1;\n+\tif (i.amd_power_monitorx)\n+\t\tamd_mwaitx_supported = 1;\n }\n \n int\n@@ -178,7 +254,7 @@ rte_power_monitor_wakeup(const unsigned int lcore_id)\n \tstruct power_wait_status *s;\n \n \t/* prevent user from running this instruction if it's not supported */\n-\tif (!wait_supported)\n+\tif (!wait_supported && !amd_mwaitx_supported)\n \t\treturn -ENOTSUP;\n \n \t/* prevent buffer overrun */\ndiff --git a/lib/power/rte_power_pmd_mgmt.c b/lib/power/rte_power_pmd_mgmt.c\nindex ca1840387c..43971e6014 100644\n--- a/lib/power/rte_power_pmd_mgmt.c\n+++ b/lib/power/rte_power_pmd_mgmt.c\n@@ -447,7 +447,8 @@ check_monitor(struct pmd_core_cfg *cfg, const union queue *qdata)\n \tbool multimonitor_supported;\n \n \t/* check if rte_power_monitor is supported */\n-\tif (!global_data.intrinsics_support.power_monitor) {\n+\tif ((!global_data.intrinsics_support.power_monitor) &&\n+\t (!global_data.intrinsics_support.amd_power_monitorx)) {\n \t\tRTE_LOG(DEBUG, POWER, \"Monitoring intrinsics are not supported\\n\");\n \t\treturn -ENOTSUP;\n \t}\n", "prefixes": [ "v1" ] }