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GET /api/patches/125805/?format=api
{ "id": 125805, "url": "http://patches.dpdk.org/api/patches/125805/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20230405142537.1899973-5-sedara@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20230405142537.1899973-5-sedara@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20230405142537.1899973-5-sedara@marvell.com", "date": "2023-04-05T14:25:30", "name": "[v2,04/10] net/octeon_ep: support IQ/OQ reset", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": true, "hash": "5ab293c6f982536563a79f234657ccfa347ffe19", "submitter": { "id": 2729, "url": "http://patches.dpdk.org/api/people/2729/?format=api", "name": "Sathesh B Edara", "email": "sedara@marvell.com" }, "delegate": { "id": 310, "url": "http://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20230405142537.1899973-5-sedara@marvell.com/mbox/", "series": [ { "id": 27627, "url": "http://patches.dpdk.org/api/series/27627/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=27627", "date": "2023-04-05T14:25:26", "name": "extend octeon ep driver functionality", "version": 2, "mbox": "http://patches.dpdk.org/series/27627/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/125805/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/125805/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id C1979428D4;\n\tWed, 5 Apr 2023 16:26:13 +0200 (CEST)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 5846B42D20;\n\tWed, 5 Apr 2023 16:25:52 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n [67.231.156.173])\n by mails.dpdk.org (Postfix) with ESMTP id 9829C42D1A\n for <dev@dpdk.org>; Wed, 5 Apr 2023 16:25:50 +0200 (CEST)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n by mx0b-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id\n 335DWaJt017817 for <dev@dpdk.org>; Wed, 5 Apr 2023 07:25:50 -0700", "from dc5-exch02.marvell.com ([199.233.59.182])\n by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3prpnd5gs4-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Wed, 05 Apr 2023 07:25:49 -0700", "from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.48;\n Wed, 5 Apr 2023 07:25:47 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.48 via Frontend\n Transport; Wed, 5 Apr 2023 07:25:47 -0700", "from localhost.marvell.com (unknown [10.106.27.249])\n by maili.marvell.com (Postfix) with ESMTP id 07CFE3F7050;\n Wed, 5 Apr 2023 07:25:47 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-transfer-encoding : content-type; s=pfpt0220;\n bh=TpTMwiJP9UNePM1F0wLKTKPTUSz5UzsdAs3a4mwhEio=;\n b=JpTI3IUwEzebNY2N8gP6r3VMWrQB/YNhXi+mb7e7kb98Nw/+RMlqabTX/pb5wgoU0+KL\n BIN5eElljx82zw7KdNL05MgHxe2GRKhxb8az0rrnVqIvkfmrBpwmP0O8086mb2meEfaJ\n nWrtYb4AMnedtVPf/GjG117f1YPwKEZHww1GVJFbVsI6C7P0NfatXY+cHvs4wOEeUDl/\n S511gsShClggCbWASehzV42AiwwCl2LsaYgyloxLHMh2OPboJsMtiq4G0AfiMp/6qjcV\n f/8cZfcAyTOX1nRQy3QvvxkCORL5IGWtWkIlSMCuOX05Qv2mjLQE5eGuzfibcqzO95iR tg==", "From": "Sathesh Edara <sedara@marvell.com>", "To": "<sburla@marvell.com>, <jerinj@marvell.com>, <sedara@marvell.com>, \"Radha\n Mohan Chintakuntla\" <radhac@marvell.com>, Veerasenareddy Burru\n <vburru@marvell.com>", "CC": "<dev@dpdk.org>", "Subject": "[PATCH v2 04/10] net/octeon_ep: support IQ/OQ reset", "Date": "Wed, 5 Apr 2023 07:25:30 -0700", "Message-ID": "<20230405142537.1899973-5-sedara@marvell.com>", "X-Mailer": "git-send-email 2.31.1", "In-Reply-To": "<20230405142537.1899973-1-sedara@marvell.com>", "References": "<20230404141855.1025625-2-sedara@marvell.com>\n <20230405142537.1899973-1-sedara@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-ORIG-GUID": "LLf7rDcRj8wcLrUkIfA8CWB4sRcaXyit", "X-Proofpoint-GUID": "LLf7rDcRj8wcLrUkIfA8CWB4sRcaXyit", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.254,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22\n definitions=2023-04-05_09,2023-04-05_01,2023-02-09_01", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "This patch adds input and output queue reset\nfunctionality, also receive queue interrupt\nenable and disable functionality.\n\nSigned-off-by: Sathesh Edara <sedara@marvell.com>\n---\n drivers/net/octeon_ep/otx2_ep_vf.c | 193 +++++++++++++++++++++++++-\n drivers/net/octeon_ep/otx2_ep_vf.h | 61 ++++++--\n drivers/net/octeon_ep/otx_ep_common.h | 5 +-\n 3 files changed, 244 insertions(+), 15 deletions(-)", "diff": "diff --git a/drivers/net/octeon_ep/otx2_ep_vf.c b/drivers/net/octeon_ep/otx2_ep_vf.c\nindex 3ffc7275c7..3e4895862b 100644\n--- a/drivers/net/octeon_ep/otx2_ep_vf.c\n+++ b/drivers/net/octeon_ep/otx2_ep_vf.c\n@@ -9,6 +9,117 @@\n #include \"otx_ep_common.h\"\n #include \"otx2_ep_vf.h\"\n \n+static int otx2_vf_enable_rxq_intr(struct otx_ep_device *otx_epvf,\n+\t\t\t\t uint16_t q_no);\n+\n+static int\n+otx2_vf_reset_iq(struct otx_ep_device *otx_ep, int q_no)\n+{\n+\tint loop = SDP_VF_BUSY_LOOP_COUNT;\n+\tvolatile uint64_t d64 = 0ull;\n+\n+\t/* There is no RST for a ring.\n+\t * Clear all registers one by one after disabling the ring\n+\t */\n+\n+\totx2_write64(d64, otx_ep->hw_addr + SDP_VF_R_IN_ENABLE(q_no));\n+\totx2_write64(d64, otx_ep->hw_addr + SDP_VF_R_IN_INSTR_BADDR(q_no));\n+\totx2_write64(d64, otx_ep->hw_addr + SDP_VF_R_IN_INSTR_RSIZE(q_no));\n+\n+\td64 = 0xFFFFFFFF; /* ~0ull */\n+\totx2_write64(d64, otx_ep->hw_addr + SDP_VF_R_IN_INSTR_DBELL(q_no));\n+\td64 = otx2_read64(otx_ep->hw_addr + SDP_VF_R_IN_INSTR_DBELL(q_no));\n+\n+\twhile ((d64 != 0) && loop--) {\n+\t\trte_delay_ms(1);\n+\t\td64 = otx2_read64(otx_ep->hw_addr +\n+\t\t\t\t SDP_VF_R_IN_INSTR_DBELL(q_no));\n+\t}\n+\tif (loop < 0) {\n+\t\totx_ep_err(\"%s: doorbell init retry limit exceeded.\\n\", __func__);\n+\t\treturn -EIO;\n+\t}\n+\n+\tloop = SDP_VF_BUSY_LOOP_COUNT;\n+\tdo {\n+\t\td64 = otx2_read64(otx_ep->hw_addr + SDP_VF_R_IN_CNTS(q_no));\n+\t\totx2_write64(d64, otx_ep->hw_addr + SDP_VF_R_IN_CNTS(q_no));\n+\t\trte_delay_ms(1);\n+\t} while ((d64 & ~SDP_VF_R_IN_CNTS_OUT_INT) != 0 && loop--);\n+\tif (loop < 0) {\n+\t\totx_ep_err(\"%s: in_cnts init retry limit exceeded.\\n\", __func__);\n+\t\treturn -EIO;\n+\t}\n+\n+\td64 = 0ull;\n+\totx2_write64(d64, otx_ep->hw_addr + SDP_VF_R_IN_INT_LEVELS(q_no));\n+\totx2_write64(d64, otx_ep->hw_addr + SDP_VF_R_IN_PKT_CNT(q_no));\n+\totx2_write64(d64, otx_ep->hw_addr + SDP_VF_R_IN_BYTE_CNT(q_no));\n+\n+\treturn 0;\n+}\n+\n+static int\n+otx2_vf_reset_oq(struct otx_ep_device *otx_ep, int q_no)\n+{\n+\tint loop = SDP_VF_BUSY_LOOP_COUNT;\n+\tvolatile uint64_t d64 = 0ull;\n+\n+\totx2_write64(d64, otx_ep->hw_addr + SDP_VF_R_OUT_ENABLE(q_no));\n+\n+\totx2_write64(d64, otx_ep->hw_addr + SDP_VF_R_OUT_SLIST_BADDR(q_no));\n+\n+\totx2_write64(d64, otx_ep->hw_addr + SDP_VF_R_OUT_SLIST_RSIZE(q_no));\n+\n+\td64 = 0xFFFFFFFF;\n+\totx2_write64(d64, otx_ep->hw_addr + SDP_VF_R_OUT_SLIST_DBELL(q_no));\n+\td64 = otx2_read64(otx_ep->hw_addr + SDP_VF_R_OUT_SLIST_DBELL(q_no));\n+\twhile ((d64 != 0) && loop--) {\n+\t\trte_delay_ms(1);\n+\t\td64 = otx2_read64(otx_ep->hw_addr +\n+\t\t\t\t SDP_VF_R_OUT_SLIST_DBELL(q_no));\n+\t}\n+\tif (loop < 0) {\n+\t\totx_ep_err(\"%s: doorbell init retry limit exceeded.\\n\", __func__);\n+\t\treturn -EIO;\n+\t}\n+\n+\tif (otx2_read64(otx_ep->hw_addr + SDP_VF_R_OUT_CNTS(q_no))\n+\t & SDP_VF_R_OUT_CNTS_OUT_INT) {\n+\t\t/*\n+\t\t * The OUT_INT bit is set. This interrupt must be enabled in\n+\t\t * order to clear the interrupt. Interrupts are disabled\n+\t\t * at the end of this function.\n+\t\t */\n+\t\tunion out_int_lvl_t out_int_lvl;\n+\n+\t\tout_int_lvl.d64 = otx2_read64(otx_ep->hw_addr +\n+\t\t\t\t\tSDP_VF_R_OUT_INT_LEVELS(q_no));\n+\t\tout_int_lvl.s.time_cnt_en = 1;\n+\t\tout_int_lvl.s.cnt = 0;\n+\t\totx2_write64(out_int_lvl.d64, otx_ep->hw_addr +\n+\t\t\t\tSDP_VF_R_OUT_INT_LEVELS(q_no));\n+\t}\n+\n+\tloop = SDP_VF_BUSY_LOOP_COUNT;\n+\tdo {\n+\t\td64 = otx2_read64(otx_ep->hw_addr + SDP_VF_R_OUT_CNTS(q_no));\n+\t\totx2_write64(d64, otx_ep->hw_addr + SDP_VF_R_OUT_CNTS(q_no));\n+\t\trte_delay_ms(1);\n+\t} while ((d64 & ~SDP_VF_R_OUT_CNTS_IN_INT) != 0 && loop--);\n+\tif (loop < 0) {\n+\t\totx_ep_err(\"%s: out_cnts init retry limit exceeded.\\n\", __func__);\n+\t\treturn -EIO;\n+\t}\n+\n+\td64 = 0ull;\n+\totx2_write64(d64, otx_ep->hw_addr + SDP_VF_R_OUT_INT_LEVELS(q_no));\n+\totx2_write64(d64, otx_ep->hw_addr + SDP_VF_R_OUT_PKT_CNT(q_no));\n+\totx2_write64(d64, otx_ep->hw_addr + SDP_VF_R_OUT_BYTE_CNT(q_no));\n+\n+\treturn 0;\n+}\n+\n static void\n otx2_vf_setup_global_iq_reg(struct otx_ep_device *otx_ep, int q_no)\n {\n@@ -49,24 +160,63 @@ otx2_vf_setup_global_oq_reg(struct otx_ep_device *otx_ep, int q_no)\n \toct_ep_write64(reg_val, otx_ep->hw_addr + SDP_VF_R_OUT_CONTROL(q_no));\n }\n \n+static int\n+otx2_vf_reset_input_queues(struct otx_ep_device *otx_ep)\n+{\n+\tuint32_t q_no = 0;\n+\tint ret = 0;\n+\n+\tfor (q_no = 0; q_no < otx_ep->sriov_info.rings_per_vf; q_no++) {\n+\t\tret = otx2_vf_reset_iq(otx_ep, q_no);\n+\t\tif (ret)\n+\t\t\treturn ret;\n+\t}\n+\n+\treturn ret;\n+}\n+\n+static int\n+otx2_vf_reset_output_queues(struct otx_ep_device *otx_ep)\n+{\n+\tuint64_t q_no = 0ull;\n+\tint ret = 0;\n+\n+\tfor (q_no = 0; q_no < otx_ep->sriov_info.rings_per_vf; q_no++) {\n+\t\tret = otx2_vf_reset_oq(otx_ep, q_no);\n+\t\tif (ret)\n+\t\t\treturn ret;\n+\t}\n+\n+\treturn ret;\n+}\n+\n static int\n otx2_vf_setup_global_input_regs(struct otx_ep_device *otx_ep)\n {\n \tuint64_t q_no = 0ull;\n+\tint ret = 0;\n+\n+\tret = otx2_vf_reset_input_queues(otx_ep);\n+\tif (ret)\n+\t\treturn ret;\n \n \tfor (q_no = 0; q_no < (otx_ep->sriov_info.rings_per_vf); q_no++)\n \t\totx2_vf_setup_global_iq_reg(otx_ep, q_no);\n-\treturn 0;\n+\treturn ret;\n }\n \n static int\n otx2_vf_setup_global_output_regs(struct otx_ep_device *otx_ep)\n {\n \tuint32_t q_no;\n+\tint ret = 0;\n \n+\tret = otx2_vf_reset_output_queues(otx_ep);\n+\tif (ret)\n+\t\treturn ret;\n \tfor (q_no = 0; q_no < (otx_ep->sriov_info.rings_per_vf); q_no++)\n \t\totx2_vf_setup_global_oq_reg(otx_ep, q_no);\n-\treturn 0;\n+\treturn ret;\n }\n \n static int\n@@ -181,8 +331,8 @@ otx2_vf_setup_oq_regs(struct otx_ep_device *otx_ep, uint32_t oq_no)\n \trte_write64(OTX_EP_CLEAR_SDP_OUT_PKT_CNT, (uint8_t *)otx_ep->hw_addr +\n \t\t SDP_VF_R_OUT_PKT_CNT(oq_no));\n \n-\tloop = OTX_EP_BUSY_LOOP_COUNT;\n \t/* Clear the OQ doorbell */\n+\tloop = OTX_EP_BUSY_LOOP_COUNT;\n \trte_write32(OTX_EP_CLEAR_SLIST_DBELL, droq->pkts_credit_reg);\n \twhile ((rte_read32(droq->pkts_credit_reg) != 0ull) && loop--) {\n \t\trte_write32(OTX_EP_CLEAR_SLIST_DBELL, droq->pkts_credit_reg);\n@@ -344,6 +494,40 @@ otx2_ep_get_defconf(struct otx_ep_device *otx_ep_dev __rte_unused)\n \treturn default_conf;\n }\n \n+static int otx2_vf_enable_rxq_intr(struct otx_ep_device *otx_epvf,\n+\t\t\t\t uint16_t q_no)\n+{\n+\tunion out_int_lvl_t out_int_lvl;\n+\tunion out_cnts_t out_cnts;\n+\n+\tout_int_lvl.d64 = otx2_read64(otx_epvf->hw_addr +\n+\t\t\t\tSDP_VF_R_OUT_INT_LEVELS(q_no));\n+\tout_int_lvl.s.time_cnt_en = 1;\n+\tout_int_lvl.s.cnt = 0;\n+\totx2_write64(out_int_lvl.d64, otx_epvf->hw_addr +\n+\t\t\tSDP_VF_R_OUT_INT_LEVELS(q_no));\n+\tout_cnts.d64 = 0;\n+\tout_cnts.s.resend = 1;\n+\totx2_write64(out_cnts.d64, otx_epvf->hw_addr + SDP_VF_R_OUT_CNTS(q_no));\n+\treturn 0;\n+}\n+\n+static int otx2_vf_disable_rxq_intr(struct otx_ep_device *otx_epvf,\n+\t\t\t\t uint16_t q_no)\n+{\n+\tunion out_int_lvl_t out_int_lvl;\n+\n+\t/* Disable the interrupt for this queue */\n+\tout_int_lvl.d64 = otx2_read64(otx_epvf->hw_addr +\n+\t\t\t\tSDP_VF_R_OUT_INT_LEVELS(q_no));\n+\tout_int_lvl.s.time_cnt_en = 0;\n+\tout_int_lvl.s.cnt = 0;\n+\totx2_write64(out_int_lvl.d64, otx_epvf->hw_addr +\n+\t\t\tSDP_VF_R_OUT_INT_LEVELS(q_no));\n+\n+\treturn 0;\n+}\n+\n int\n otx2_ep_vf_setup_device(struct otx_ep_device *otx_ep)\n {\n@@ -381,5 +565,8 @@ otx2_ep_vf_setup_device(struct otx_ep_device *otx_ep)\n \totx_ep->fn_list.enable_oq = otx2_vf_enable_oq;\n \totx_ep->fn_list.disable_oq = otx2_vf_disable_oq;\n \n+\totx_ep->fn_list.enable_rxq_intr = otx2_vf_enable_rxq_intr;\n+\totx_ep->fn_list.disable_rxq_intr = otx2_vf_disable_rxq_intr;\n+\n \treturn 0;\n }\ndiff --git a/drivers/net/octeon_ep/otx2_ep_vf.h b/drivers/net/octeon_ep/otx2_ep_vf.h\nindex 8f00acd737..36c0b25dea 100644\n--- a/drivers/net/octeon_ep/otx2_ep_vf.h\n+++ b/drivers/net/octeon_ep/otx2_ep_vf.h\n@@ -14,17 +14,20 @@\n #define SDP_VF_BUSY_LOOP_COUNT (10000)\n \n /* SDP VF OQ Masks */\n-#define SDP_VF_R_OUT_CTL_IDLE (1ull << 40)\n-#define SDP_VF_R_OUT_CTL_ES_I (1ull << 34)\n-#define SDP_VF_R_OUT_CTL_NSR_I (1ull << 33)\n-#define SDP_VF_R_OUT_CTL_ROR_I (1ull << 32)\n-#define SDP_VF_R_OUT_CTL_ES_D (1ull << 30)\n-#define SDP_VF_R_OUT_CTL_NSR_D (1ull << 29)\n-#define SDP_VF_R_OUT_CTL_ROR_D (1ull << 28)\n-#define SDP_VF_R_OUT_CTL_ES_P (1ull << 26)\n-#define SDP_VF_R_OUT_CTL_NSR_P (1ull << 25)\n-#define SDP_VF_R_OUT_CTL_ROR_P (1ull << 24)\n-#define SDP_VF_R_OUT_CTL_IMODE (1ull << 23)\n+#define SDP_VF_R_OUT_CTL_IDLE (0x1ull << 40)\n+#define SDP_VF_R_OUT_CTL_ES_I (0x1ull << 34)\n+#define SDP_VF_R_OUT_CTL_NSR_I (0x1ull << 33)\n+#define SDP_VF_R_OUT_CTL_ROR_I (0x1ull << 32)\n+#define SDP_VF_R_OUT_CTL_ES_D (0x1ull << 30)\n+#define SDP_VF_R_OUT_CTL_NSR_D (0x1ull << 29)\n+#define SDP_VF_R_OUT_CTL_ROR_D (0x1ull << 28)\n+#define SDP_VF_R_OUT_CTL_ES_P (0x1ull << 26)\n+#define SDP_VF_R_OUT_CTL_NSR_P (0x1ull << 25)\n+#define SDP_VF_R_OUT_CTL_ROR_P (0x1ull << 24)\n+#define SDP_VF_R_OUT_CTL_IMODE (0x1ull << 23)\n+#define SDP_VF_R_OUT_CNTS_OUT_INT (0x1ull << 62)\n+#define SDP_VF_R_OUT_CNTS_IN_INT (0x1ull << 61)\n+#define SDP_VF_R_IN_CNTS_OUT_INT (0x1ull << 62)\n \n /* SDP VF Register definitions */\n #define SDP_VF_RING_OFFSET (0x1ull << 17)\n@@ -140,4 +143,40 @@ struct otx2_ep_instr_64B {\n \tuint64_t exhdr[4];\n };\n \n+union out_int_lvl_t {\n+\tuint64_t d64;\n+\tstruct {\n+\t\tuint64_t cnt:32;\n+\t\tuint64_t timet:22;\n+\t\tuint64_t max_len:7;\n+\t\tuint64_t max_len_en:1;\n+\t\tuint64_t time_cnt_en:1;\n+\t\tuint64_t bmode:1;\n+\t} s;\n+};\n+\n+union out_cnts_t {\n+\tuint64_t d64;\n+\tstruct {\n+\t\tuint64_t cnt:32;\n+\t\tuint64_t timer:22;\n+\t\tuint64_t rsvd:5;\n+\t\tuint64_t resend:1;\n+\t\tuint64_t mbox_int:1;\n+\t\tuint64_t in_int:1;\n+\t\tuint64_t out_int:1;\n+\t\tuint64_t send_ism:1;\n+\t} s;\n+};\n+\n+#define OTX2_EP_64B_INSTR_SIZE\t(sizeof(otx2_ep_instr_64B))\n+\n+#define NIX_MAX_HW_FRS\t\t\t9212\n+#define NIX_MAX_VTAG_INS\t\t2\n+#define NIX_MAX_VTAG_ACT_SIZE\t\t(4 * NIX_MAX_VTAG_INS)\n+#define NIX_MAX_FRS\t\\\n+\t(NIX_MAX_HW_FRS + RTE_ETHER_CRC_LEN - NIX_MAX_VTAG_ACT_SIZE)\n+\n+#define CN93XX_INTR_R_OUT_INT (1ULL << 62)\n+#define CN93XX_INTR_R_IN_INT (1ULL << 61)\n #endif /*_OTX2_EP_VF_H_ */\ndiff --git a/drivers/net/octeon_ep/otx_ep_common.h b/drivers/net/octeon_ep/otx_ep_common.h\nindex 479bb1a1a0..a3260d5243 100644\n--- a/drivers/net/octeon_ep/otx_ep_common.h\n+++ b/drivers/net/octeon_ep/otx_ep_common.h\n@@ -408,6 +408,9 @@ struct otx_ep_fn_list {\n \n \tint (*enable_oq)(struct otx_ep_device *otx_ep, uint32_t q_no);\n \tvoid (*disable_oq)(struct otx_ep_device *otx_ep, uint32_t q_no);\n+\n+\tint (*enable_rxq_intr)(struct otx_ep_device *otx_epvf, uint16_t q_no);\n+\tint (*disable_rxq_intr)(struct otx_ep_device *otx_epvf, uint16_t q_no);\n };\n \n /* OTX_EP EP VF device data structure */\n@@ -498,7 +501,7 @@ struct otx_ep_buf_free_info {\n \tstruct otx_ep_gather g;\n };\n \n-#define OTX_EP_MAX_PKT_SZ 64000U\n+#define OTX_EP_MAX_PKT_SZ 65498U\n #define OTX_EP_MAX_MAC_ADDRS 1\n #define OTX_EP_SG_ALIGN 8\n #define OTX_EP_CLEAR_ISIZE_BSIZE 0x7FFFFFULL\n", "prefixes": [ "v2", "04/10" ] }