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GET /api/patches/125651/?format=api
{ "id": 125651, "url": "http://patches.dpdk.org/api/patches/125651/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20230331022258.382085-3-simei.su@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20230331022258.382085-3-simei.su@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20230331022258.382085-3-simei.su@intel.com", "date": "2023-03-31T02:22:56", "name": "[RFC,2/4] net/ice: add frequency adjustment support for PTP", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "eac192216f79df9b752c704c9d148f6a48fd6983", "submitter": { "id": 1298, "url": "http://patches.dpdk.org/api/people/1298/?format=api", "name": "Simei Su", "email": "simei.su@intel.com" }, "delegate": { "id": 1540, "url": "http://patches.dpdk.org/api/users/1540/?format=api", "username": "qzhan15", "first_name": "Qi", "last_name": "Zhang", "email": "qi.z.zhang@intel.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20230331022258.382085-3-simei.su@intel.com/mbox/", "series": [ { "id": 27588, "url": "http://patches.dpdk.org/api/series/27588/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=27588", "date": "2023-03-31T02:22:54", "name": "add frequency adjustment support for PTP", "version": 1, "mbox": "http://patches.dpdk.org/series/27588/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/125651/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/125651/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id E13624287D;\n\tFri, 31 Mar 2023 04:24:51 +0200 (CEST)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 0051542C54;\n\tFri, 31 Mar 2023 04:24:42 +0200 (CEST)", "from mga07.intel.com (mga07.intel.com [134.134.136.100])\n by mails.dpdk.org (Postfix) with ESMTP id 3E94D4282D\n for <dev@dpdk.org>; Fri, 31 Mar 2023 04:24:41 +0200 (CEST)", "from orsmga007.jf.intel.com ([10.7.209.58])\n by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 30 Mar 2023 19:24:40 -0700", "from unknown (HELO npg-dpdk-simeisu-cvl-119d218.sh.intel.com)\n ([10.67.119.208])\n by orsmga007.jf.intel.com with ESMTP; 30 Mar 2023 19:24:38 -0700" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1680229481; x=1711765481;\n h=from:to:cc:subject:date:message-id:in-reply-to: references;\n bh=cBwWlJKELDQZMZUpZzeT1vHVeLAaXFy8bC4c+RzBkGE=;\n b=Un0XIRXi7cTmPyu7drWFNf7oiEzQP3pgr/xwDse8cDraDDlnioehDvJk\n CI3xq9zGP0DcdgkR8ZwzVyt/Qi5qztvHnAsWJBPJCyyLsV+XwbF5MJ277\n rQA1BwChPcZo0k2Clc8BAK8v3rj/AO78T76Nu4s34t+y0ZOuctGbeeWKn\n kukF2gGb+O7bY9goNBr0PnomOQtZB0N970MR+3ojRpk4O5RvSlicpJOHR\n 9E12Ke4ggXqtf7enHiHCwr1WIx2pl4SETPaP8AOs+WvQaS77ma+BtWy5p\n cVdlks2sCbheAzsB+nIh4848uj/WqKfUXHxk1x4KMiuWkMNAekCudrq5l g==;", "X-IronPort-AV": [ "E=McAfee;i=\"6600,9927,10665\"; a=\"406339268\"", "E=Sophos;i=\"5.98,306,1673942400\"; d=\"scan'208\";a=\"406339268\"", "E=McAfee;i=\"6600,9927,10665\"; a=\"678419756\"", "E=Sophos;i=\"5.98,306,1673942400\"; d=\"scan'208\";a=\"678419756\"" ], "X-ExtLoop1": "1", "From": "Simei Su <simei.su@intel.com>", "To": "thomas@monjalon.net, ferruh.yigit@amd.com, andrew.rybchenko@oktetlabs.ru,\n kirill.rybalchenko@intel.com, qi.z.zhang@intel.com", "Cc": "dev@dpdk.org,\n\twenjun1.wu@intel.com,\n\tSimei Su <simei.su@intel.com>", "Subject": "[RFC 2/4] net/ice: add frequency adjustment support for PTP", "Date": "Fri, 31 Mar 2023 10:22:56 +0800", "Message-Id": "<20230331022258.382085-3-simei.su@intel.com>", "X-Mailer": "git-send-email 2.9.5", "In-Reply-To": "<20230331022258.382085-1-simei.su@intel.com>", "References": "<20230331022258.382085-1-simei.su@intel.com>", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Add ice support for new ethdev API to adjust frequency for IEEE1588\nPTP. Also, this patch reworks code for converting software update\nto hardware update.\n\nSigned-off-by: Simei Su <simei.su@intel.com>\n---\n drivers/net/ice/ice_ethdev.c | 111 ++++++++++++++++++++++++++++---------------\n 1 file changed, 72 insertions(+), 39 deletions(-)", "diff": "diff --git a/drivers/net/ice/ice_ethdev.c b/drivers/net/ice/ice_ethdev.c\nindex 9a88cf9..fa4d840 100644\n--- a/drivers/net/ice/ice_ethdev.c\n+++ b/drivers/net/ice/ice_ethdev.c\n@@ -158,6 +158,7 @@ static int ice_timesync_read_rx_timestamp(struct rte_eth_dev *dev,\n static int ice_timesync_read_tx_timestamp(struct rte_eth_dev *dev,\n \t\t\t\t\t struct timespec *timestamp);\n static int ice_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);\n+static int ice_timesync_adjust_freq(struct rte_eth_dev *dev, int64_t ppm);\n static int ice_timesync_read_time(struct rte_eth_dev *dev,\n \t\t\t\t struct timespec *timestamp);\n static int ice_timesync_write_time(struct rte_eth_dev *dev,\n@@ -274,6 +275,7 @@ static const struct eth_dev_ops ice_eth_dev_ops = {\n \t.timesync_read_rx_timestamp = ice_timesync_read_rx_timestamp,\n \t.timesync_read_tx_timestamp = ice_timesync_read_tx_timestamp,\n \t.timesync_adjust_time = ice_timesync_adjust_time,\n+\t.timesync_adjust_freq = ice_timesync_adjust_freq,\n \t.timesync_read_time = ice_timesync_read_time,\n \t.timesync_write_time = ice_timesync_write_time,\n \t.timesync_disable = ice_timesync_disable,\n@@ -5840,23 +5842,6 @@ ice_timesync_enable(struct rte_eth_dev *dev)\n \t\t}\n \t}\n \n-\t/* Initialize cycle counters for system time/RX/TX timestamp */\n-\tmemset(&ad->systime_tc, 0, sizeof(struct rte_timecounter));\n-\tmemset(&ad->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));\n-\tmemset(&ad->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));\n-\n-\tad->systime_tc.cc_mask = ICE_CYCLECOUNTER_MASK;\n-\tad->systime_tc.cc_shift = 0;\n-\tad->systime_tc.nsec_mask = 0;\n-\n-\tad->rx_tstamp_tc.cc_mask = ICE_CYCLECOUNTER_MASK;\n-\tad->rx_tstamp_tc.cc_shift = 0;\n-\tad->rx_tstamp_tc.nsec_mask = 0;\n-\n-\tad->tx_tstamp_tc.cc_mask = ICE_CYCLECOUNTER_MASK;\n-\tad->tx_tstamp_tc.cc_shift = 0;\n-\tad->tx_tstamp_tc.nsec_mask = 0;\n-\n \tad->ptp_ena = 1;\n \n \treturn 0;\n@@ -5871,14 +5856,13 @@ ice_timesync_read_rx_timestamp(struct rte_eth_dev *dev,\n \t\t\tICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);\n \tstruct ice_rx_queue *rxq;\n \tuint32_t ts_high;\n-\tuint64_t ts_ns, ns;\n+\tuint64_t ts_ns;\n \n \trxq = dev->data->rx_queues[flags];\n \n \tts_high = rxq->time_high;\n \tts_ns = ice_tstamp_convert_32b_64b(hw, ad, 1, ts_high);\n-\tns = rte_timecounter_update(&ad->rx_tstamp_tc, ts_ns);\n-\t*timestamp = rte_ns_to_timespec(ns);\n+\t*timestamp = rte_ns_to_timespec(ts_ns);\n \n \treturn 0;\n }\n@@ -5891,7 +5875,7 @@ ice_timesync_read_tx_timestamp(struct rte_eth_dev *dev,\n \tstruct ice_adapter *ad =\n \t\t\tICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);\n \tuint8_t lport;\n-\tuint64_t ts_ns, ns, tstamp;\n+\tuint64_t ts_ns, tstamp;\n \tconst uint64_t mask = 0xFFFFFFFF;\n \tint ret;\n \n@@ -5904,8 +5888,7 @@ ice_timesync_read_tx_timestamp(struct rte_eth_dev *dev,\n \t}\n \n \tts_ns = ice_tstamp_convert_32b_64b(hw, ad, 1, (tstamp >> 8) & mask);\n-\tns = rte_timecounter_update(&ad->tx_tstamp_tc, ts_ns);\n-\t*timestamp = rte_ns_to_timespec(ns);\n+\t*timestamp = rte_ns_to_timespec(ts_ns);\n \n \treturn 0;\n }\n@@ -5913,12 +5896,66 @@ ice_timesync_read_tx_timestamp(struct rte_eth_dev *dev,\n static int\n ice_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)\n {\n-\tstruct ice_adapter *ad =\n-\t\t\tICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);\n+\tstruct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n+\tuint8_t tmr_idx = hw->func_caps.ts_func_info.tmr_index_assoc;\n+\tuint32_t lo, lo2, hi;\n+\tuint64_t time, ns;\n+\tint ret;\n+\n+\tif (delta > INT32_MAX || delta < INT32_MIN) {\n+\t\tlo = ICE_READ_REG(hw, GLTSYN_TIME_L(tmr_idx));\n+\t\thi = ICE_READ_REG(hw, GLTSYN_TIME_H(tmr_idx));\n+\t\tlo2 = ICE_READ_REG(hw, GLTSYN_TIME_L(tmr_idx));\n+\n+\t\tif (lo2 < lo) {\n+\t\t\tlo = ICE_READ_REG(hw, GLTSYN_TIME_L(tmr_idx));\n+\t\t\thi = ICE_READ_REG(hw, GLTSYN_TIME_H(tmr_idx));\n+\t\t}\n+\n+\t\ttime = ((uint64_t)hi << 32) | lo;\n+\t\tns = time + delta;\n+\n+\t\treturn ice_ptp_init_time(hw, ns);\n+\t}\n+\n+\tret = ice_ptp_adj_clock(hw, delta, true);\n+\tif (ret)\n+\t\treturn -1;\n+\n+\treturn 0;\n+}\n \n-\tad->systime_tc.nsec += delta;\n-\tad->rx_tstamp_tc.nsec += delta;\n-\tad->tx_tstamp_tc.nsec += delta;\n+#define DEFAULT_INCVAL_E810 0x13b13b13bULL\n+static int\n+ice_timesync_adjust_freq(struct rte_eth_dev *dev, int64_t ppm)\n+{\n+\tuint64_t freq, divisor = 1000000ULL;\n+\tstruct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n+\tint64_t incval = DEFAULT_INCVAL_E810, diff;\n+\tint neg_adj = 0;\n+\tint ret;\n+\n+\tif (ppm < 0) {\n+\t\tneg_adj = 1;\n+\t\tppm = -ppm;\n+\t}\n+\n+\twhile ((uint64_t)ppm > UINT64_MAX / incval) {\n+\t\tppm >>= 2;\n+\t\tdivisor >>= 2;\n+\t}\n+\n+\tfreq = (incval * (uint64_t)ppm) >> 16;\n+\tdiff = freq / divisor;\n+\n+\tif (neg_adj)\n+\t\tincval -= diff;\n+\telse\n+\t\tincval += diff;\n+\n+\tret = ice_ptp_write_incval_locked(hw, incval);\n+\tif (ret)\n+\t\treturn -1;\n \n \treturn 0;\n }\n@@ -5926,15 +5963,14 @@ ice_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)\n static int\n ice_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)\n {\n-\tstruct ice_adapter *ad =\n-\t\t\tICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);\n+\tstruct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n \tuint64_t ns;\n+\tint ret;\n \n \tns = rte_timespec_to_ns(ts);\n-\n-\tad->systime_tc.nsec = ns;\n-\tad->rx_tstamp_tc.nsec = ns;\n-\tad->tx_tstamp_tc.nsec = ns;\n+\tret = ice_ptp_init_time(hw, ns);\n+\tif (ret)\n+\t\treturn -1;\n \n \treturn 0;\n }\n@@ -5943,11 +5979,9 @@ static int\n ice_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)\n {\n \tstruct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n-\tstruct ice_adapter *ad =\n-\t\t\tICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);\n \tuint8_t tmr_idx = hw->func_caps.ts_func_info.tmr_index_assoc;\n \tuint32_t hi, lo, lo2;\n-\tuint64_t time, ns;\n+\tuint64_t time;\n \n \tlo = ICE_READ_REG(hw, GLTSYN_TIME_L(tmr_idx));\n \thi = ICE_READ_REG(hw, GLTSYN_TIME_H(tmr_idx));\n@@ -5959,8 +5993,7 @@ ice_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)\n \t}\n \n \ttime = ((uint64_t)hi << 32) | lo;\n-\tns = rte_timecounter_update(&ad->systime_tc, time);\n-\t*ts = rte_ns_to_timespec(ns);\n+\t*ts = rte_ns_to_timespec(time);\n \n \treturn 0;\n }\n", "prefixes": [ "RFC", "2/4" ] }