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GET /api/patches/12557/?format=api
{ "id": 12557, "url": "http://patches.dpdk.org/api/patches/12557/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1462562780-47991-24-git-send-email-stephen.hurd@broadcom.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1462562780-47991-24-git-send-email-stephen.hurd@broadcom.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1462562780-47991-24-git-send-email-stephen.hurd@broadcom.com", "date": "2016-05-06T19:26:04", "name": "[dpdk-dev,24/40] bnxt: add HWRM ring alloc/free functions", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "df5c31ad6d2b069d9fc4292135e71cbf466bd5d4", "submitter": { "id": 438, "url": "http://patches.dpdk.org/api/people/438/?format=api", "name": "Stephen Hurd", "email": "stephen.hurd@broadcom.com" }, "delegate": { "id": 10, "url": "http://patches.dpdk.org/api/users/10/?format=api", "username": "bruce", "first_name": "Bruce", "last_name": "Richardson", "email": "bruce.richardson@intel.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1462562780-47991-24-git-send-email-stephen.hurd@broadcom.com/mbox/", "series": [], "comments": "http://patches.dpdk.org/api/patches/12557/comments/", "check": "pending", "checks": "http://patches.dpdk.org/api/patches/12557/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [IPv6:::1])\n\tby dpdk.org (Postfix) with ESMTP id 704995A5C;\n\tFri, 6 May 2016 21:27:01 +0200 (CEST)", "from mail-gw3-out.broadcom.com (mail-gw3-out.broadcom.com\n\t[216.31.210.64]) by dpdk.org (Postfix) with ESMTP id 29A51559C\n\tfor <dev@dpdk.org>; Fri, 6 May 2016 21:26:52 +0200 (CEST)", "from mail-irv-18.broadcom.com ([10.15.198.37])\n\tby mail-gw3-out.broadcom.com with ESMTP; 06 May 2016 12:41:09 -0700", "from mail-irva-12.broadcom.com (mail-irva-12.broadcom.com\n\t[10.11.16.101])\n\tby mail-irv-18.broadcom.com (Postfix) with ESMTP id D051382025\n\tfor <dev@dpdk.org>; Fri, 6 May 2016 12:26:51 -0700 (PDT)", "from DPDK-C1.broadcom.com (dhcp-10-13-115-104.irv.broadcom.com\n\t[10.13.115.104])\n\tby mail-irva-12.broadcom.com (Postfix) with ESMTP id 1DDFF127625\n\tfor <dev@dpdk.org>; Fri, 6 May 2016 12:26:51 -0700 (PDT)" ], "X-IronPort-AV": "E=Sophos;i=\"5.24,587,1455004800\"; d=\"scan'208\";a=\"94345998\"", "From": "Stephen Hurd <stephen.hurd@broadcom.com>", "To": "dev@dpdk.org", "Date": "Fri, 6 May 2016 12:26:04 -0700", "Message-Id": "<1462562780-47991-24-git-send-email-stephen.hurd@broadcom.com>", "X-Mailer": "git-send-email 1.9.1", "In-Reply-To": "<1462562780-47991-1-git-send-email-stephen.hurd@broadcom.com>", "References": "<20160421100005.GA976@bricha3-MOBL3>\n\t<1462562780-47991-1-git-send-email-stephen.hurd@broadcom.com>", "Subject": "[dpdk-dev] [PATCH 24/40] bnxt: add HWRM ring alloc/free functions", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "patches and discussions about DPDK <dev.dpdk.org>", "List-Unsubscribe": "<http://dpdk.org/ml/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://dpdk.org/ml/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<http://dpdk.org/ml/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Add HWRM calls to allocate and free TX/RX/CMPL rings along with\nthe associated structs and definitions.\n\nSigned-off-by: Stephen Hurd <stephen.hurd@broadcom.com>\nReviewed-by: Ajit Kumar Khaparde <ajit.khaparde@broadcom.com>\n---\n drivers/net/bnxt/bnxt_hwrm.c | 108 ++++++++++++\n drivers/net/bnxt/bnxt_hwrm.h | 7 +\n drivers/net/bnxt/hsi_struct_def_dpdk.h | 305 +++++++++++++++++++++++++++++++++\n 3 files changed, 420 insertions(+)", "diff": "diff --git a/drivers/net/bnxt/bnxt_hwrm.c b/drivers/net/bnxt/bnxt_hwrm.c\nindex 2993aef..6a92089 100644\n--- a/drivers/net/bnxt/bnxt_hwrm.c\n+++ b/drivers/net/bnxt/bnxt_hwrm.c\n@@ -504,6 +504,114 @@ int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)\n \treturn rc;\n }\n \n+int bnxt_hwrm_ring_alloc(struct bnxt *bp,\n+\t\t\t struct bnxt_ring_struct *ring,\n+\t\t\t uint32_t ring_type, uint32_t map_index,\n+\t\t\t uint32_t stats_ctx_id)\n+{\n+\tint rc = 0;\n+\tstruct hwrm_ring_alloc_input req = {.req_type = 0 };\n+\tstruct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr;\n+\n+\tHWRM_PREP(req, RING_ALLOC, -1, resp);\n+\n+\treq.enables = rte_cpu_to_le_32(0);\n+\n+\treq.page_tbl_addr = rte_cpu_to_le_64(ring->bd_dma);\n+\treq.fbo = rte_cpu_to_le_32(0);\n+\t/* Association of ring index with doorbell index */\n+\treq.logical_id = rte_cpu_to_le_16(map_index);\n+\n+\tswitch (ring_type) {\n+\tcase HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:\n+\t\treq.queue_id = bp->cos_queue[0].id;\n+\tcase HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:\n+\t\treq.ring_type = ring_type;\n+\t\treq.cmpl_ring_id =\n+\t\t rte_cpu_to_le_16(bp->grp_info[map_index].cp_fw_ring_id);\n+\t\treq.length = rte_cpu_to_le_32(ring->ring_size);\n+\t\treq.stat_ctx_id = rte_cpu_to_le_16(stats_ctx_id);\n+\t\treq.enables = rte_cpu_to_le_32(rte_le_to_cpu_32(req.enables) |\n+\t\t\tHWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID);\n+\t\tbreak;\n+\tcase HWRM_RING_ALLOC_INPUT_RING_TYPE_CMPL:\n+\t\treq.ring_type = ring_type;\n+\t\treq.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_POLL;\n+\t\treq.length = rte_cpu_to_le_32(ring->ring_size);\n+\t\tbreak;\n+\tdefault:\n+\t\tRTE_LOG(ERR, PMD, \"hwrm alloc invalid ring type %d\\n\",\n+\t\t\tring_type);\n+\t\treturn -1;\n+\t}\n+\n+\trc = bnxt_hwrm_send_message(bp, &req, sizeof(req));\n+\n+\tif (rc || resp->error_code) {\n+\t\tif (rc == 0 && resp->error_code)\n+\t\t\trc = rte_le_to_cpu_16(resp->error_code);\n+\t\tswitch (ring_type) {\n+\t\tcase HWRM_RING_FREE_INPUT_RING_TYPE_CMPL:\n+\t\t\tRTE_LOG(ERR, PMD,\n+\t\t\t\t\"hwrm_ring_alloc cp failed. rc:%d\\n\", rc);\n+\t\t\treturn rc;\n+\t\tcase HWRM_RING_FREE_INPUT_RING_TYPE_RX:\n+\t\t\tRTE_LOG(ERR, PMD,\n+\t\t\t\t\"hwrm_ring_alloc rx failed. rc:%d\\n\", rc);\n+\t\t\treturn rc;\n+\t\tcase HWRM_RING_FREE_INPUT_RING_TYPE_TX:\n+\t\t\tRTE_LOG(ERR, PMD,\n+\t\t\t\t\"hwrm_ring_alloc tx failed. rc:%d\\n\", rc);\n+\t\t\treturn rc;\n+\t\tdefault:\n+\t\t\tRTE_LOG(ERR, PMD, \"Invalid ring. rc:%d\\n\", rc);\n+\t\t\treturn rc;\n+\t\t}\n+\t}\n+\n+\tring->fw_ring_id = rte_le_to_cpu_16(resp->ring_id);\n+\treturn rc;\n+}\n+\n+int bnxt_hwrm_ring_free(struct bnxt *bp,\n+\t\t\tstruct bnxt_ring_struct *ring, uint32_t ring_type)\n+{\n+\tint rc;\n+\tstruct hwrm_ring_free_input req = {.req_type = 0 };\n+\tstruct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;\n+\n+\tHWRM_PREP(req, RING_FREE, -1, resp);\n+\n+\treq.ring_type = ring_type;\n+\treq.ring_id = rte_cpu_to_le_16(ring->fw_ring_id);\n+\n+\trc = bnxt_hwrm_send_message(bp, &req, sizeof(req));\n+\n+\tif (rc || resp->error_code) {\n+\t\tif (rc == 0 && resp->error_code)\n+\t\t\trc = rte_le_to_cpu_16(resp->error_code);\n+\n+\t\tswitch (ring_type) {\n+\t\tcase HWRM_RING_FREE_INPUT_RING_TYPE_CMPL:\n+\t\t\tRTE_LOG(ERR, PMD, \"hwrm_ring_free cp failed. rc:%d\\n\",\n+\t\t\t\trc);\n+\t\t\treturn rc;\n+\t\tcase HWRM_RING_FREE_INPUT_RING_TYPE_RX:\n+\t\t\tRTE_LOG(ERR, PMD, \"hwrm_ring_free rx failed. rc:%d\\n\",\n+\t\t\t\trc);\n+\t\t\treturn rc;\n+\t\tcase HWRM_RING_FREE_INPUT_RING_TYPE_TX:\n+\t\t\tRTE_LOG(ERR, PMD, \"hwrm_ring_free tx failed. rc:%d\\n\",\n+\t\t\t\trc);\n+\t\t\treturn rc;\n+\t\tdefault:\n+\t\t\tRTE_LOG(ERR, PMD, \"Invalid ring, rc:%d\\n\", rc);\n+\t\t\treturn rc;\n+\t\t}\n+\t}\n+\treturn 0;\n+}\n+\n int bnxt_hwrm_stat_clear(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)\n {\n \tint rc = 0;\ndiff --git a/drivers/net/bnxt/bnxt_hwrm.h b/drivers/net/bnxt/bnxt_hwrm.h\nindex b4cc3b6..40accbc 100644\n--- a/drivers/net/bnxt/bnxt_hwrm.h\n+++ b/drivers/net/bnxt/bnxt_hwrm.h\n@@ -58,6 +58,13 @@ int bnxt_hwrm_func_driver_unregister(struct bnxt *bp, uint32_t flags);\n \n int bnxt_hwrm_queue_qportcfg(struct bnxt *bp);\n \n+int bnxt_hwrm_ring_alloc(struct bnxt *bp,\n+\t\t\t struct bnxt_ring_struct *ring,\n+\t\t\t uint32_t ring_type, uint32_t map_index,\n+\t\t\t uint32_t stats_ctx_id);\n+int bnxt_hwrm_ring_free(struct bnxt *bp,\n+\t\t\tstruct bnxt_ring_struct *ring, uint32_t ring_type);\n+\n int bnxt_hwrm_stat_clear(struct bnxt *bp, struct bnxt_cp_ring_info *cpr);\n int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp,\n \t\t\t struct bnxt_cp_ring_info *cpr, unsigned idx);\ndiff --git a/drivers/net/bnxt/hsi_struct_def_dpdk.h b/drivers/net/bnxt/hsi_struct_def_dpdk.h\nindex de3eb0e..16ac528 100644\n--- a/drivers/net/bnxt/hsi_struct_def_dpdk.h\n+++ b/drivers/net/bnxt/hsi_struct_def_dpdk.h\n@@ -93,6 +93,8 @@ typedef struct ctx_hw_stats64 {\n #define HWRM_VNIC_FREE\t\t\t(UINT32_C(0x41))\n #define HWRM_VNIC_CFG\t\t\t(UINT32_C(0x42))\n #define HWRM_VNIC_RSS_CFG\t\t(UINT32_C(0x46))\n+#define HWRM_RING_ALLOC\t\t\t(UINT32_C(0x50))\n+#define HWRM_RING_FREE\t\t\t(UINT32_C(0x51))\n #define HWRM_VNIC_RSS_COS_LB_CTX_ALLOC\t(UINT32_C(0x70))\n #define HWRM_VNIC_RSS_COS_LB_CTX_FREE\t(UINT32_C(0x71))\n #define HWRM_CFA_L2_FILTER_ALLOC\t(UINT32_C(0x90))\n@@ -3233,6 +3235,309 @@ struct hwrm_queue_qportcfg_input {\n \tuint16_t unused_0;\n } __attribute__((packed));\n \n+/* hwrm_ring_alloc */\n+/*\n+ * Description: This command allocates and does basic preparation for a ring.\n+ */\n+\n+/* Input (80 bytes) */\n+struct hwrm_ring_alloc_input {\n+\t/*\n+\t * This value indicates what type of request this is. The format for the\n+\t * rest of the command is determined by this field.\n+\t */\n+\tuint16_t req_type;\n+\n+\t/*\n+\t * This value indicates the what completion ring the request will be\n+\t * optionally completed on. If the value is -1, then no CR completion\n+\t * will be generated. Any other value must be a valid CR ring_id value\n+\t * for this function.\n+\t */\n+\tuint16_t cmpl_ring;\n+\n+\t/* This value indicates the command sequence number. */\n+\tuint16_t seq_id;\n+\n+\t/*\n+\t * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids\n+\t * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM\n+\t */\n+\tuint16_t target_id;\n+\n+\t/*\n+\t * This is the host address where the response will be written when the\n+\t * request is complete. This area must be 16B aligned and must be\n+\t * cleared to zero before the request is made.\n+\t */\n+\tuint64_t resp_addr;\n+\n+\t/* This bit must be '1' for the Reserved1 field to be configured. */\n+\t#define HWRM_RING_ALLOC_INPUT_ENABLES_RESERVED1\t\tUINT32_C(0x1)\n+\t/* This bit must be '1' for the Reserved2 field to be configured. */\n+\t#define HWRM_RING_ALLOC_INPUT_ENABLES_RESERVED2\t\tUINT32_C(0x2)\n+\t/* This bit must be '1' for the Reserved3 field to be configured. */\n+\t#define HWRM_RING_ALLOC_INPUT_ENABLES_RESERVED3\t\tUINT32_C(0x4)\n+\t/*\n+\t * This bit must be '1' for the stat_ctx_id_valid field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID\tUINT32_C(0x8)\n+\t/* This bit must be '1' for the Reserved4 field to be configured. */\n+\t#define HWRM_RING_ALLOC_INPUT_ENABLES_RESERVED4\t\tUINT32_C(0x10)\n+\t/* This bit must be '1' for the max_bw_valid field to be configured. */\n+\t#define HWRM_RING_ALLOC_INPUT_ENABLES_MAX_BW_VALID\tUINT32_C(0x20)\n+\tuint32_t enables;\n+\n+\t/* Ring Type. */\n+\t\t/* Completion Ring (CR) */\n+\t#define HWRM_RING_ALLOC_INPUT_RING_TYPE_CMPL\t(UINT32_C(0x0) << 0)\n+\t\t/* TX Ring (TR) */\n+\t#define HWRM_RING_ALLOC_INPUT_RING_TYPE_TX\t(UINT32_C(0x1) << 0)\n+\t\t/* RX Ring (RR) */\n+\t#define HWRM_RING_ALLOC_INPUT_RING_TYPE_RX\t(UINT32_C(0x2) << 0)\n+\tuint8_t ring_type;\n+\n+\tuint8_t unused_0;\n+\tuint16_t unused_1;\n+\n+\t/* This value is a pointer to the page table for the Ring. */\n+\tuint64_t page_tbl_addr;\n+\n+\t/* First Byte Offset of the first entry in the first page. */\n+\tuint32_t fbo;\n+\n+\t/*\n+\t * Actual page size in 2^page_size. The supported range is increments in\n+\t * powers of 2 from 16 bytes to 1GB. - 4 = 16 B Page size is 16 B. - 12\n+\t * = 4 KB Page size is 4 KB. - 13 = 8 KB Page size is 8 KB. - 16 = 64 KB\n+\t * Page size is 64 KB. - 22 = 2 MB Page size is 2 MB. - 23 = 4 MB Page\n+\t * size is 4 MB. - 31 = 1 GB Page size is 1 GB.\n+\t */\n+\tuint8_t page_size;\n+\n+\t/*\n+\t * This value indicates the depth of page table. For this version of the\n+\t * specification, value other than 0 or 1 shall be considered as an\n+\t * invalid value. When the page_tbl_depth = 0, then it is treated as a\n+\t * special case with the following. 1. FBO and page size fields are not\n+\t * valid. 2. page_tbl_addr is the physical address of the first element\n+\t * of the ring.\n+\t */\n+\tuint8_t page_tbl_depth;\n+\n+\tuint8_t unused_2;\n+\tuint8_t unused_3;\n+\n+\t/*\n+\t * Number of 16B units in the ring. Minimum size for a ring is 16 16B\n+\t * entries.\n+\t */\n+\tuint32_t length;\n+\n+\t/*\n+\t * Logical ring number for the ring to be allocated. This value\n+\t * determines the position in the doorbell area where the update to the\n+\t * ring will be made. For completion rings, this value is also the MSI-X\n+\t * vector number for the function the completion ring is associated\n+\t * with.\n+\t */\n+\tuint16_t logical_id;\n+\n+\t/*\n+\t * This field is used only when ring_type is a TX ring. This value\n+\t * indicates what completion ring the TX ring is associated with.\n+\t */\n+\tuint16_t cmpl_ring_id;\n+\n+\t/*\n+\t * This field is used only when ring_type is a TX ring. This value\n+\t * indicates what CoS queue the TX ring is associated with.\n+\t */\n+\tuint16_t queue_id;\n+\n+\tuint8_t unused_4;\n+\tuint8_t unused_5;\n+\n+\t/* This field is reserved for the future use. It shall be set to 0. */\n+\tuint32_t reserved1;\n+\t/* This field is reserved for the future use. It shall be set to 0. */\n+\tuint16_t reserved2;\n+\n+\tuint8_t unused_6;\n+\tuint8_t unused_7;\n+\t/* This field is reserved for the future use. It shall be set to 0. */\n+\tuint32_t reserved3;\n+\n+\t/*\n+\t * This field is used only when ring_type is a TX ring. This input\n+\t * indicates what statistics context this ring should be associated\n+\t * with.\n+\t */\n+\tuint32_t stat_ctx_id;\n+\n+\t/* This field is reserved for the future use. It shall be set to 0. */\n+\tuint32_t reserved4;\n+\n+\t/*\n+\t * This field is used only when ring_type is a TX ring. Maximum BW\n+\t * allocated to this TX ring in Mbps. The HWRM will translate this value\n+\t * into byte counter and time interval used for this ring inside the\n+\t * device.\n+\t */\n+\tuint32_t max_bw;\n+\n+\t/*\n+\t * This field is used only when ring_type is a Completion ring. This\n+\t * value indicates what interrupt mode should be used on this completion\n+\t * ring. Note: In the legacy interrupt mode, no more than 16 completion\n+\t * rings are allowed.\n+\t */\n+\t\t/* Legacy INTA */\n+\t#define HWRM_RING_ALLOC_INPUT_INT_MODE_LEGACY\t(UINT32_C(0x0) << 0)\n+\t\t/* Reserved */\n+\t#define HWRM_RING_ALLOC_INPUT_INT_MODE_RSVD\t(UINT32_C(0x1) << 0)\n+\t\t/* MSI-X */\n+\t#define HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX\t(UINT32_C(0x2) << 0)\n+\t\t/* No Interrupt - Polled mode */\n+\t#define HWRM_RING_ALLOC_INPUT_INT_MODE_POLL\t(UINT32_C(0x3) << 0)\n+\tuint8_t int_mode;\n+\n+\tuint8_t unused_8[3];\n+} __attribute__((packed));\n+\n+/* Output (16 bytes) */\n+\n+struct hwrm_ring_alloc_output {\n+\t/*\n+\t * Pass/Fail or error type Note: receiver to verify the in parameters,\n+\t * and fail the call with an error when appropriate\n+\t */\n+\tuint16_t error_code;\n+\n+\t/* This field returns the type of original request. */\n+\tuint16_t req_type;\n+\n+\t/* This field provides original sequence number of the command. */\n+\tuint16_t seq_id;\n+\n+\t/*\n+\t * This field is the length of the response in bytes. The last byte of\n+\t * the response is a valid flag that will read as '1' when the command\n+\t * has been completely written to memory.\n+\t */\n+\tuint16_t resp_len;\n+\n+\t/* Physical number of ring allocated. */\n+\tuint16_t ring_id;\n+\n+\t/* Logical number of ring allocated. */\n+\tuint16_t logical_ring_id;\n+\n+\tuint8_t unused_0;\n+\tuint8_t unused_1;\n+\tuint8_t unused_2;\n+\n+\t/*\n+\t * This field is used in Output records to indicate that the output is\n+\t * completely written to RAM. This field should be read as '1' to\n+\t * indicate that the output has been completely written. When writing a\n+\t * command completion or response to an internal processor, the order of\n+\t * writes has to be such that this field is written last.\n+\t */\n+\tuint8_t valid;\n+} __attribute__((packed));\n+\n+/* hwrm_ring_free */\n+/*\n+ * Description: This command is used to free a ring and associated resources.\n+ */\n+/* Input (24 bytes) */\n+\n+struct hwrm_ring_free_input {\n+\t/*\n+\t * This value indicates what type of request this is. The format for the\n+\t * rest of the command is determined by this field.\n+\t */\n+\tuint16_t req_type;\n+\n+\t/*\n+\t * This value indicates the what completion ring the request will be\n+\t * optionally completed on. If the value is -1, then no CR completion\n+\t * will be generated. Any other value must be a valid CR ring_id value\n+\t * for this function.\n+\t */\n+\tuint16_t cmpl_ring;\n+\n+\t/* This value indicates the command sequence number. */\n+\tuint16_t seq_id;\n+\n+\t/*\n+\t * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids\n+\t * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM\n+\t */\n+\tuint16_t target_id;\n+\n+\t/*\n+\t * This is the host address where the response will be written when the\n+\t * request is complete. This area must be 16B aligned and must be\n+\t * cleared to zero before the request is made.\n+\t */\n+\tuint64_t resp_addr;\n+\n+\t/* Ring Type. */\n+\t\t/* Completion Ring (CR) */\n+\t#define HWRM_RING_FREE_INPUT_RING_TYPE_CMPL\t(UINT32_C(0x0) << 0)\n+\t\t/* TX Ring (TR) */\n+\t#define HWRM_RING_FREE_INPUT_RING_TYPE_TX\t(UINT32_C(0x1) << 0)\n+\t\t/* RX Ring (RR) */\n+\t#define HWRM_RING_FREE_INPUT_RING_TYPE_RX\t(UINT32_C(0x2) << 0)\n+\tuint8_t ring_type;\n+\n+\tuint8_t unused_0;\n+\n+\t/* Physical number of ring allocated. */\n+\tuint16_t ring_id;\n+\n+\tuint32_t unused_1;\n+} __attribute__((packed));\n+\n+/* Output (16 bytes) */\n+struct hwrm_ring_free_output {\n+\t/*\n+\t * Pass/Fail or error type Note: receiver to verify the in parameters,\n+\t * and fail the call with an error when appropriate\n+\t */\n+\tuint16_t error_code;\n+\n+\t/* This field returns the type of original request. */\n+\tuint16_t req_type;\n+\n+\t/* This field provides original sequence number of the command. */\n+\tuint16_t seq_id;\n+\n+\t/*\n+\t * This field is the length of the response in bytes. The last byte of\n+\t * the response is a valid flag that will read as '1' when the command\n+\t * has been completely written to memory.\n+\t */\n+\tuint16_t resp_len;\n+\n+\tuint32_t unused_0;\n+\tuint8_t unused_1;\n+\tuint8_t unused_2;\n+\tuint8_t unused_3;\n+\n+\t/*\n+\t * This field is used in Output records to indicate that the output is\n+\t * completely written to RAM. This field should be read as '1' to\n+\t * indicate that the output has been completely written. When writing a\n+\t * command completion or response to an internal processor, the order of\n+\t * writes has to be such that this field is written last.\n+\t */\n+\tuint8_t valid;\n+} __attribute__((packed));\n+\n /* hwrm_stat_ctx_alloc */\n /*\n * Description: This command allocates and does basic preparation for a stat\n", "prefixes": [ "dpdk-dev", "24/40" ] }