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GET /api/patches/124705/?format=api
{ "id": 124705, "url": "http://patches.dpdk.org/api/patches/124705/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20230302212057.1114863-16-mingxia.liu@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20230302212057.1114863-16-mingxia.liu@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20230302212057.1114863-16-mingxia.liu@intel.com", "date": "2023-03-02T21:20:51", "name": "[v9,15/21] net/cpfl: add AVX512 data path for single queue model", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "a06b52d0b592034248c915a1e2cbec951f2314de", "submitter": { "id": 2514, "url": "http://patches.dpdk.org/api/people/2514/?format=api", "name": "Liu, Mingxia", "email": "mingxia.liu@intel.com" }, "delegate": { "id": 319, "url": "http://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20230302212057.1114863-16-mingxia.liu@intel.com/mbox/", "series": [ { "id": 27228, "url": "http://patches.dpdk.org/api/series/27228/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=27228", "date": "2023-03-02T21:20:36", "name": "add support for cpfl PMD in DPDK", "version": 9, "mbox": "http://patches.dpdk.org/series/27228/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/124705/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/124705/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id EF22141DB5;\n\tThu, 2 Mar 2023 14:07:52 +0100 (CET)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 299EC42D64;\n\tThu, 2 Mar 2023 14:06:32 +0100 (CET)", "from mga02.intel.com (mga02.intel.com [134.134.136.20])\n by mails.dpdk.org (Postfix) with ESMTP id 2B5A342D39\n for <dev@dpdk.org>; Thu, 2 Mar 2023 14:06:30 +0100 (CET)", "from orsmga001.jf.intel.com ([10.7.209.18])\n by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 02 Mar 2023 05:06:29 -0800", "from dpdk-mingxial-ice.sh.intel.com ([10.67.110.191])\n by orsmga001.jf.intel.com with ESMTP; 02 Mar 2023 05:06:27 -0800" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1677762390; x=1709298390;\n h=from:to:cc:subject:date:message-id:in-reply-to:\n references:mime-version:content-transfer-encoding;\n bh=bqsmURuR+y0gukh84wBSRS/UQIUIQwfINefCc2LCmyc=;\n b=BDdiUAZIMWPaKW8w0mzE595FLhPIrV8lmpwybwVEwWCcGHcoxivpJtzR\n 5essiK5kz/OxevZj+jayobl70dLOeqtzOkFQCIsCs3VBYEvPNAS4VQaD6\n HaDFpb4s7jzSUI4mg/u+nn3iv999zYPn3l4DVQhwxrb19iWSk4GniVWyi\n 3iOYww3YSs20CakwPcatjgHKvFtYeJyn0oLxtAfzCRYqkSSc8p+k+Up3J\n HXo5kYKEQe9yn087xkGA4qpyzuaiGmTvgNoGsSua7rSKzYlb1Fi7yfSJe\n XUoxAdLUH1DZHgVwdsyNTeVedgnAs2mgVjMKRFPcSx5v0Mw+pc6bYH6Jy Q==;", "X-IronPort-AV": [ "E=McAfee;i=\"6500,9779,10636\"; a=\"322988278\"", "E=Sophos;i=\"5.98,227,1673942400\"; d=\"scan'208\";a=\"322988278\"", "E=McAfee;i=\"6500,9779,10636\"; a=\"707406436\"", "E=Sophos;i=\"5.98,227,1673942400\"; d=\"scan'208\";a=\"707406436\"" ], "X-ExtLoop1": "1", "From": "Mingxia Liu <mingxia.liu@intel.com>", "To": "dev@dpdk.org,\n\tbeilei.xing@intel.com,\n\tyuying.zhang@intel.com", "Cc": "Mingxia Liu <mingxia.liu@intel.com>,\n\tWenjun Wu <wenjun1.wu@intel.com>", "Subject": "[PATCH v9 15/21] net/cpfl: add AVX512 data path for single queue\n model", "Date": "Thu, 2 Mar 2023 21:20:51 +0000", "Message-Id": "<20230302212057.1114863-16-mingxia.liu@intel.com>", "X-Mailer": "git-send-email 2.34.1", "In-Reply-To": "<20230302212057.1114863-1-mingxia.liu@intel.com>", "References": "<20230302103527.931071-1-mingxia.liu@intel.com>\n <20230302212057.1114863-1-mingxia.liu@intel.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Add support of AVX512 vector data path for single queue model.\n\nSigned-off-by: Wenjun Wu <wenjun1.wu@intel.com>\nSigned-off-by: Mingxia Liu <mingxia.liu@intel.com>\n---\n doc/guides/nics/cpfl.rst | 24 +++++-\n drivers/net/cpfl/cpfl_ethdev.c | 3 +-\n drivers/net/cpfl/cpfl_rxtx.c | 93 ++++++++++++++++++++++\n drivers/net/cpfl/cpfl_rxtx_vec_common.h | 100 ++++++++++++++++++++++++\n drivers/net/cpfl/meson.build | 25 +++++-\n 5 files changed, 242 insertions(+), 3 deletions(-)\n create mode 100644 drivers/net/cpfl/cpfl_rxtx_vec_common.h", "diff": "diff --git a/doc/guides/nics/cpfl.rst b/doc/guides/nics/cpfl.rst\nindex 253fa3afae..e2d71f8a4c 100644\n--- a/doc/guides/nics/cpfl.rst\n+++ b/doc/guides/nics/cpfl.rst\n@@ -82,4 +82,26 @@ Runtime Config Options\n Driver compilation and testing\n ------------------------------\n \n-Refer to the document :doc:`build_and_test` for details.\n\\ No newline at end of file\n+Refer to the document :doc:`build_and_test` for details.\n+\n+Features\n+--------\n+\n+Vector PMD\n+~~~~~~~~~~\n+\n+Vector path for Rx and Tx path are selected automatically.\n+The paths are chosen based on 2 conditions:\n+\n+- ``CPU``\n+\n+ On the x86 platform, the driver checks if the CPU supports AVX512.\n+ If the CPU supports AVX512 and EAL argument ``--force-max-simd-bitwidth``\n+ is set to 512, AVX512 paths will be chosen.\n+\n+- ``Offload features``\n+\n+ The supported HW offload features are described in the document cpfl.ini,\n+ A value \"P\" means the offload feature is not supported by vector path.\n+ If any not supported features are used, cpfl vector PMD is disabled\n+ and the scalar paths are chosen.\ndiff --git a/drivers/net/cpfl/cpfl_ethdev.c b/drivers/net/cpfl/cpfl_ethdev.c\nindex 1167cdcef7..e64cadfd38 100644\n--- a/drivers/net/cpfl/cpfl_ethdev.c\n+++ b/drivers/net/cpfl/cpfl_ethdev.c\n@@ -108,7 +108,8 @@ cpfl_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)\n \t\tRTE_ETH_TX_OFFLOAD_TCP_CKSUM\t\t|\n \t\tRTE_ETH_TX_OFFLOAD_SCTP_CKSUM\t\t|\n \t\tRTE_ETH_TX_OFFLOAD_TCP_TSO\t\t|\n-\t\tRTE_ETH_TX_OFFLOAD_MULTI_SEGS;\n+\t\tRTE_ETH_TX_OFFLOAD_MULTI_SEGS\t\t|\n+\t\tRTE_ETH_TX_OFFLOAD_MBUF_FAST_FREE;\n \n \tdev_info->default_txconf = (struct rte_eth_txconf) {\n \t\t.tx_free_thresh = CPFL_DEFAULT_TX_FREE_THRESH,\ndiff --git a/drivers/net/cpfl/cpfl_rxtx.c b/drivers/net/cpfl/cpfl_rxtx.c\nindex 520f61e07e..a3832acd4f 100644\n--- a/drivers/net/cpfl/cpfl_rxtx.c\n+++ b/drivers/net/cpfl/cpfl_rxtx.c\n@@ -8,6 +8,7 @@\n \n #include \"cpfl_ethdev.h\"\n #include \"cpfl_rxtx.h\"\n+#include \"cpfl_rxtx_vec_common.h\"\n \n static uint64_t\n cpfl_rx_offload_convert(uint64_t offload)\n@@ -739,24 +740,96 @@ void\n cpfl_set_rx_function(struct rte_eth_dev *dev)\n {\n \tstruct idpf_vport *vport = dev->data->dev_private;\n+#ifdef RTE_ARCH_X86\n+\tstruct idpf_rx_queue *rxq;\n+\tint i;\n+\n+\tif (cpfl_rx_vec_dev_check_default(dev) == CPFL_VECTOR_PATH &&\n+\t rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) {\n+\t\tvport->rx_vec_allowed = true;\n+\n+\t\tif (rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_512)\n+#ifdef CC_AVX512_SUPPORT\n+\t\t\tif (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1 &&\n+\t\t\t rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512BW) == 1)\n+\t\t\t\tvport->rx_use_avx512 = true;\n+#else\n+\t\tPMD_DRV_LOG(NOTICE,\n+\t\t\t \"AVX512 is not supported in build env\");\n+#endif /* CC_AVX512_SUPPORT */\n+\t} else {\n+\t\tvport->rx_vec_allowed = false;\n+\t}\n+#endif /* RTE_ARCH_X86 */\n \n+#ifdef RTE_ARCH_X86\n \tif (vport->rxq_model == VIRTCHNL2_QUEUE_MODEL_SPLIT) {\n \t\tPMD_DRV_LOG(NOTICE,\n \t\t\t \"Using Split Scalar Rx (port %d).\",\n \t\t\t dev->data->port_id);\n \t\tdev->rx_pkt_burst = idpf_dp_splitq_recv_pkts;\n \t} else {\n+\t\tif (vport->rx_vec_allowed) {\n+\t\t\tfor (i = 0; i < dev->data->nb_rx_queues; i++) {\n+\t\t\t\trxq = dev->data->rx_queues[i];\n+\t\t\t\t(void)idpf_qc_singleq_rx_vec_setup(rxq);\n+\t\t\t}\n+#ifdef CC_AVX512_SUPPORT\n+\t\t\tif (vport->rx_use_avx512) {\n+\t\t\t\tPMD_DRV_LOG(NOTICE,\n+\t\t\t\t\t \"Using Single AVX512 Vector Rx (port %d).\",\n+\t\t\t\t\t dev->data->port_id);\n+\t\t\t\tdev->rx_pkt_burst = idpf_dp_singleq_recv_pkts_avx512;\n+\t\t\t\treturn;\n+\t\t\t}\n+#endif /* CC_AVX512_SUPPORT */\n+\t\t}\n \t\tPMD_DRV_LOG(NOTICE,\n \t\t\t \"Using Single Scalar Rx (port %d).\",\n \t\t\t dev->data->port_id);\n \t\tdev->rx_pkt_burst = idpf_dp_singleq_recv_pkts;\n \t}\n+#else\n+\tif (vport->rxq_model == VIRTCHNL2_QUEUE_MODEL_SPLIT) {\n+\t\tPMD_DRV_LOG(NOTICE,\n+\t\t\t \"Using Split Scalar Rx (port %d).\",\n+\t\t\t dev->data->port_id);\n+\t\tdev->rx_pkt_burst = idpf_dp_splitq_recv_pkts;\n+\t} else {\n+\t\tPMD_DRV_LOG(NOTICE,\n+\t\t\t \"Using Single Scalar Rx (port %d).\",\n+\t\t\t dev->data->port_id);\n+\t\tdev->rx_pkt_burst = idpf_dp_singleq_recv_pkts;\n+\t}\n+#endif /* RTE_ARCH_X86 */\n }\n \n void\n cpfl_set_tx_function(struct rte_eth_dev *dev)\n {\n \tstruct idpf_vport *vport = dev->data->dev_private;\n+#ifdef RTE_ARCH_X86\n+#ifdef CC_AVX512_SUPPORT\n+\tstruct idpf_tx_queue *txq;\n+\tint i;\n+#endif /* CC_AVX512_SUPPORT */\n+\n+\tif (cpfl_tx_vec_dev_check_default(dev) == CPFL_VECTOR_PATH &&\n+\t rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) {\n+\t\tvport->tx_vec_allowed = true;\n+\t\tif (rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_512)\n+#ifdef CC_AVX512_SUPPORT\n+\t\t\tif (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1 &&\n+\t\t\t rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512BW) == 1)\n+\t\t\t\tvport->tx_use_avx512 = true;\n+#else\n+\t\tPMD_DRV_LOG(NOTICE,\n+\t\t\t \"AVX512 is not supported in build env\");\n+#endif /* CC_AVX512_SUPPORT */\n+\t} else {\n+\t\tvport->tx_vec_allowed = false;\n+\t}\n+#endif /* RTE_ARCH_X86 */\n \n \tif (vport->txq_model == VIRTCHNL2_QUEUE_MODEL_SPLIT) {\n \t\tPMD_DRV_LOG(NOTICE,\n@@ -765,6 +838,26 @@ cpfl_set_tx_function(struct rte_eth_dev *dev)\n \t\tdev->tx_pkt_burst = idpf_dp_splitq_xmit_pkts;\n \t\tdev->tx_pkt_prepare = idpf_dp_prep_pkts;\n \t} else {\n+#ifdef RTE_ARCH_X86\n+\t\tif (vport->tx_vec_allowed) {\n+#ifdef CC_AVX512_SUPPORT\n+\t\t\tif (vport->tx_use_avx512) {\n+\t\t\t\tfor (i = 0; i < dev->data->nb_tx_queues; i++) {\n+\t\t\t\t\ttxq = dev->data->tx_queues[i];\n+\t\t\t\t\tif (txq == NULL)\n+\t\t\t\t\t\tcontinue;\n+\t\t\t\t\tidpf_qc_tx_vec_avx512_setup(txq);\n+\t\t\t\t}\n+\t\t\t\tPMD_DRV_LOG(NOTICE,\n+\t\t\t\t\t \"Using Single AVX512 Vector Tx (port %d).\",\n+\t\t\t\t\t dev->data->port_id);\n+\t\t\t\tdev->tx_pkt_burst = idpf_dp_singleq_xmit_pkts_avx512;\n+\t\t\t\tdev->tx_pkt_prepare = idpf_dp_prep_pkts;\n+\t\t\t\treturn;\n+\t\t\t}\n+#endif /* CC_AVX512_SUPPORT */\n+\t\t}\n+#endif /* RTE_ARCH_X86 */\n \t\tPMD_DRV_LOG(NOTICE,\n \t\t\t \"Using Single Scalar Tx (port %d).\",\n \t\t\t dev->data->port_id);\ndiff --git a/drivers/net/cpfl/cpfl_rxtx_vec_common.h b/drivers/net/cpfl/cpfl_rxtx_vec_common.h\nnew file mode 100644\nindex 0000000000..2d4c6a0ef3\n--- /dev/null\n+++ b/drivers/net/cpfl/cpfl_rxtx_vec_common.h\n@@ -0,0 +1,100 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2023 Intel Corporation\n+ */\n+\n+#ifndef _CPFL_RXTX_VEC_COMMON_H_\n+#define _CPFL_RXTX_VEC_COMMON_H_\n+#include <stdint.h>\n+#include <ethdev_driver.h>\n+#include <rte_malloc.h>\n+\n+#include \"cpfl_ethdev.h\"\n+#include \"cpfl_rxtx.h\"\n+\n+#ifndef __INTEL_COMPILER\n+#pragma GCC diagnostic ignored \"-Wcast-qual\"\n+#endif\n+\n+#define CPFL_SCALAR_PATH\t\t0\n+#define CPFL_VECTOR_PATH\t\t1\n+#define CPFL_RX_NO_VECTOR_FLAGS (\t\t\\\n+\t\tRTE_ETH_RX_OFFLOAD_IPV4_CKSUM |\t\\\n+\t\tRTE_ETH_RX_OFFLOAD_UDP_CKSUM |\t\\\n+\t\tRTE_ETH_RX_OFFLOAD_TCP_CKSUM |\t\\\n+\t\tRTE_ETH_RX_OFFLOAD_OUTER_IPV4_CKSUM |\t\\\n+\t\tRTE_ETH_RX_OFFLOAD_TIMESTAMP)\n+#define CPFL_TX_NO_VECTOR_FLAGS (\t\t\\\n+\t\tRTE_ETH_TX_OFFLOAD_TCP_TSO |\t\\\n+\t\tRTE_ETH_TX_OFFLOAD_MULTI_SEGS)\n+\n+static inline int\n+cpfl_rx_vec_queue_default(struct idpf_rx_queue *rxq)\n+{\n+\tif (rxq == NULL)\n+\t\treturn CPFL_SCALAR_PATH;\n+\n+\tif (rte_is_power_of_2(rxq->nb_rx_desc) == 0)\n+\t\treturn CPFL_SCALAR_PATH;\n+\n+\tif (rxq->rx_free_thresh < IDPF_VPMD_RX_MAX_BURST)\n+\t\treturn CPFL_SCALAR_PATH;\n+\n+\tif ((rxq->nb_rx_desc % rxq->rx_free_thresh) != 0)\n+\t\treturn CPFL_SCALAR_PATH;\n+\n+\tif ((rxq->offloads & CPFL_RX_NO_VECTOR_FLAGS) != 0)\n+\t\treturn CPFL_SCALAR_PATH;\n+\n+\treturn CPFL_VECTOR_PATH;\n+}\n+\n+static inline int\n+cpfl_tx_vec_queue_default(struct idpf_tx_queue *txq)\n+{\n+\tif (txq == NULL)\n+\t\treturn CPFL_SCALAR_PATH;\n+\n+\tif (txq->rs_thresh < IDPF_VPMD_TX_MAX_BURST ||\n+\t (txq->rs_thresh & 3) != 0)\n+\t\treturn CPFL_SCALAR_PATH;\n+\n+\tif ((txq->offloads & CPFL_TX_NO_VECTOR_FLAGS) != 0)\n+\t\treturn CPFL_SCALAR_PATH;\n+\n+\treturn CPFL_VECTOR_PATH;\n+}\n+\n+static inline int\n+cpfl_rx_vec_dev_check_default(struct rte_eth_dev *dev)\n+{\n+\tstruct idpf_rx_queue *rxq;\n+\tint i, ret = 0;\n+\n+\tfor (i = 0; i < dev->data->nb_rx_queues; i++) {\n+\t\trxq = dev->data->rx_queues[i];\n+\t\tret = (cpfl_rx_vec_queue_default(rxq));\n+\t\tif (ret == CPFL_SCALAR_PATH)\n+\t\t\treturn CPFL_SCALAR_PATH;\n+\t}\n+\n+\treturn CPFL_VECTOR_PATH;\n+}\n+\n+static inline int\n+cpfl_tx_vec_dev_check_default(struct rte_eth_dev *dev)\n+{\n+\tint i;\n+\tstruct idpf_tx_queue *txq;\n+\tint ret = 0;\n+\n+\tfor (i = 0; i < dev->data->nb_tx_queues; i++) {\n+\t\ttxq = dev->data->tx_queues[i];\n+\t\tret = cpfl_tx_vec_queue_default(txq);\n+\t\tif (ret == CPFL_SCALAR_PATH)\n+\t\t\treturn CPFL_SCALAR_PATH;\n+\t}\n+\n+\treturn CPFL_VECTOR_PATH;\n+}\n+\n+#endif /*_CPFL_RXTX_VEC_COMMON_H_*/\ndiff --git a/drivers/net/cpfl/meson.build b/drivers/net/cpfl/meson.build\nindex 1894423689..fbe6500826 100644\n--- a/drivers/net/cpfl/meson.build\n+++ b/drivers/net/cpfl/meson.build\n@@ -7,9 +7,32 @@ if is_windows\n subdir_done()\n endif\n \n+if dpdk_conf.get('RTE_IOVA_AS_PA') == 0\n+ build = false\n+ reason = 'driver does not support disabling IOVA as PA mode'\n+ subdir_done()\n+endif\n+\n deps += ['common_idpf']\n \n sources = files(\n 'cpfl_ethdev.c',\n 'cpfl_rxtx.c',\n-)\n\\ No newline at end of file\n+)\n+\n+if arch_subdir == 'x86'\n+ cpfl_avx512_cpu_support = (\n+ cc.get_define('__AVX512F__', args: machine_args) != '' and\n+ cc.get_define('__AVX512BW__', args: machine_args) != ''\n+ )\n+\n+ cpfl_avx512_cc_support = (\n+ not machine_args.contains('-mno-avx512f') and\n+ cc.has_argument('-mavx512f') and\n+ cc.has_argument('-mavx512bw')\n+ )\n+\n+ if cpfl_avx512_cpu_support == true or cpfl_avx512_cc_support == true\n+ cflags += ['-DCC_AVX512_SUPPORT']\n+ endif\n+endif\n", "prefixes": [ "v9", "15/21" ] }