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GET /api/patches/124486/?format=api
{ "id": 124486, "url": "http://patches.dpdk.org/api/patches/124486/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20230224054813.2855914-10-ktejasree@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20230224054813.2855914-10-ktejasree@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20230224054813.2855914-10-ktejasree@marvell.com", "date": "2023-02-24T05:48:11", "name": "[09/11] crypto/cnxk: support cn10k IPsec SG mode", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "3209c28d721d3492d10757fd797360b60442e98d", "submitter": { "id": 1789, "url": "http://patches.dpdk.org/api/people/1789/?format=api", "name": "Tejasree Kondoj", "email": "ktejasree@marvell.com" }, "delegate": { "id": 1, "url": "http://patches.dpdk.org/api/users/1/?format=api", "username": "tmonjalo", "first_name": "Thomas", "last_name": "Monjalon", "email": "thomas@monjalon.net" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20230224054813.2855914-10-ktejasree@marvell.com/mbox/", "series": [ { "id": 27165, "url": "http://patches.dpdk.org/api/series/27165/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=27165", "date": "2023-02-24T05:48:02", "name": "fixes and improvements to cnxk crypto PMD", "version": 1, "mbox": "http://patches.dpdk.org/series/27165/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/124486/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/124486/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 3AC8241D5B;\n\tFri, 24 Feb 2023 06:49:16 +0100 (CET)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 28A5B42D13;\n\tFri, 24 Feb 2023 06:48:39 +0100 (CET)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n [67.231.156.173])\n by mails.dpdk.org (Postfix) with ESMTP id 61A3A42C24\n for <dev@dpdk.org>; Fri, 24 Feb 2023 06:48:37 +0100 (CET)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n by mx0b-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id\n 31O3N3Ds009275 for <dev@dpdk.org>; Thu, 23 Feb 2023 21:48:36 -0800", "from dc5-exch01.marvell.com ([199.233.59.181])\n by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3nxfkwa3ce-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Thu, 23 Feb 2023 21:48:36 -0800", "from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.42;\n Thu, 23 Feb 2023 21:48:34 -0800", "from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.42 via Frontend\n Transport; Thu, 23 Feb 2023 21:48:34 -0800", "from hyd1554.marvell.com (unknown [10.29.57.11])\n by maili.marvell.com (Postfix) with ESMTP id E754D3F7080;\n Thu, 23 Feb 2023 21:48:32 -0800 (PST)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-transfer-encoding : content-type; s=pfpt0220;\n bh=DhdxFVKSKsuhGNQ8Hxlq4cH0iW4rzFduNAfwth3yLTs=;\n b=O6Ikht9oVd04UbHIpY5cLnfPKibRYu8FKBumMb6h9v4ZbnYDNfQxeESgV1NHcdDx8Pni\n yYKxaiuVJm5MkYA5i8BzG/4ea1XUPLVALqMwzjs5YMYnFC/gz8gYBj2YW+9ceplxr10L\n aid9rd9WM2/gALGWBGGORSeOQR9++LGcmQ+Mt2jSkAH425Puk6xDTt5ozzo8XuRr7z/B\n 0UkS5ncqyBLzifFFl3RdgfIQKdWHIk7T0P++FJZ0swJ2mH2uDhjWq+EshQcEbOK9GQbW\n klyrT7tMGoAq4zd5hMnoUYfZFigv+4a0Mnyi5OsAsm8dKOwHDZhogEA+rtJHmBy+vCza aw==", "From": "Tejasree Kondoj <ktejasree@marvell.com>", "To": "Akhil Goyal <gakhil@marvell.com>", "CC": "Anoob Joseph <anoobj@marvell.com>, Gowrishankar Muthukrishnan\n <gmuthukrishn@marvell.com>, <dev@dpdk.org>", "Subject": "[PATCH 09/11] crypto/cnxk: support cn10k IPsec SG mode", "Date": "Fri, 24 Feb 2023 11:18:11 +0530", "Message-ID": "<20230224054813.2855914-10-ktejasree@marvell.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20230224054813.2855914-1-ktejasree@marvell.com>", "References": "<20230224054813.2855914-1-ktejasree@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-GUID": "Ns9NJckvE-q3i74dAmLJrpQJt2PY1DCi", "X-Proofpoint-ORIG-GUID": "Ns9NJckvE-q3i74dAmLJrpQJt2PY1DCi", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.219,Aquarius:18.0.930,Hydra:6.0.562,FMLib:17.11.170.22\n definitions=2023-02-24_02,2023-02-23_01,2023-02-09_01", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Adding support for scatter-gather mode in 103XX and\n106XX lookaside IPsec.\n\nSigned-off-by: Tejasree Kondoj <ktejasree@marvell.com>\n---\n drivers/crypto/cnxk/cn10k_cryptodev_ops.c | 21 +-\n drivers/crypto/cnxk/cn10k_ipsec_la_ops.h | 222 ++++++++++++++++++++--\n drivers/crypto/cnxk/cnxk_sg.h | 23 +++\n 3 files changed, 239 insertions(+), 27 deletions(-)", "diff": "diff --git a/drivers/crypto/cnxk/cn10k_cryptodev_ops.c b/drivers/crypto/cnxk/cn10k_cryptodev_ops.c\nindex 9f6fd4e411..e405a2ad9f 100644\n--- a/drivers/crypto/cnxk/cn10k_cryptodev_ops.c\n+++ b/drivers/crypto/cnxk/cn10k_cryptodev_ops.c\n@@ -77,8 +77,8 @@ cn10k_cpt_sym_temp_sess_create(struct cnxk_cpt_qp *qp, struct rte_crypto_op *op)\n }\n \n static __rte_always_inline int __rte_hot\n-cpt_sec_inst_fill(struct cnxk_cpt_qp *qp, struct rte_crypto_op *op,\n-\t\t struct cn10k_sec_session *sess, struct cpt_inst_s *inst)\n+cpt_sec_inst_fill(struct cnxk_cpt_qp *qp, struct rte_crypto_op *op, struct cn10k_sec_session *sess,\n+\t\t struct cpt_inst_s *inst, struct cpt_inflight_req *infl_req, const bool is_sg_ver2)\n {\n \tstruct rte_crypto_sym_op *sym_op = op->sym;\n \tint ret;\n@@ -88,15 +88,11 @@ cpt_sec_inst_fill(struct cnxk_cpt_qp *qp, struct rte_crypto_op *op,\n \t\treturn -ENOTSUP;\n \t}\n \n-\tif (unlikely(!rte_pktmbuf_is_contiguous(sym_op->m_src))) {\n-\t\tplt_dp_err(\"Scatter Gather mode is not supported\");\n-\t\treturn -ENOTSUP;\n-\t}\n-\n \tif (sess->is_outbound)\n-\t\tret = process_outb_sa(&qp->lf, op, sess, inst);\n+\t\tret = process_outb_sa(&qp->lf, op, sess, &qp->meta_info, infl_req, inst,\n+\t\t\t\t is_sg_ver2);\n \telse\n-\t\tret = process_inb_sa(op, sess, inst);\n+\t\tret = process_inb_sa(op, sess, inst, &qp->meta_info, infl_req, is_sg_ver2);\n \n \treturn ret;\n }\n@@ -129,7 +125,7 @@ cn10k_cpt_fill_inst(struct cnxk_cpt_qp *qp, struct rte_crypto_op *ops[], struct\n \tif (op->type == RTE_CRYPTO_OP_TYPE_SYMMETRIC) {\n \t\tif (op->sess_type == RTE_CRYPTO_OP_SECURITY_SESSION) {\n \t\t\tsec_sess = (struct cn10k_sec_session *)sym_op->session;\n-\t\t\tret = cpt_sec_inst_fill(qp, op, sec_sess, &inst[0]);\n+\t\t\tret = cpt_sec_inst_fill(qp, op, sec_sess, &inst[0], infl_req, is_sg_ver2);\n \t\t\tif (unlikely(ret))\n \t\t\t\treturn 0;\n \t\t\tw7 = sec_sess->inst.w7;\n@@ -827,7 +823,10 @@ cn10k_cpt_sec_post_process(struct rte_crypto_op *cop, struct cpt_cn10k_res_s *re\n \t\tcop->status = RTE_CRYPTO_OP_STATUS_ERROR;\n \t\treturn;\n \t}\n-\tmbuf->data_len = m_len;\n+\n+\tif (mbuf->next == NULL)\n+\t\tmbuf->data_len = m_len;\n+\n \tmbuf->pkt_len = m_len;\n }\n \ndiff --git a/drivers/crypto/cnxk/cn10k_ipsec_la_ops.h b/drivers/crypto/cnxk/cn10k_ipsec_la_ops.h\nindex f2761a55a5..8e208eb2ca 100644\n--- a/drivers/crypto/cnxk/cn10k_ipsec_la_ops.h\n+++ b/drivers/crypto/cnxk/cn10k_ipsec_la_ops.h\n@@ -8,9 +8,13 @@\n #include <rte_crypto_sym.h>\n #include <rte_security.h>\n \n+#include \"roc_ie.h\"\n+\n #include \"cn10k_cryptodev.h\"\n #include \"cn10k_ipsec.h\"\n #include \"cnxk_cryptodev.h\"\n+#include \"cnxk_cryptodev_ops.h\"\n+#include \"cnxk_sg.h\"\n \n static inline void\n ipsec_po_sa_iv_set(struct cn10k_sec_session *sess, struct rte_crypto_op *cop)\n@@ -44,18 +48,14 @@ ipsec_po_sa_aes_gcm_iv_set(struct cn10k_sec_session *sess, struct rte_crypto_op\n \n static __rte_always_inline int\n process_outb_sa(struct roc_cpt_lf *lf, struct rte_crypto_op *cop, struct cn10k_sec_session *sess,\n-\t\tstruct cpt_inst_s *inst)\n+\t\tstruct cpt_qp_meta_info *m_info, struct cpt_inflight_req *infl_req,\n+\t\tstruct cpt_inst_s *inst, const bool is_sg_ver2)\n {\n \tstruct rte_crypto_sym_op *sym_op = cop->sym;\n \tstruct rte_mbuf *m_src = sym_op->m_src;\n \tuint64_t inst_w4_u64 = sess->inst.w4;\n \tuint64_t dptr;\n \n-\tif (unlikely(rte_pktmbuf_tailroom(m_src) < sess->max_extended_len)) {\n-\t\tplt_dp_err(\"Not enough tail room\");\n-\t\treturn -ENOMEM;\n-\t}\n-\n \tRTE_SET_USED(lf);\n \n #ifdef LA_IPSEC_DEBUG\n@@ -79,27 +79,217 @@ process_outb_sa(struct roc_cpt_lf *lf, struct rte_crypto_op *cop, struct cn10k_s\n \tif (m_src->ol_flags & RTE_MBUF_F_TX_L4_MASK)\n \t\tinst_w4_u64 &= ~BIT_ULL(32);\n \n-\t/* Prepare CPT instruction */\n-\tinst->w4.u64 = inst_w4_u64 | rte_pktmbuf_pkt_len(m_src);\n-\tdptr = rte_pktmbuf_mtod(m_src, uint64_t);\n-\tinst->dptr = dptr;\n+\tif (likely(m_src->next == NULL)) {\n+\t\tif (unlikely(rte_pktmbuf_tailroom(m_src) < sess->max_extended_len)) {\n+\t\t\tplt_dp_err(\"Not enough tail room\");\n+\t\t\treturn -ENOMEM;\n+\t\t}\n+\n+\t\t/* Prepare CPT instruction */\n+\t\tinst->w4.u64 = inst_w4_u64 | rte_pktmbuf_pkt_len(m_src);\n+\t\tdptr = rte_pktmbuf_mtod(m_src, uint64_t);\n+\t\tinst->dptr = dptr;\n+\t} else if (is_sg_ver2 == false) {\n+\t\tstruct roc_sglist_comp *scatter_comp, *gather_comp;\n+\t\tuint32_t g_size_bytes, s_size_bytes;\n+\t\tstruct rte_mbuf *last_seg;\n+\t\tuint8_t *in_buffer;\n+\t\tuint32_t dlen;\n+\t\tvoid *m_data;\n+\t\tint i;\n+\n+\t\tlast_seg = rte_pktmbuf_lastseg(m_src);\n+\n+\t\tif (unlikely(rte_pktmbuf_tailroom(last_seg) < sess->max_extended_len)) {\n+\t\t\tplt_dp_err(\"Not enough tail room (required: %d, available: %d)\",\n+\t\t\t\t sess->max_extended_len, rte_pktmbuf_tailroom(last_seg));\n+\t\t\treturn -ENOMEM;\n+\t\t}\n+\n+\t\tm_data = alloc_op_meta(NULL, m_info->mlen, m_info->pool, infl_req);\n+\t\tif (unlikely(m_data == NULL)) {\n+\t\t\tplt_dp_err(\"Error allocating meta buffer for request\");\n+\t\t\treturn -ENOMEM;\n+\t\t}\n+\n+\t\tin_buffer = m_data;\n+\n+\t\t((uint16_t *)in_buffer)[0] = 0;\n+\t\t((uint16_t *)in_buffer)[1] = 0;\n+\n+\t\t/* Input Gather List */\n+\t\ti = 0;\n+\t\tgather_comp = (struct roc_sglist_comp *)((uint8_t *)m_data + 8);\n+\n+\t\ti = fill_ipsec_sg_comp_from_pkt(gather_comp, i, m_src);\n+\t\t((uint16_t *)in_buffer)[2] = rte_cpu_to_be_16(i);\n+\n+\t\tg_size_bytes = ((i + 3) / 4) * sizeof(struct roc_sglist_comp);\n+\n+\t\t/* Output Scatter List */\n+\t\tlast_seg->data_len += sess->max_extended_len;\n+\n+\t\ti = 0;\n+\t\tscatter_comp = (struct roc_sglist_comp *)((uint8_t *)gather_comp + g_size_bytes);\n+\n+\t\ti = fill_ipsec_sg_comp_from_pkt(scatter_comp, i, m_src);\n+\t\t((uint16_t *)in_buffer)[3] = rte_cpu_to_be_16(i);\n+\n+\t\ts_size_bytes = ((i + 3) / 4) * sizeof(struct roc_sglist_comp);\n+\n+\t\tdlen = g_size_bytes + s_size_bytes + ROC_SG_LIST_HDR_SIZE;\n+\n+\t\tinst->dptr = (uint64_t)in_buffer;\n+\n+\t\tinst->w4.u64 = sess->inst.w4 | dlen;\n+\t\tinst->w4.s.opcode_major |= (uint64_t)ROC_DMA_MODE_SG;\n+\t} else {\n+\t\tstruct roc_sg2list_comp *scatter_comp, *gather_comp;\n+\t\tunion cpt_inst_w5 cpt_inst_w5;\n+\t\tunion cpt_inst_w6 cpt_inst_w6;\n+\t\tstruct rte_mbuf *last_seg;\n+\t\tuint32_t g_size_bytes;\n+\t\tvoid *m_data;\n+\t\tint i;\n+\n+\t\tlast_seg = rte_pktmbuf_lastseg(m_src);\n+\n+\t\tif (unlikely(rte_pktmbuf_tailroom(last_seg) < sess->max_extended_len)) {\n+\t\t\tplt_dp_err(\"Not enough tail room (required: %d, available: %d)\",\n+\t\t\t\t sess->max_extended_len, rte_pktmbuf_tailroom(last_seg));\n+\t\t\treturn -ENOMEM;\n+\t\t}\n+\n+\t\tm_data = alloc_op_meta(NULL, m_info->mlen, m_info->pool, infl_req);\n+\t\tif (unlikely(m_data == NULL)) {\n+\t\t\tplt_dp_err(\"Error allocating meta buffer for request\");\n+\t\t\treturn -ENOMEM;\n+\t\t}\n+\n+\t\t/* Input Gather List */\n+\t\ti = 0;\n+\t\tgather_comp = (struct roc_sg2list_comp *)((uint8_t *)m_data);\n+\n+\t\ti = fill_ipsec_sg2_comp_from_pkt(gather_comp, i, m_src);\n+\n+\t\tcpt_inst_w5.s.gather_sz = ((i + 2) / 3);\n+\t\tg_size_bytes = ((i + 2) / 3) * sizeof(struct roc_sg2list_comp);\n+\n+\t\t/* Output Scatter List */\n+\t\tlast_seg->data_len += sess->max_extended_len;\n+\n+\t\ti = 0;\n+\t\tscatter_comp = (struct roc_sg2list_comp *)((uint8_t *)gather_comp + g_size_bytes);\n+\n+\t\ti = fill_ipsec_sg2_comp_from_pkt(scatter_comp, i, m_src);\n+\n+\t\tcpt_inst_w6.s.scatter_sz = ((i + 2) / 3);\n+\n+\t\tcpt_inst_w5.s.dptr = (uint64_t)gather_comp;\n+\t\tcpt_inst_w6.s.rptr = (uint64_t)scatter_comp;\n+\n+\t\tinst->w5.u64 = cpt_inst_w5.u64;\n+\t\tinst->w6.u64 = cpt_inst_w6.u64;\n+\t\tinst->w4.u64 = sess->inst.w4 | rte_pktmbuf_pkt_len(m_src);\n+\t\tinst->w4.s.opcode_major &= (~(ROC_IE_OT_INPLACE_BIT));\n+\t}\n \n \treturn 0;\n }\n \n static __rte_always_inline int\n-process_inb_sa(struct rte_crypto_op *cop, struct cn10k_sec_session *sess, struct cpt_inst_s *inst)\n+process_inb_sa(struct rte_crypto_op *cop, struct cn10k_sec_session *sess, struct cpt_inst_s *inst,\n+\t struct cpt_qp_meta_info *m_info, struct cpt_inflight_req *infl_req,\n+\t const bool is_sg_ver2)\n {\n \tstruct rte_crypto_sym_op *sym_op = cop->sym;\n \tstruct rte_mbuf *m_src = sym_op->m_src;\n \tuint64_t dptr;\n \n-\t/* Prepare CPT instruction */\n-\tinst->w4.u64 = sess->inst.w4 | rte_pktmbuf_pkt_len(m_src);\n-\tdptr = rte_pktmbuf_mtod(m_src, uint64_t);\n-\tinst->dptr = dptr;\n-\tm_src->ol_flags |= (uint64_t)sess->ip_csum;\n+\tif (likely(m_src->next == NULL)) {\n+\t\t/* Prepare CPT instruction */\n+\t\tinst->w4.u64 = sess->inst.w4 | rte_pktmbuf_pkt_len(m_src);\n+\t\tdptr = rte_pktmbuf_mtod(m_src, uint64_t);\n+\t\tinst->dptr = dptr;\n+\t\tm_src->ol_flags |= (uint64_t)sess->ip_csum;\n+\t} else if (is_sg_ver2 == false) {\n+\t\tstruct roc_sglist_comp *scatter_comp, *gather_comp;\n+\t\tuint32_t g_size_bytes, s_size_bytes;\n+\t\tuint8_t *in_buffer;\n+\t\tuint32_t dlen;\n+\t\tvoid *m_data;\n+\t\tint i;\n+\n+\t\tm_data = alloc_op_meta(NULL, m_info->mlen, m_info->pool, infl_req);\n+\t\tif (unlikely(m_data == NULL)) {\n+\t\t\tplt_dp_err(\"Error allocating meta buffer for request\");\n+\t\t\treturn -ENOMEM;\n+\t\t}\n+\n+\t\tin_buffer = m_data;\n+\n+\t\t((uint16_t *)in_buffer)[0] = 0;\n+\t\t((uint16_t *)in_buffer)[1] = 0;\n+\n+\t\t/* Input Gather List */\n+\t\ti = 0;\n+\t\tgather_comp = (struct roc_sglist_comp *)((uint8_t *)m_data + 8);\n+\t\ti = fill_ipsec_sg_comp_from_pkt(gather_comp, i, m_src);\n+\t\t((uint16_t *)in_buffer)[2] = rte_cpu_to_be_16(i);\n+\n+\t\tg_size_bytes = ((i + 3) / 4) * sizeof(struct roc_sglist_comp);\n \n+\t\t/* Output Scatter List */\n+\t\ti = 0;\n+\t\tscatter_comp = (struct roc_sglist_comp *)((uint8_t *)gather_comp + g_size_bytes);\n+\t\ti = fill_ipsec_sg_comp_from_pkt(scatter_comp, i, m_src);\n+\t\t((uint16_t *)in_buffer)[3] = rte_cpu_to_be_16(i);\n+\n+\t\ts_size_bytes = ((i + 3) / 4) * sizeof(struct roc_sglist_comp);\n+\n+\t\tdlen = g_size_bytes + s_size_bytes + ROC_SG_LIST_HDR_SIZE;\n+\n+\t\tinst->dptr = (uint64_t)in_buffer;\n+\t\tinst->w4.u64 = sess->inst.w4 | dlen;\n+\t\tinst->w4.s.opcode_major |= (uint64_t)ROC_DMA_MODE_SG;\n+\t} else {\n+\t\tstruct roc_sg2list_comp *scatter_comp, *gather_comp;\n+\t\tunion cpt_inst_w5 cpt_inst_w5;\n+\t\tunion cpt_inst_w6 cpt_inst_w6;\n+\t\tuint32_t g_size_bytes;\n+\t\tvoid *m_data;\n+\t\tint i;\n+\n+\t\tm_data = alloc_op_meta(NULL, m_info->mlen, m_info->pool, infl_req);\n+\t\tif (unlikely(m_data == NULL)) {\n+\t\t\tplt_dp_err(\"Error allocating meta buffer for request\");\n+\t\t\treturn -ENOMEM;\n+\t\t}\n+\n+\t\t/* Input Gather List */\n+\t\ti = 0;\n+\t\tgather_comp = (struct roc_sg2list_comp *)((uint8_t *)m_data);\n+\n+\t\ti = fill_ipsec_sg2_comp_from_pkt(gather_comp, i, m_src);\n+\n+\t\tcpt_inst_w5.s.gather_sz = ((i + 2) / 3);\n+\t\tg_size_bytes = ((i + 2) / 3) * sizeof(struct roc_sg2list_comp);\n+\n+\t\t/* Output Scatter List */\n+\t\ti = 0;\n+\t\tscatter_comp = (struct roc_sg2list_comp *)((uint8_t *)gather_comp + g_size_bytes);\n+\t\ti = fill_ipsec_sg2_comp_from_pkt(scatter_comp, i, m_src);\n+\n+\t\tcpt_inst_w6.s.scatter_sz = ((i + 2) / 3);\n+\n+\t\tcpt_inst_w5.s.dptr = (uint64_t)gather_comp;\n+\t\tcpt_inst_w6.s.rptr = (uint64_t)scatter_comp;\n+\n+\t\tinst->w5.u64 = cpt_inst_w5.u64;\n+\t\tinst->w6.u64 = cpt_inst_w6.u64;\n+\t\tinst->w4.u64 = sess->inst.w4 | rte_pktmbuf_pkt_len(m_src);\n+\t\tinst->w4.s.opcode_major &= (~(ROC_IE_OT_INPLACE_BIT));\n+\t}\n \treturn 0;\n }\n \ndiff --git a/drivers/crypto/cnxk/cnxk_sg.h b/drivers/crypto/cnxk/cnxk_sg.h\nindex ead2886e99..65244199bd 100644\n--- a/drivers/crypto/cnxk/cnxk_sg.h\n+++ b/drivers/crypto/cnxk/cnxk_sg.h\n@@ -6,6 +6,7 @@\n #define _CNXK_SG_H_\n \n #include \"roc_cpt_sg.h\"\n+#include \"roc_se.h\"\n \n static __rte_always_inline uint32_t\n fill_sg_comp(struct roc_sglist_comp *list, uint32_t i, phys_addr_t dma_addr, uint32_t size)\n@@ -148,6 +149,28 @@ fill_ipsec_sg_comp_from_pkt(struct roc_sglist_comp *list, uint32_t i, struct rte\n \treturn i;\n }\n \n+static __rte_always_inline uint32_t\n+fill_ipsec_sg2_comp_from_pkt(struct roc_sg2list_comp *list, uint32_t i, struct rte_mbuf *pkt)\n+{\n+\tuint32_t buf_sz;\n+\tvoid *vaddr;\n+\n+\twhile (unlikely(pkt != NULL)) {\n+\t\tstruct roc_sg2list_comp *to = &list[i / 3];\n+\t\tbuf_sz = pkt->data_len;\n+\t\tvaddr = rte_pktmbuf_mtod(pkt, void *);\n+\n+\t\tto->u.s.len[i % 3] = buf_sz;\n+\t\tto->ptr[i % 3] = (uint64_t)vaddr;\n+\t\tto->u.s.valid_segs = (i % 3) + 1;\n+\n+\t\tpkt = pkt->next;\n+\t\ti++;\n+\t}\n+\n+\treturn i;\n+}\n+\n static __rte_always_inline uint32_t\n fill_sg2_comp(struct roc_sg2list_comp *list, uint32_t i, phys_addr_t dma_addr, uint32_t size)\n {\n", "prefixes": [ "09/11" ] }