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{
    "id": 123462,
    "url": "http://patches.dpdk.org/api/patches/123462/?format=api",
    "web_url": "http://patches.dpdk.org/project/dpdk/patch/20230208132824.775985-4-adwivedi@marvell.com/",
    "project": {
        "id": 1,
        "url": "http://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<20230208132824.775985-4-adwivedi@marvell.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/20230208132824.775985-4-adwivedi@marvell.com",
    "date": "2023-02-08T13:28:21",
    "name": "[v10,3/6] ethdev: add trace points for ethdev (part two)",
    "commit_ref": null,
    "pull_url": null,
    "state": "superseded",
    "archived": true,
    "hash": "4734b99d28ab41eaf48195ddd137b5305ba2eb98",
    "submitter": {
        "id": 1561,
        "url": "http://patches.dpdk.org/api/people/1561/?format=api",
        "name": "Ankur Dwivedi",
        "email": "adwivedi@marvell.com"
    },
    "delegate": {
        "id": 319,
        "url": "http://patches.dpdk.org/api/users/319/?format=api",
        "username": "fyigit",
        "first_name": "Ferruh",
        "last_name": "Yigit",
        "email": "ferruh.yigit@amd.com"
    },
    "mbox": "http://patches.dpdk.org/project/dpdk/patch/20230208132824.775985-4-adwivedi@marvell.com/mbox/",
    "series": [
        {
            "id": 26891,
            "url": "http://patches.dpdk.org/api/series/26891/?format=api",
            "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=26891",
            "date": "2023-02-08T13:28:18",
            "name": "add trace points in ethdev library",
            "version": 10,
            "mbox": "http://patches.dpdk.org/series/26891/mbox/"
        }
    ],
    "comments": "http://patches.dpdk.org/api/patches/123462/comments/",
    "check": "success",
    "checks": "http://patches.dpdk.org/api/patches/123462/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@inbox.dpdk.org",
        "Delivered-To": "patchwork@inbox.dpdk.org",
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        ],
        "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-transfer-encoding : content-type; s=pfpt0220;\n bh=atvcjQ1u01IxB1AORl8BiIKZXYtD2TbEuxtenjc8UzI=;\n b=NK4cGaQXpbloHoJXn4hIgNY+jDWphxEGXD+archI3Qnr+D6aXIAii8OjAJwL+JIqOQ0O\n DLKyBliQUEyNSL3f24ZJpljn2csOvjjGpCfxnXVlGz4mblFtqLrGt3FX7K0GwVw+4lDb\n lA0W4g/XdKaTR8muOTIxJtULgC7VzNKyBxGwLkOdMbAX9sHqKGdGUfYCDpYzqQW5gx9w\n rlG14DloOxJ6I2mwDHiNsADgKzT6WUpPnY86JPyNhnIMt44yhGGzkoer5tdZEBDFNk4e\n db2t26Uol3mKbyFyuI9IAdGdHfxVWeAosqpIqEqsqryC+8vRnSj8WCGT0ZeC2w7fkyr/ oQ==",
        "From": "Ankur Dwivedi <adwivedi@marvell.com>",
        "To": "<dev@dpdk.org>",
        "CC": "<thomas@monjalon.net>, <david.marchand@redhat.com>, <mdr@ashroe.eu>,\n <orika@nvidia.com>, <ferruh.yigit@amd.com>, <chas3@att.com>,\n <humin29@huawei.com>, <linville@tuxdriver.com>,\n <ciara.loftus@intel.com>, <qi.z.zhang@intel.com>, <mw@semihalf.com>,\n <mk@semihalf.com>, <shaibran@amazon.com>, <evgenys@amazon.com>,\n <igorch@amazon.com>, <chandu@amd.com>, <irusskikh@marvell.com>,\n <shepard.siegel@atomicrules.com>, <ed.czeck@atomicrules.com>,\n <john.miller@atomicrules.com>, <ajit.khaparde@broadcom.com>,\n <somnath.kotur@broadcom.com>, <jerinj@marvell.com>,\n <mczekaj@marvell.com>, <sthotton@marvell.com>,\n <srinivasan@marvell.com>, <hkalra@marvell.com>,\n <rahul.lakkireddy@chelsio.com>, <johndale@cisco.com>,\n <hyonkim@cisco.com>, <liudongdong3@huawei.com>,\n <yisen.zhuang@huawei.com>, <xuanziyang2@huawei.com>,\n <cloud.wangxiaoyun@huawei.com>, <zhouguoyang@huawei.com>,\n <simei.su@intel.com>, <wenjun1.wu@intel.com>, <qiming.yang@intel.com>,\n <Yuying.Zhang@intel.com>, <beilei.xing@intel.com>,\n <xiao.w.wang@intel.com>, <jingjing.wu@intel.com>,\n <junfeng.guo@intel.com>, <rosen.xu@intel.com>,\n <ndabilpuram@marvell.com>, <kirankumark@marvell.com>,\n <skori@marvell.com>, <skoteshwar@marvell.com>, <lironh@marvell.com>,\n <zr@semihalf.com>, <radhac@marvell.com>, <vburru@marvell.com>,\n <sedara@marvell.com>, <matan@nvidia.com>, <viacheslavo@nvidia.com>,\n <longli@microsoft.com>, <spinler@cesnet.cz>,\n <chaoyong.he@corigine.com>, <niklas.soderlund@corigine.com>,\n <hemant.agrawal@nxp.com>, <sachin.saxena@oss.nxp.com>,\n <g.singh@nxp.com>, <apeksha.gupta@nxp.com>, <sachin.saxena@nxp.com>,\n <aboyer@pensando.io>, <rmody@marvell.com>, <shshaikh@marvell.com>,\n <dsinghrawat@marvell.com>, <andrew.rybchenko@oktetlabs.ru>,\n <jiawenwu@trustnetic.com>, <jianwang@trustnetic.com>,\n <jbehrens@vmware.com>, <maxime.coquelin@redhat.com>,\n <chenbo.xia@intel.com>, <steven.webster@windriver.com>,\n <matt.peters@windriver.com>, <bruce.richardson@intel.com>,\n <mtetsuyah@gmail.com>, <grive@u256.net>, <jasvinder.singh@intel.com>,\n <cristian.dumitrescu@intel.com>, <jgrajcia@cisco.com>,\n <mb@smartsharesystems.com>, Ankur Dwivedi <adwivedi@marvell.com>",
        "Subject": "[PATCH v10 3/6] ethdev: add trace points for ethdev (part two)",
        "Date": "Wed, 8 Feb 2023 18:58:21 +0530",
        "Message-ID": "<20230208132824.775985-4-adwivedi@marvell.com>",
        "X-Mailer": "git-send-email 2.25.1",
        "In-Reply-To": "<20230208132824.775985-1-adwivedi@marvell.com>",
        "References": "<20230207063254.401538-1-adwivedi@marvell.com>\n <20230208132824.775985-1-adwivedi@marvell.com>",
        "MIME-Version": "1.0",
        "Content-Transfer-Encoding": "8bit",
        "Content-Type": "text/plain",
        "X-Proofpoint-GUID": "x2S5TVN4hTCue29a91todOqX8e1x-ZCX",
        "X-Proofpoint-ORIG-GUID": "x2S5TVN4hTCue29a91todOqX8e1x-ZCX",
        "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.219,Aquarius:18.0.930,Hydra:6.0.562,FMLib:17.11.122.1\n definitions=2023-02-08_05,2023-02-08_02,2022-06-22_01",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.29",
        "Precedence": "list",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
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        "List-Archive": "<http://mails.dpdk.org/archives/dev/>",
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        "Errors-To": "dev-bounces@dpdk.org"
    },
    "content": "Adds trace points for remaining ethdev functions.\n\nSigned-off-by: Ankur Dwivedi <adwivedi@marvell.com>\nAcked-by: Sunil Kumar Kori <skori@marvell.com>\n---\n lib/ethdev/ethdev_trace.h        | 875 +++++++++++++++++++++++++++++++\n lib/ethdev/ethdev_trace_points.c | 252 +++++++++\n lib/ethdev/rte_ethdev.c          | 485 ++++++++++++++---\n lib/ethdev/rte_ethdev_cman.c     |  29 +-\n 4 files changed, 1559 insertions(+), 82 deletions(-)",
    "diff": "diff --git a/lib/ethdev/ethdev_trace.h b/lib/ethdev/ethdev_trace.h\nindex d88ad60ec8..1a4b7c3a9b 100644\n--- a/lib/ethdev/ethdev_trace.h\n+++ b/lib/ethdev/ethdev_trace.h\n@@ -586,6 +586,801 @@ RTE_TRACE_POINT(\n \trte_trace_point_emit_int(ret);\n )\n \n+RTE_TRACE_POINT(\n+\trte_ethdev_trace_info_get,\n+\tRTE_TRACE_POINT_ARGS(uint16_t port_id,\n+\t\tconst struct rte_eth_dev_info *dev_info),\n+\trte_trace_point_emit_u16(port_id);\n+\trte_trace_point_emit_string(dev_info->driver_name);\n+\trte_trace_point_emit_u16(dev_info->min_mtu);\n+\trte_trace_point_emit_u16(dev_info->max_mtu);\n+\trte_trace_point_emit_u32(dev_info->min_rx_bufsize);\n+\trte_trace_point_emit_u32(dev_info->max_rx_pktlen);\n+\trte_trace_point_emit_u16(dev_info->max_rx_queues);\n+\trte_trace_point_emit_u16(dev_info->max_tx_queues);\n+\trte_trace_point_emit_u32(dev_info->max_mac_addrs);\n+\trte_trace_point_emit_u64(dev_info->rx_offload_capa);\n+\trte_trace_point_emit_u64(dev_info->tx_offload_capa);\n+\trte_trace_point_emit_u64(dev_info->rx_queue_offload_capa);\n+\trte_trace_point_emit_u64(dev_info->tx_queue_offload_capa);\n+\trte_trace_point_emit_u16(dev_info->reta_size);\n+\trte_trace_point_emit_u8(dev_info->hash_key_size);\n+\trte_trace_point_emit_u64(dev_info->flow_type_rss_offloads);\n+\trte_trace_point_emit_u16(dev_info->rx_desc_lim.nb_max);\n+\trte_trace_point_emit_u16(dev_info->rx_desc_lim.nb_min);\n+\trte_trace_point_emit_u16(dev_info->rx_desc_lim.nb_align);\n+\trte_trace_point_emit_u16(dev_info->tx_desc_lim.nb_max);\n+\trte_trace_point_emit_u16(dev_info->tx_desc_lim.nb_min);\n+\trte_trace_point_emit_u16(dev_info->tx_desc_lim.nb_align);\n+\trte_trace_point_emit_u32(dev_info->speed_capa);\n+\trte_trace_point_emit_u16(dev_info->nb_rx_queues);\n+\trte_trace_point_emit_u16(dev_info->nb_tx_queues);\n+\trte_trace_point_emit_u64(dev_info->dev_capa);\n+)\n+\n+RTE_TRACE_POINT(\n+\trte_ethdev_trace_conf_get,\n+\tRTE_TRACE_POINT_ARGS(uint16_t port_id,\n+\t\tconst struct rte_eth_conf *dev_conf),\n+\trte_trace_point_emit_u16(port_id);\n+\trte_trace_point_emit_u32(dev_conf->link_speeds);\n+\trte_trace_point_emit_u64(dev_conf->rxmode.offloads);\n+\trte_trace_point_emit_u64(dev_conf->txmode.offloads);\n+\trte_trace_point_emit_u32(dev_conf->lpbk_mode);\n+)\n+\n+RTE_TRACE_POINT(\n+\trte_ethdev_trace_get_supported_ptypes,\n+\tRTE_TRACE_POINT_ARGS(uint16_t port_id, int supported_num, int num,\n+\t\tuint32_t ptypes),\n+\trte_trace_point_emit_u16(port_id);\n+\trte_trace_point_emit_int(supported_num);\n+\trte_trace_point_emit_int(num);\n+\trte_trace_point_emit_u32(ptypes);\n+)\n+\n+RTE_TRACE_POINT(\n+\trte_ethdev_trace_set_ptypes,\n+\tRTE_TRACE_POINT_ARGS(uint16_t port_id, int supported_num,\n+\t\tunsigned int num, uint32_t set_ptypes),\n+\trte_trace_point_emit_u16(port_id);\n+\trte_trace_point_emit_int(supported_num);\n+\trte_trace_point_emit_u32(num);\n+\trte_trace_point_emit_u32(set_ptypes);\n+)\n+\n+RTE_TRACE_POINT(\n+\trte_eth_trace_macaddrs_get,\n+\tRTE_TRACE_POINT_ARGS(uint16_t port_id, unsigned int num),\n+\trte_trace_point_emit_u16(port_id);\n+\trte_trace_point_emit_u32(num);\n+)\n+\n+RTE_TRACE_POINT(\n+\trte_ethdev_trace_set_mtu,\n+\tRTE_TRACE_POINT_ARGS(uint16_t port_id, uint16_t mtu, int ret),\n+\trte_trace_point_emit_u16(port_id);\n+\trte_trace_point_emit_u16(mtu);\n+\trte_trace_point_emit_int(ret);\n+)\n+\n+RTE_TRACE_POINT(\n+\trte_ethdev_trace_vlan_filter,\n+\tRTE_TRACE_POINT_ARGS(uint16_t port_id, uint16_t vlan_id, int on,\n+\t\tint ret),\n+\trte_trace_point_emit_u16(port_id);\n+\trte_trace_point_emit_u16(vlan_id);\n+\trte_trace_point_emit_int(on);\n+\trte_trace_point_emit_int(ret);\n+)\n+\n+RTE_TRACE_POINT(\n+\trte_ethdev_trace_set_vlan_strip_on_queue,\n+\tRTE_TRACE_POINT_ARGS(uint16_t port_id, uint16_t rx_queue_id, int on),\n+\trte_trace_point_emit_u16(port_id);\n+\trte_trace_point_emit_u16(rx_queue_id);\n+\trte_trace_point_emit_int(on);\n+)\n+\n+RTE_TRACE_POINT(\n+\trte_ethdev_trace_set_vlan_ether_type,\n+\tRTE_TRACE_POINT_ARGS(uint16_t port_id, enum rte_vlan_type vlan_type,\n+\t\tuint16_t tag_type, int ret),\n+\trte_trace_point_emit_u16(port_id);\n+\trte_trace_point_emit_int(vlan_type);\n+\trte_trace_point_emit_u16(tag_type);\n+\trte_trace_point_emit_int(ret);\n+)\n+\n+RTE_TRACE_POINT(\n+\trte_ethdev_trace_set_vlan_offload,\n+\tRTE_TRACE_POINT_ARGS(uint16_t port_id, int offload_mask, int ret),\n+\trte_trace_point_emit_u16(port_id);\n+\trte_trace_point_emit_int(offload_mask);\n+\trte_trace_point_emit_int(ret);\n+)\n+\n+RTE_TRACE_POINT(\n+\trte_ethdev_trace_get_vlan_offload,\n+\tRTE_TRACE_POINT_ARGS(uint16_t port_id, int ret),\n+\trte_trace_point_emit_u16(port_id);\n+\trte_trace_point_emit_int(ret);\n+)\n+\n+RTE_TRACE_POINT(\n+\trte_ethdev_trace_set_vlan_pvid,\n+\tRTE_TRACE_POINT_ARGS(uint16_t port_id, uint16_t pvid, int on, int ret),\n+\trte_trace_point_emit_u16(port_id);\n+\trte_trace_point_emit_u16(pvid);\n+\trte_trace_point_emit_int(on);\n+\trte_trace_point_emit_int(ret);\n+)\n+\n+RTE_TRACE_POINT(\n+\trte_ethdev_trace_flow_ctrl_get,\n+\tRTE_TRACE_POINT_ARGS(uint16_t port_id,\n+\t\tconst struct rte_eth_fc_conf *fc_conf, int ret),\n+\trte_trace_point_emit_u16(port_id);\n+\trte_trace_point_emit_u32(fc_conf->high_water);\n+\trte_trace_point_emit_u32(fc_conf->low_water);\n+\trte_trace_point_emit_u16(fc_conf->pause_time);\n+\trte_trace_point_emit_u16(fc_conf->send_xon);\n+\trte_trace_point_emit_int(fc_conf->mode);\n+\trte_trace_point_emit_u8(fc_conf->mac_ctrl_frame_fwd);\n+\trte_trace_point_emit_u8(fc_conf->autoneg);\n+\trte_trace_point_emit_int(ret);\n+)\n+\n+RTE_TRACE_POINT(\n+\trte_ethdev_trace_flow_ctrl_set,\n+\tRTE_TRACE_POINT_ARGS(uint16_t port_id,\n+\t\tconst struct rte_eth_fc_conf *fc_conf, int ret),\n+\trte_trace_point_emit_u16(port_id);\n+\trte_trace_point_emit_u32(fc_conf->high_water);\n+\trte_trace_point_emit_u32(fc_conf->low_water);\n+\trte_trace_point_emit_u16(fc_conf->pause_time);\n+\trte_trace_point_emit_u16(fc_conf->send_xon);\n+\trte_trace_point_emit_int(fc_conf->mode);\n+\trte_trace_point_emit_u8(fc_conf->mac_ctrl_frame_fwd);\n+\trte_trace_point_emit_u8(fc_conf->autoneg);\n+\trte_trace_point_emit_int(ret);\n+)\n+\n+RTE_TRACE_POINT(\n+\trte_ethdev_trace_priority_flow_ctrl_set,\n+\tRTE_TRACE_POINT_ARGS(uint16_t port_id,\n+\t\tconst struct rte_eth_pfc_conf *pfc_conf, int ret),\n+\trte_trace_point_emit_u16(port_id);\n+\trte_trace_point_emit_u32(pfc_conf->fc.high_water);\n+\trte_trace_point_emit_u32(pfc_conf->fc.low_water);\n+\trte_trace_point_emit_u16(pfc_conf->fc.pause_time);\n+\trte_trace_point_emit_u16(pfc_conf->fc.send_xon);\n+\trte_trace_point_emit_int(pfc_conf->fc.mode);\n+\trte_trace_point_emit_u8(pfc_conf->fc.mac_ctrl_frame_fwd);\n+\trte_trace_point_emit_u8(pfc_conf->fc.autoneg);\n+\trte_trace_point_emit_u8(pfc_conf->priority);\n+\trte_trace_point_emit_int(ret);\n+)\n+\n+RTE_TRACE_POINT(\n+\trte_ethdev_trace_priority_flow_ctrl_queue_info_get,\n+\tRTE_TRACE_POINT_ARGS(uint16_t port_id,\n+\t\tconst struct rte_eth_pfc_queue_info *pfc_queue_info, int ret),\n+\trte_trace_point_emit_u16(port_id);\n+\trte_trace_point_emit_u8(pfc_queue_info->tc_max);\n+\trte_trace_point_emit_int(pfc_queue_info->mode_capa);\n+\trte_trace_point_emit_int(ret);\n+)\n+\n+RTE_TRACE_POINT(\n+\trte_ethdev_trace_priority_flow_ctrl_queue_configure,\n+\tRTE_TRACE_POINT_ARGS(uint16_t port_id,\n+\t\tconst struct rte_eth_pfc_queue_conf *pfc_queue_conf, int ret),\n+\trte_trace_point_emit_u16(port_id);\n+\trte_trace_point_emit_int(pfc_queue_conf->mode);\n+\trte_trace_point_emit_u16(pfc_queue_conf->rx_pause.tx_qid);\n+\trte_trace_point_emit_u16(pfc_queue_conf->tx_pause.rx_qid);\n+\trte_trace_point_emit_int(ret);\n+)\n+\n+RTE_TRACE_POINT(\n+\trte_ethdev_trace_rss_reta_update,\n+\tRTE_TRACE_POINT_ARGS(uint16_t port_id,\n+\t\tconst struct rte_eth_rss_reta_entry64 *reta_conf,\n+\t\tuint16_t reta_size, int ret),\n+\trte_trace_point_emit_u16(port_id);\n+\trte_trace_point_emit_u64(reta_conf->mask);\n+\trte_trace_point_emit_u16(reta_size);\n+\trte_trace_point_emit_int(ret);\n+)\n+\n+RTE_TRACE_POINT(\n+\trte_ethdev_trace_rss_reta_query,\n+\tRTE_TRACE_POINT_ARGS(uint16_t port_id,\n+\t\tconst struct rte_eth_rss_reta_entry64 *reta_conf,\n+\t\tuint16_t reta_size, int ret),\n+\trte_trace_point_emit_u16(port_id);\n+\trte_trace_point_emit_u64(reta_conf->mask);\n+\trte_trace_point_emit_u16(reta_size);\n+\trte_trace_point_emit_int(ret);\n+)\n+\n+RTE_TRACE_POINT(\n+\trte_ethdev_trace_rss_hash_update,\n+\tRTE_TRACE_POINT_ARGS(uint16_t port_id,\n+\t\tconst struct rte_eth_rss_conf *rss_conf, int ret),\n+\trte_trace_point_emit_u16(port_id);\n+\trte_trace_point_emit_ptr(rss_conf->rss_key);\n+\trte_trace_point_emit_u8(rss_conf->rss_key_len);\n+\trte_trace_point_emit_u64(rss_conf->rss_hf);\n+\trte_trace_point_emit_int(ret);\n+)\n+\n+RTE_TRACE_POINT(\n+\trte_ethdev_trace_rss_hash_conf_get,\n+\tRTE_TRACE_POINT_ARGS(uint16_t port_id,\n+\t\tconst struct rte_eth_rss_conf *rss_conf, int ret),\n+\trte_trace_point_emit_u16(port_id);\n+\trte_trace_point_emit_ptr(rss_conf->rss_key);\n+\trte_trace_point_emit_u8(rss_conf->rss_key_len);\n+\trte_trace_point_emit_u64(rss_conf->rss_hf);\n+\trte_trace_point_emit_int(ret);\n+)\n+\n+RTE_TRACE_POINT(\n+\trte_ethdev_trace_udp_tunnel_port_add,\n+\tRTE_TRACE_POINT_ARGS(uint16_t port_id,\n+\t\tconst struct rte_eth_udp_tunnel *tunnel_udp, int ret),\n+\trte_trace_point_emit_u16(port_id);\n+\trte_trace_point_emit_u16(tunnel_udp->udp_port);\n+\trte_trace_point_emit_u8(tunnel_udp->prot_type);\n+\trte_trace_point_emit_int(ret);\n+)\n+\n+RTE_TRACE_POINT(\n+\trte_ethdev_trace_udp_tunnel_port_delete,\n+\tRTE_TRACE_POINT_ARGS(uint16_t port_id,\n+\t\tconst struct rte_eth_udp_tunnel *tunnel_udp, int ret),\n+\trte_trace_point_emit_u16(port_id);\n+\trte_trace_point_emit_u16(tunnel_udp->udp_port);\n+\trte_trace_point_emit_u8(tunnel_udp->prot_type);\n+\trte_trace_point_emit_int(ret);\n+)\n+\n+RTE_TRACE_POINT(\n+\trte_eth_trace_led_on,\n+\tRTE_TRACE_POINT_ARGS(uint16_t port_id, int ret),\n+\trte_trace_point_emit_u16(port_id);\n+\trte_trace_point_emit_int(ret);\n+)\n+\n+RTE_TRACE_POINT(\n+\trte_eth_trace_led_off,\n+\tRTE_TRACE_POINT_ARGS(uint16_t port_id, int ret),\n+\trte_trace_point_emit_u16(port_id);\n+\trte_trace_point_emit_int(ret);\n+)\n+\n+RTE_TRACE_POINT(\n+\trte_eth_trace_fec_get_capability,\n+\tRTE_TRACE_POINT_ARGS(uint16_t port_id,\n+\t\tconst struct rte_eth_fec_capa *speed_fec_capa,\n+\t\tunsigned int num, int ret),\n+\trte_trace_point_emit_u16(port_id);\n+\trte_trace_point_emit_u32(speed_fec_capa->speed);\n+\trte_trace_point_emit_u32(speed_fec_capa->capa);\n+\trte_trace_point_emit_u32(num);\n+\trte_trace_point_emit_int(ret);\n+)\n+\n+RTE_TRACE_POINT(\n+\trte_eth_trace_fec_get,\n+\tRTE_TRACE_POINT_ARGS(uint16_t port_id, const uint32_t *fec_capa,\n+\t\tint ret),\n+\trte_trace_point_emit_u16(port_id);\n+\trte_trace_point_emit_ptr(fec_capa);\n+\trte_trace_point_emit_int(ret);\n+)\n+\n+RTE_TRACE_POINT(\n+\trte_eth_trace_fec_set,\n+\tRTE_TRACE_POINT_ARGS(uint16_t port_id, uint32_t fec_capa, int ret),\n+\trte_trace_point_emit_u16(port_id);\n+\trte_trace_point_emit_u32(fec_capa);\n+\trte_trace_point_emit_int(ret);\n+)\n+\n+RTE_TRACE_POINT(\n+\trte_ethdev_trace_mac_addr_add,\n+\tRTE_TRACE_POINT_ARGS(uint16_t port_id,\n+\t\tconst struct rte_ether_addr *addr, uint32_t pool, int ret),\n+\tuint8_t len = RTE_ETHER_ADDR_LEN;\n+\n+\trte_trace_point_emit_u16(port_id);\n+\trte_trace_point_emit_blob(addr->addr_bytes, len);\n+\trte_trace_point_emit_u32(pool);\n+\trte_trace_point_emit_int(ret);\n+)\n+\n+RTE_TRACE_POINT(\n+\trte_ethdev_trace_mac_addr_remove,\n+\tRTE_TRACE_POINT_ARGS(uint16_t port_id,\n+\t\tconst struct rte_ether_addr *addr),\n+\tuint8_t len = RTE_ETHER_ADDR_LEN;\n+\n+\trte_trace_point_emit_u16(port_id);\n+\trte_trace_point_emit_blob(addr->addr_bytes, len);\n+)\n+\n+RTE_TRACE_POINT(\n+\trte_ethdev_trace_default_mac_addr_set,\n+\tRTE_TRACE_POINT_ARGS(uint16_t port_id,\n+\t\tconst struct rte_ether_addr *addr),\n+\tuint8_t len = RTE_ETHER_ADDR_LEN;\n+\n+\trte_trace_point_emit_u16(port_id);\n+\trte_trace_point_emit_blob(addr->addr_bytes, len);\n+)\n+\n+RTE_TRACE_POINT(\n+\trte_ethdev_trace_uc_hash_table_set,\n+\tRTE_TRACE_POINT_ARGS(uint16_t port_id, uint8_t on, int ret),\n+\trte_trace_point_emit_u16(port_id);\n+\trte_trace_point_emit_u8(on);\n+\trte_trace_point_emit_int(ret);\n+)\n+\n+RTE_TRACE_POINT(\n+\trte_ethdev_trace_uc_all_hash_table_set,\n+\tRTE_TRACE_POINT_ARGS(uint16_t port_id, uint8_t on, int ret),\n+\trte_trace_point_emit_u16(port_id);\n+\trte_trace_point_emit_u8(on);\n+\trte_trace_point_emit_int(ret);\n+)\n+\n+RTE_TRACE_POINT(\n+\trte_eth_trace_set_queue_rate_limit,\n+\tRTE_TRACE_POINT_ARGS(uint16_t port_id, uint16_t queue_idx,\n+\t\tuint16_t tx_rate, int ret),\n+\trte_trace_point_emit_u16(port_id);\n+\trte_trace_point_emit_u16(queue_idx);\n+\trte_trace_point_emit_u16(tx_rate);\n+\trte_trace_point_emit_int(ret);\n+)\n+\n+RTE_TRACE_POINT(\n+\trte_eth_trace_rx_avail_thresh_set,\n+\tRTE_TRACE_POINT_ARGS(uint16_t port_id, uint16_t queue_id,\n+\t\tuint8_t avail_thresh, int ret),\n+\trte_trace_point_emit_u16(port_id);\n+\trte_trace_point_emit_u16(queue_id);\n+\trte_trace_point_emit_u8(avail_thresh);\n+\trte_trace_point_emit_int(ret);\n+)\n+\n+RTE_TRACE_POINT(\n+\trte_eth_trace_rx_avail_thresh_query,\n+\tRTE_TRACE_POINT_ARGS(uint16_t port_id, uint16_t queue_id, int ret),\n+\trte_trace_point_emit_u16(port_id);\n+\trte_trace_point_emit_u16(queue_id);\n+\trte_trace_point_emit_int(ret);\n+)\n+\n+RTE_TRACE_POINT(\n+\trte_ethdev_trace_callback_register,\n+\tRTE_TRACE_POINT_ARGS(uint16_t port_id, enum rte_eth_event_type event,\n+\t\trte_eth_dev_cb_fn cb_fn, const void *cb_arg),\n+\trte_trace_point_emit_u16(port_id);\n+\trte_trace_point_emit_int(event);\n+\trte_trace_point_emit_ptr(cb_fn);\n+\trte_trace_point_emit_ptr(cb_arg);\n+)\n+\n+RTE_TRACE_POINT(\n+\trte_ethdev_trace_callback_unregister,\n+\tRTE_TRACE_POINT_ARGS(uint16_t port_id, enum rte_eth_event_type event,\n+\t\trte_eth_dev_cb_fn cb_fn, const void *cb_arg, int ret),\n+\trte_trace_point_emit_u16(port_id);\n+\trte_trace_point_emit_int(event);\n+\trte_trace_point_emit_ptr(cb_fn);\n+\trte_trace_point_emit_ptr(cb_arg);\n+\trte_trace_point_emit_int(ret);\n+)\n+\n+RTE_TRACE_POINT(\n+\trte_ethdev_trace_rx_intr_ctl,\n+\tRTE_TRACE_POINT_ARGS(uint16_t port_id, uint16_t qid, int epfd, int op,\n+\t\tconst void *data, int rc),\n+\trte_trace_point_emit_u16(port_id);\n+\trte_trace_point_emit_u16(qid);\n+\trte_trace_point_emit_int(epfd);\n+\trte_trace_point_emit_int(op);\n+\trte_trace_point_emit_ptr(data);\n+\trte_trace_point_emit_int(rc);\n+)\n+\n+RTE_TRACE_POINT(\n+\trte_ethdev_trace_rx_intr_ctl_q_get_fd,\n+\tRTE_TRACE_POINT_ARGS(uint16_t port_id, uint16_t queue_id, int fd),\n+\trte_trace_point_emit_u16(port_id);\n+\trte_trace_point_emit_u16(queue_id);\n+\trte_trace_point_emit_int(fd);\n+)\n+\n+RTE_TRACE_POINT(\n+\trte_ethdev_trace_rx_intr_ctl_q,\n+\tRTE_TRACE_POINT_ARGS(uint16_t port_id, uint16_t queue_id, int epfd,\n+\t\tint op, const void *data, int rc),\n+\trte_trace_point_emit_u16(port_id);\n+\trte_trace_point_emit_u16(queue_id);\n+\trte_trace_point_emit_int(epfd);\n+\trte_trace_point_emit_int(op);\n+\trte_trace_point_emit_ptr(data);\n+\trte_trace_point_emit_int(rc);\n+)\n+\n+RTE_TRACE_POINT(\n+\trte_eth_trace_add_rx_callback,\n+\tRTE_TRACE_POINT_ARGS(uint16_t port_id, uint16_t queue_id,\n+\t\trte_rx_callback_fn fn, void *user_param,\n+\t\tconst struct rte_eth_rxtx_callback *cb),\n+\trte_trace_point_emit_u16(port_id);\n+\trte_trace_point_emit_u16(queue_id);\n+\trte_trace_point_emit_ptr(fn);\n+\trte_trace_point_emit_ptr(user_param);\n+\trte_trace_point_emit_ptr(cb);\n+)\n+\n+RTE_TRACE_POINT(\n+\trte_eth_trace_add_first_rx_callback,\n+\tRTE_TRACE_POINT_ARGS(uint16_t port_id, uint16_t queue_id,\n+\t\trte_rx_callback_fn fn, const void *user_param,\n+\t\tconst struct rte_eth_rxtx_callback *cb),\n+\trte_trace_point_emit_u16(port_id);\n+\trte_trace_point_emit_u16(queue_id);\n+\trte_trace_point_emit_ptr(fn);\n+\trte_trace_point_emit_ptr(user_param);\n+\trte_trace_point_emit_ptr(cb);\n+)\n+\n+RTE_TRACE_POINT(\n+\trte_eth_trace_add_tx_callback,\n+\tRTE_TRACE_POINT_ARGS(uint16_t port_id, uint16_t queue_id,\n+\t\trte_tx_callback_fn fn, const void *user_param,\n+\t\tconst struct rte_eth_rxtx_callback *cb),\n+\trte_trace_point_emit_u16(port_id);\n+\trte_trace_point_emit_u16(queue_id);\n+\trte_trace_point_emit_ptr(fn);\n+\trte_trace_point_emit_ptr(user_param);\n+\trte_trace_point_emit_ptr(cb);\n+)\n+\n+RTE_TRACE_POINT(\n+\trte_eth_trace_remove_rx_callback,\n+\tRTE_TRACE_POINT_ARGS(uint16_t port_id, uint16_t queue_id,\n+\t\tconst struct rte_eth_rxtx_callback *user_cb, int ret),\n+\trte_trace_point_emit_u16(port_id);\n+\trte_trace_point_emit_u16(queue_id);\n+\trte_trace_point_emit_ptr(user_cb);\n+\trte_trace_point_emit_int(ret);\n+)\n+\n+RTE_TRACE_POINT(\n+\trte_eth_trace_remove_tx_callback,\n+\tRTE_TRACE_POINT_ARGS(uint16_t port_id, uint16_t queue_id,\n+\t\tconst struct rte_eth_rxtx_callback *user_cb, int ret),\n+\trte_trace_point_emit_u16(port_id);\n+\trte_trace_point_emit_u16(queue_id);\n+\trte_trace_point_emit_ptr(user_cb);\n+\trte_trace_point_emit_int(ret);\n+)\n+\n+RTE_TRACE_POINT(\n+\trte_eth_trace_rx_queue_info_get,\n+\tRTE_TRACE_POINT_ARGS(uint16_t port_id, uint16_t queue_id,\n+\t\tconst struct rte_eth_rxq_info *qinfo),\n+\trte_trace_point_emit_u16(port_id);\n+\trte_trace_point_emit_u16(queue_id);\n+\trte_trace_point_emit_ptr(qinfo->mp);\n+\trte_trace_point_emit_u8(qinfo->conf.rx_drop_en);\n+\trte_trace_point_emit_u64(qinfo->conf.offloads);\n+\trte_trace_point_emit_u8(qinfo->scattered_rx);\n+\trte_trace_point_emit_u8(qinfo->queue_state);\n+\trte_trace_point_emit_u16(qinfo->nb_desc);\n+\trte_trace_point_emit_u16(qinfo->rx_buf_size);\n+)\n+\n+RTE_TRACE_POINT(\n+\trte_eth_trace_tx_queue_info_get,\n+\tRTE_TRACE_POINT_ARGS(uint16_t port_id, uint16_t queue_id,\n+\t\tconst struct rte_eth_txq_info *qinfo),\n+\trte_trace_point_emit_u16(port_id);\n+\trte_trace_point_emit_u16(queue_id);\n+\trte_trace_point_emit_u16(qinfo->nb_desc);\n+\trte_trace_point_emit_u8(qinfo->queue_state);\n+)\n+\n+RTE_TRACE_POINT(\n+\trte_eth_trace_rx_burst_mode_get,\n+\tRTE_TRACE_POINT_ARGS(uint16_t port_id, uint16_t queue_id,\n+\t\tconst struct rte_eth_burst_mode *mode, int ret),\n+\trte_trace_point_emit_u16(port_id);\n+\trte_trace_point_emit_u16(queue_id);\n+\trte_trace_point_emit_u64(mode->flags);\n+\trte_trace_point_emit_int(ret);\n+)\n+\n+RTE_TRACE_POINT(\n+\trte_eth_trace_tx_burst_mode_get,\n+\tRTE_TRACE_POINT_ARGS(uint16_t port_id, uint16_t queue_id,\n+\t\tconst struct rte_eth_burst_mode *mode, int ret),\n+\trte_trace_point_emit_u16(port_id);\n+\trte_trace_point_emit_u16(queue_id);\n+\trte_trace_point_emit_u64(mode->flags);\n+\trte_trace_point_emit_int(ret);\n+)\n+\n+RTE_TRACE_POINT(\n+\trte_eth_trace_get_monitor_addr,\n+\tRTE_TRACE_POINT_ARGS(uint16_t port_id, uint16_t queue_id,\n+\t\tconst struct rte_power_monitor_cond *pmc, int ret),\n+\trte_trace_point_emit_u16(port_id);\n+\trte_trace_point_emit_u16(queue_id);\n+\trte_trace_point_emit_ptr(pmc->addr);\n+\trte_trace_point_emit_u8(pmc->size);\n+\trte_trace_point_emit_int(ret);\n+)\n+\n+RTE_TRACE_POINT(\n+\trte_ethdev_trace_set_mc_addr_list,\n+\tRTE_TRACE_POINT_ARGS(uint16_t port_id,\n+\t\tconst struct rte_ether_addr *mc_addr_set, uint32_t nb_mc_addr,\n+\t\tint ret),\n+\trte_trace_point_emit_u16(port_id);\n+\trte_trace_point_emit_ptr(mc_addr_set);\n+\trte_trace_point_emit_u32(nb_mc_addr);\n+\trte_trace_point_emit_int(ret);\n+)\n+\n+RTE_TRACE_POINT(\n+\trte_eth_trace_timesync_enable,\n+\tRTE_TRACE_POINT_ARGS(uint16_t port_id, int ret),\n+\trte_trace_point_emit_u16(port_id);\n+\trte_trace_point_emit_int(ret);\n+)\n+\n+RTE_TRACE_POINT(\n+\trte_eth_trace_timesync_disable,\n+\tRTE_TRACE_POINT_ARGS(uint16_t port_id, int ret),\n+\trte_trace_point_emit_u16(port_id);\n+\trte_trace_point_emit_int(ret);\n+)\n+\n+RTE_TRACE_POINT(\n+\trte_eth_trace_timesync_write_time,\n+\tRTE_TRACE_POINT_ARGS(uint16_t port_id, const struct timespec *time,\n+\t\tint ret),\n+\trte_trace_point_emit_u16(port_id);\n+\trte_trace_point_emit_size_t(time->tv_sec);\n+\trte_trace_point_emit_long(time->tv_nsec);\n+\trte_trace_point_emit_int(ret);\n+)\n+\n+RTE_TRACE_POINT(\n+\trte_eth_trace_read_clock,\n+\tRTE_TRACE_POINT_ARGS(uint16_t port_id, const uint64_t *clk, int ret),\n+\tuint64_t clk_v = *clk;\n+\n+\trte_trace_point_emit_u16(port_id);\n+\trte_trace_point_emit_u64(clk_v);\n+\trte_trace_point_emit_int(ret);\n+)\n+\n+RTE_TRACE_POINT(\n+\trte_ethdev_trace_get_reg_info,\n+\tRTE_TRACE_POINT_ARGS(uint16_t port_id,\n+\t\tconst struct rte_dev_reg_info *info, int ret),\n+\trte_trace_point_emit_u16(port_id);\n+\trte_trace_point_emit_ptr(info->data);\n+\trte_trace_point_emit_u32(info->offset);\n+\trte_trace_point_emit_u32(info->length);\n+\trte_trace_point_emit_u32(info->width);\n+\trte_trace_point_emit_u32(info->version);\n+\trte_trace_point_emit_int(ret);\n+)\n+\n+RTE_TRACE_POINT(\n+\trte_ethdev_trace_get_eeprom_length,\n+\tRTE_TRACE_POINT_ARGS(uint16_t port_id, int ret),\n+\trte_trace_point_emit_u16(port_id);\n+\trte_trace_point_emit_int(ret);\n+)\n+\n+RTE_TRACE_POINT(\n+\trte_ethdev_trace_get_eeprom,\n+\tRTE_TRACE_POINT_ARGS(uint16_t port_id,\n+\t\tconst struct rte_dev_eeprom_info *info, int ret),\n+\trte_trace_point_emit_u16(port_id);\n+\trte_trace_point_emit_ptr(info->data);\n+\trte_trace_point_emit_u32(info->offset);\n+\trte_trace_point_emit_u32(info->length);\n+\trte_trace_point_emit_u32(info->magic);\n+\trte_trace_point_emit_int(ret);\n+)\n+\n+RTE_TRACE_POINT(\n+\trte_ethdev_trace_set_eeprom,\n+\tRTE_TRACE_POINT_ARGS(uint16_t port_id,\n+\t\tconst struct rte_dev_eeprom_info *info, int ret),\n+\trte_trace_point_emit_u16(port_id);\n+\trte_trace_point_emit_ptr(info->data);\n+\trte_trace_point_emit_u32(info->offset);\n+\trte_trace_point_emit_u32(info->length);\n+\trte_trace_point_emit_u32(info->magic);\n+\trte_trace_point_emit_int(ret);\n+)\n+\n+RTE_TRACE_POINT(\n+\trte_ethdev_trace_get_module_info,\n+\tRTE_TRACE_POINT_ARGS(uint16_t port_id,\n+\t\tconst struct rte_eth_dev_module_info *modinfo, int ret),\n+\trte_trace_point_emit_u16(port_id);\n+\trte_trace_point_emit_u32(modinfo->type);\n+\trte_trace_point_emit_u32(modinfo->eeprom_len);\n+\trte_trace_point_emit_int(ret);\n+)\n+\n+RTE_TRACE_POINT(\n+\trte_ethdev_trace_get_module_eeprom,\n+\tRTE_TRACE_POINT_ARGS(uint16_t port_id,\n+\t\tconst struct rte_dev_eeprom_info *info, int ret),\n+\trte_trace_point_emit_u16(port_id);\n+\trte_trace_point_emit_ptr(info->data);\n+\trte_trace_point_emit_u32(info->offset);\n+\trte_trace_point_emit_u32(info->length);\n+\trte_trace_point_emit_u32(info->magic);\n+\trte_trace_point_emit_int(ret);\n+)\n+\n+RTE_TRACE_POINT(\n+\trte_ethdev_trace_get_dcb_info,\n+\tRTE_TRACE_POINT_ARGS(uint16_t port_id,\n+\t\tconst struct rte_eth_dcb_info *dcb_info, int ret),\n+\tuint8_t num_user_priorities = RTE_ETH_DCB_NUM_USER_PRIORITIES;\n+\tuint8_t num_tcs = RTE_ETH_DCB_NUM_TCS;\n+\n+\trte_trace_point_emit_u16(port_id);\n+\trte_trace_point_emit_u8(dcb_info->nb_tcs);\n+\trte_trace_point_emit_blob(dcb_info->prio_tc, num_user_priorities);\n+\trte_trace_point_emit_blob(dcb_info->tc_bws, num_tcs);\n+\trte_trace_point_emit_int(ret);\n+)\n+\n+RTE_TRACE_POINT(\n+\trte_ethdev_trace_adjust_nb_rx_tx_desc,\n+\tRTE_TRACE_POINT_ARGS(uint16_t port_id),\n+\trte_trace_point_emit_u16(port_id);\n+)\n+\n+RTE_TRACE_POINT(\n+\trte_ethdev_trace_hairpin_capability_get,\n+\tRTE_TRACE_POINT_ARGS(uint16_t port_id,\n+\t\tconst struct rte_eth_hairpin_cap *cap, int ret),\n+\trte_trace_point_emit_u16(port_id);\n+\trte_trace_point_emit_u16(cap->max_nb_queues);\n+\trte_trace_point_emit_u16(cap->max_rx_2_tx);\n+\trte_trace_point_emit_u16(cap->max_tx_2_rx);\n+\trte_trace_point_emit_u16(cap->max_nb_desc);\n+\trte_trace_point_emit_int(ret);\n+)\n+\n+RTE_TRACE_POINT(\n+\trte_ethdev_trace_pool_ops_supported,\n+\tRTE_TRACE_POINT_ARGS(uint16_t port_id, const char *pool, int ret),\n+\trte_trace_point_emit_u16(port_id);\n+\trte_trace_point_emit_string(pool);\n+\trte_trace_point_emit_int(ret);\n+)\n+\n+RTE_TRACE_POINT(\n+\trte_eth_trace_representor_info_get,\n+\tRTE_TRACE_POINT_ARGS(uint16_t port_id,\n+\t\tconst struct rte_eth_representor_info *info, int ret),\n+\trte_trace_point_emit_u16(port_id);\n+\trte_trace_point_emit_ptr(info);\n+\trte_trace_point_emit_int(ret);\n+)\n+\n+RTE_TRACE_POINT(\n+\trte_eth_trace_rx_metadata_negotiate,\n+\tRTE_TRACE_POINT_ARGS(uint16_t port_id, uint64_t features_val, int ret),\n+\trte_trace_point_emit_u16(port_id);\n+\trte_trace_point_emit_u64(features_val);\n+\trte_trace_point_emit_int(ret);\n+)\n+\n+RTE_TRACE_POINT(\n+\trte_eth_trace_ip_reassembly_capability_get,\n+\tRTE_TRACE_POINT_ARGS(uint16_t port_id,\n+\t\tconst struct rte_eth_ip_reassembly_params *capa, int ret),\n+\trte_trace_point_emit_u16(port_id);\n+\trte_trace_point_emit_u32(capa->timeout_ms);\n+\trte_trace_point_emit_u16(capa->max_frags);\n+\trte_trace_point_emit_u16(capa->flags);\n+\trte_trace_point_emit_int(ret);\n+)\n+\n+RTE_TRACE_POINT(\n+\trte_eth_trace_ip_reassembly_conf_get,\n+\tRTE_TRACE_POINT_ARGS(uint16_t port_id,\n+\t\tconst struct rte_eth_ip_reassembly_params *conf, int ret),\n+\trte_trace_point_emit_u16(port_id);\n+\trte_trace_point_emit_u32(conf->timeout_ms);\n+\trte_trace_point_emit_u16(conf->max_frags);\n+\trte_trace_point_emit_u16(conf->flags);\n+\trte_trace_point_emit_int(ret);\n+)\n+\n+RTE_TRACE_POINT(\n+\trte_eth_trace_ip_reassembly_conf_set,\n+\tRTE_TRACE_POINT_ARGS(uint16_t port_id,\n+\t\tconst struct rte_eth_ip_reassembly_params *conf, int ret),\n+\trte_trace_point_emit_u16(port_id);\n+\trte_trace_point_emit_u32(conf->timeout_ms);\n+\trte_trace_point_emit_u16(conf->max_frags);\n+\trte_trace_point_emit_u16(conf->flags);\n+\trte_trace_point_emit_int(ret);\n+)\n+\n+RTE_TRACE_POINT(\n+\trte_eth_trace_buffer_split_get_supported_hdr_ptypes,\n+\tRTE_TRACE_POINT_ARGS(uint16_t port_id, int supported_num,\n+\t\tuint32_t ptypes),\n+\trte_trace_point_emit_u16(port_id);\n+\trte_trace_point_emit_int(supported_num);\n+\trte_trace_point_emit_u32(ptypes);\n+)\n+\n+RTE_TRACE_POINT(\n+\trte_eth_trace_cman_info_get,\n+\tRTE_TRACE_POINT_ARGS(uint16_t port_id,\n+\t\tconst struct rte_eth_cman_info *info, int ret),\n+\trte_trace_point_emit_u16(port_id);\n+\trte_trace_point_emit_u64(info->modes_supported);\n+\trte_trace_point_emit_u64(info->objs_supported);\n+\trte_trace_point_emit_int(ret);\n+)\n+\n+RTE_TRACE_POINT(\n+\trte_eth_trace_cman_config_init,\n+\tRTE_TRACE_POINT_ARGS(uint16_t port_id,\n+\t\tconst struct rte_eth_cman_config *config, int ret),\n+\trte_trace_point_emit_u16(port_id);\n+\trte_trace_point_emit_int(config->obj);\n+\trte_trace_point_emit_int(config->mode);\n+\trte_trace_point_emit_int(ret);\n+)\n+\n+RTE_TRACE_POINT(\n+\trte_eth_trace_cman_config_set,\n+\tRTE_TRACE_POINT_ARGS(uint16_t port_id,\n+\t\tconst struct rte_eth_cman_config *config, int ret),\n+\trte_trace_point_emit_u16(port_id);\n+\trte_trace_point_emit_int(config->obj);\n+\trte_trace_point_emit_int(config->mode);\n+\trte_trace_point_emit_int(ret);\n+)\n+\n+RTE_TRACE_POINT(\n+\trte_eth_trace_cman_config_get,\n+\tRTE_TRACE_POINT_ARGS(uint16_t port_id,\n+\t\tconst struct rte_eth_cman_config *config, int ret),\n+\trte_trace_point_emit_u16(port_id);\n+\trte_trace_point_emit_int(config->obj);\n+\trte_trace_point_emit_int(config->mode);\n+\trte_trace_point_emit_int(ret);\n+)\n+\n /* Fast path trace points */\n \n /* Called in loop in examples/qos_sched and examples/distributor */\n@@ -628,6 +1423,86 @@ RTE_TRACE_POINT_FP(\n \trte_trace_point_emit_string(ret);\n )\n \n+/* Called in loop in examples/bond and examples/ethtool */\n+RTE_TRACE_POINT_FP(\n+\trte_eth_trace_macaddr_get,\n+\tRTE_TRACE_POINT_ARGS(uint16_t port_id,\n+\t\tconst struct rte_ether_addr *mac_addr),\n+\tuint8_t len = RTE_ETHER_ADDR_LEN;\n+\n+\trte_trace_point_emit_u16(port_id);\n+\trte_trace_point_emit_blob(mac_addr->addr_bytes, len);\n+)\n+\n+/* Called in loop in examples/ip_pipeline */\n+RTE_TRACE_POINT_FP(\n+\trte_ethdev_trace_get_mtu,\n+\tRTE_TRACE_POINT_ARGS(uint16_t port_id, uint16_t mtu),\n+\trte_trace_point_emit_u16(port_id);\n+\trte_trace_point_emit_u16(mtu);\n+)\n+\n+/* Called in loop in examples/l3fwd-power */\n+RTE_TRACE_POINT_FP(\n+\trte_ethdev_trace_rx_intr_enable,\n+\tRTE_TRACE_POINT_ARGS(uint16_t port_id, uint16_t queue_id, int ret),\n+\trte_trace_point_emit_u16(port_id);\n+\trte_trace_point_emit_u16(queue_id);\n+\trte_trace_point_emit_int(ret);\n+)\n+\n+/* Called in loop in examples/l3fwd-power */\n+RTE_TRACE_POINT_FP(\n+\trte_ethdev_trace_rx_intr_disable,\n+\tRTE_TRACE_POINT_ARGS(uint16_t port_id, uint16_t queue_id, int ret),\n+\trte_trace_point_emit_u16(port_id);\n+\trte_trace_point_emit_u16(queue_id);\n+\trte_trace_point_emit_int(ret);\n+)\n+\n+/* Called in loop in examples/ptpclient */\n+RTE_TRACE_POINT_FP(\n+\trte_eth_trace_timesync_read_rx_timestamp,\n+\tRTE_TRACE_POINT_ARGS(uint16_t port_id, const struct timespec *timestamp,\n+\t\tuint32_t flags, int ret),\n+\trte_trace_point_emit_u16(port_id);\n+\trte_trace_point_emit_size_t(timestamp->tv_sec);\n+\trte_trace_point_emit_long(timestamp->tv_nsec);\n+\trte_trace_point_emit_u32(flags);\n+\trte_trace_point_emit_int(ret);\n+)\n+\n+/* Called in loop in examples/ptpclient */\n+RTE_TRACE_POINT_FP(\n+\trte_eth_trace_timesync_read_tx_timestamp,\n+\tRTE_TRACE_POINT_ARGS(uint16_t port_id, const struct timespec *timestamp,\n+\t\tint ret),\n+\trte_trace_point_emit_u16(port_id);\n+\trte_trace_point_emit_size_t(timestamp->tv_sec);\n+\trte_trace_point_emit_long(timestamp->tv_nsec);\n+\trte_trace_point_emit_int(ret);\n+)\n+\n+/* Called in loop in examples/ptpclient */\n+RTE_TRACE_POINT_FP(\n+\trte_eth_trace_timesync_read_time,\n+\tRTE_TRACE_POINT_ARGS(uint16_t port_id, const struct timespec *time,\n+\t\tint ret),\n+\trte_trace_point_emit_u16(port_id);\n+\trte_trace_point_emit_size_t(time->tv_sec);\n+\trte_trace_point_emit_long(time->tv_nsec);\n+\trte_trace_point_emit_int(ret);\n+)\n+\n+/* Called in loop in examples/ptpclient */\n+RTE_TRACE_POINT_FP(\n+\trte_eth_trace_timesync_adjust_time,\n+\tRTE_TRACE_POINT_ARGS(uint16_t port_id, int64_t delta, int ret),\n+\trte_trace_point_emit_u16(port_id);\n+\trte_trace_point_emit_i64(delta);\n+\trte_trace_point_emit_int(ret);\n+)\n+\n #ifdef __cplusplus\n }\n #endif\ndiff --git a/lib/ethdev/ethdev_trace_points.c b/lib/ethdev/ethdev_trace_points.c\nindex 3e58c679c3..7a08104dc9 100644\n--- a/lib/ethdev/ethdev_trace_points.c\n+++ b/lib/ethdev/ethdev_trace_points.c\n@@ -222,3 +222,255 @@ RTE_TRACE_POINT_REGISTER(rte_ethdev_trace_set_rx_queue_stats_mapping,\n \n RTE_TRACE_POINT_REGISTER(rte_ethdev_trace_fw_version_get,\n \tlib.ethdev.fw_version_get)\n+\n+RTE_TRACE_POINT_REGISTER(rte_ethdev_trace_info_get,\n+\tlib.ethdev.info_get)\n+\n+RTE_TRACE_POINT_REGISTER(rte_ethdev_trace_conf_get,\n+\tlib.ethdev.conf_get)\n+\n+RTE_TRACE_POINT_REGISTER(rte_ethdev_trace_get_supported_ptypes,\n+\tlib.ethdev.get_supported_ptypes)\n+\n+RTE_TRACE_POINT_REGISTER(rte_ethdev_trace_set_ptypes,\n+\tlib.ethdev.set_ptypes)\n+\n+RTE_TRACE_POINT_REGISTER(rte_eth_trace_macaddrs_get,\n+\tlib.ethdev.macaddrs_get)\n+\n+RTE_TRACE_POINT_REGISTER(rte_eth_trace_macaddr_get,\n+\tlib.ethdev.macaddr_get)\n+\n+RTE_TRACE_POINT_REGISTER(rte_ethdev_trace_get_mtu,\n+\tlib.ethdev.get_mtu)\n+\n+RTE_TRACE_POINT_REGISTER(rte_ethdev_trace_set_mtu,\n+\tlib.ethdev.set_mtu)\n+\n+RTE_TRACE_POINT_REGISTER(rte_ethdev_trace_vlan_filter,\n+\tlib.ethdev.vlan_filter)\n+\n+RTE_TRACE_POINT_REGISTER(rte_ethdev_trace_set_vlan_strip_on_queue,\n+\tlib.ethdev.set_vlan_strip_on_queue)\n+\n+RTE_TRACE_POINT_REGISTER(rte_ethdev_trace_set_vlan_ether_type,\n+\tlib.ethdev.set_vlan_ether_type)\n+\n+RTE_TRACE_POINT_REGISTER(rte_ethdev_trace_set_vlan_offload,\n+\tlib.ethdev.set_vlan_offload)\n+\n+RTE_TRACE_POINT_REGISTER(rte_ethdev_trace_get_vlan_offload,\n+\tlib.ethdev.get_vlan_offload)\n+\n+RTE_TRACE_POINT_REGISTER(rte_ethdev_trace_set_vlan_pvid,\n+\tlib.ethdev.set_vlan_pvid)\n+\n+RTE_TRACE_POINT_REGISTER(rte_ethdev_trace_flow_ctrl_get,\n+\tlib.ethdev.flow_ctrl_get)\n+\n+RTE_TRACE_POINT_REGISTER(rte_ethdev_trace_flow_ctrl_set,\n+\tlib.ethdev.flow_ctrl_set)\n+\n+RTE_TRACE_POINT_REGISTER(rte_ethdev_trace_priority_flow_ctrl_set,\n+\tlib.ethdev.priority_flow_ctrl_set)\n+\n+RTE_TRACE_POINT_REGISTER(rte_ethdev_trace_priority_flow_ctrl_queue_info_get,\n+\tlib.ethdev.priority_flow_ctrl_queue_info_get)\n+\n+RTE_TRACE_POINT_REGISTER(rte_ethdev_trace_priority_flow_ctrl_queue_configure,\n+\tlib.ethdev.priority_flow_ctrl_queue_configure)\n+\n+RTE_TRACE_POINT_REGISTER(rte_ethdev_trace_rss_reta_update,\n+\tlib.ethdev.rss_reta_update)\n+\n+RTE_TRACE_POINT_REGISTER(rte_ethdev_trace_rss_reta_query,\n+\tlib.ethdev.rss_reta_query)\n+\n+RTE_TRACE_POINT_REGISTER(rte_ethdev_trace_rss_hash_update,\n+\tlib.ethdev.rss_hash_update)\n+\n+RTE_TRACE_POINT_REGISTER(rte_ethdev_trace_rss_hash_conf_get,\n+\tlib.ethdev.rss_hash_conf_get)\n+\n+RTE_TRACE_POINT_REGISTER(rte_ethdev_trace_udp_tunnel_port_add,\n+\tlib.ethdev.udp_tunnel_port_add)\n+\n+RTE_TRACE_POINT_REGISTER(rte_ethdev_trace_udp_tunnel_port_delete,\n+\tlib.ethdev.udp_tunnel_port_delete)\n+\n+RTE_TRACE_POINT_REGISTER(rte_eth_trace_led_on,\n+\tlib.ethdev.led_on)\n+\n+RTE_TRACE_POINT_REGISTER(rte_eth_trace_led_off,\n+\tlib.ethdev.led_off)\n+\n+RTE_TRACE_POINT_REGISTER(rte_eth_trace_fec_get_capability,\n+\tlib.ethdev.fec_get_capability)\n+\n+RTE_TRACE_POINT_REGISTER(rte_eth_trace_fec_get,\n+\tlib.ethdev.fec_get)\n+\n+RTE_TRACE_POINT_REGISTER(rte_eth_trace_fec_set,\n+\tlib.ethdev.fec_set)\n+\n+RTE_TRACE_POINT_REGISTER(rte_ethdev_trace_mac_addr_add,\n+\tlib.ethdev.mac_addr_add)\n+\n+RTE_TRACE_POINT_REGISTER(rte_ethdev_trace_mac_addr_remove,\n+\tlib.ethdev.mac_addr_remove)\n+\n+RTE_TRACE_POINT_REGISTER(rte_ethdev_trace_default_mac_addr_set,\n+\tlib.ethdev.default_mac_addr_set)\n+\n+RTE_TRACE_POINT_REGISTER(rte_ethdev_trace_uc_hash_table_set,\n+\tlib.ethdev.uc_hash_table_set)\n+\n+RTE_TRACE_POINT_REGISTER(rte_ethdev_trace_uc_all_hash_table_set,\n+\tlib.ethdev.uc_all_hash_table_set)\n+\n+RTE_TRACE_POINT_REGISTER(rte_eth_trace_set_queue_rate_limit,\n+\tlib.ethdev.set_queue_rate_limit)\n+\n+RTE_TRACE_POINT_REGISTER(rte_eth_trace_rx_avail_thresh_set,\n+\tlib.ethdev.rx_avail_thresh_set)\n+\n+RTE_TRACE_POINT_REGISTER(rte_eth_trace_rx_avail_thresh_query,\n+\tlib.ethdev.rx_avail_thresh_query)\n+\n+RTE_TRACE_POINT_REGISTER(rte_ethdev_trace_callback_register,\n+\tlib.ethdev.callback_register)\n+\n+RTE_TRACE_POINT_REGISTER(rte_ethdev_trace_callback_unregister,\n+\tlib.ethdev.callback_unregister)\n+\n+RTE_TRACE_POINT_REGISTER(rte_ethdev_trace_rx_intr_ctl,\n+\tlib.ethdev.rx_intr_ctl)\n+\n+RTE_TRACE_POINT_REGISTER(rte_ethdev_trace_rx_intr_ctl_q_get_fd,\n+\tlib.ethdev.rx_intr_ctl_q_get_fd)\n+\n+RTE_TRACE_POINT_REGISTER(rte_ethdev_trace_rx_intr_ctl_q,\n+\tlib.ethdev.rx_intr_ctl_q)\n+\n+RTE_TRACE_POINT_REGISTER(rte_ethdev_trace_rx_intr_enable,\n+\tlib.ethdev.rx_intr_enable)\n+\n+RTE_TRACE_POINT_REGISTER(rte_ethdev_trace_rx_intr_disable,\n+\tlib.ethdev.rx_intr_disable)\n+\n+RTE_TRACE_POINT_REGISTER(rte_eth_trace_add_rx_callback,\n+\tlib.ethdev.add_rx_callback)\n+\n+RTE_TRACE_POINT_REGISTER(rte_eth_trace_add_first_rx_callback,\n+\tlib.ethdev.add_first_rx_callback)\n+\n+RTE_TRACE_POINT_REGISTER(rte_eth_trace_add_tx_callback,\n+\tlib.ethdev.add_tx_callback)\n+\n+RTE_TRACE_POINT_REGISTER(rte_eth_trace_remove_rx_callback,\n+\tlib.ethdev.remove_rx_callback)\n+\n+RTE_TRACE_POINT_REGISTER(rte_eth_trace_remove_tx_callback,\n+\tlib.ethdev.remove_tx_callback)\n+\n+RTE_TRACE_POINT_REGISTER(rte_eth_trace_rx_queue_info_get,\n+\tlib.ethdev.rx_queue_info_get)\n+\n+RTE_TRACE_POINT_REGISTER(rte_eth_trace_tx_queue_info_get,\n+\tlib.ethdev.tx_queue_info_get)\n+\n+RTE_TRACE_POINT_REGISTER(rte_eth_trace_rx_burst_mode_get,\n+\tlib.ethdev.rx_burst_mode_get)\n+\n+RTE_TRACE_POINT_REGISTER(rte_eth_trace_tx_burst_mode_get,\n+\tlib.ethdev.tx_burst_mode_get)\n+\n+RTE_TRACE_POINT_REGISTER(rte_eth_trace_get_monitor_addr,\n+\tlib.ethdev.get_monitor_addr)\n+\n+RTE_TRACE_POINT_REGISTER(rte_ethdev_trace_set_mc_addr_list,\n+\tlib.ethdev.set_mc_addr_list)\n+\n+RTE_TRACE_POINT_REGISTER(rte_eth_trace_timesync_enable,\n+\tlib.ethdev.timesync_enable)\n+\n+RTE_TRACE_POINT_REGISTER(rte_eth_trace_timesync_disable,\n+\tlib.ethdev.timesync_disable)\n+\n+RTE_TRACE_POINT_REGISTER(rte_eth_trace_timesync_read_rx_timestamp,\n+\tlib.ethdev.timesync_read_rx_timestamp)\n+\n+RTE_TRACE_POINT_REGISTER(rte_eth_trace_timesync_read_tx_timestamp,\n+\tlib.ethdev.timesync_read_tx_timestamp)\n+\n+RTE_TRACE_POINT_REGISTER(rte_eth_trace_timesync_adjust_time,\n+\tlib.ethdev.timesync_adjust_time)\n+\n+RTE_TRACE_POINT_REGISTER(rte_eth_trace_timesync_read_time,\n+\tlib.ethdev.timesync_read_time)\n+\n+RTE_TRACE_POINT_REGISTER(rte_eth_trace_timesync_write_time,\n+\tlib.ethdev.timesync_write_time)\n+\n+RTE_TRACE_POINT_REGISTER(rte_eth_trace_read_clock,\n+\tlib.ethdev.read_clock)\n+\n+RTE_TRACE_POINT_REGISTER(rte_ethdev_trace_get_reg_info,\n+\tlib.ethdev.get_reg_info)\n+\n+RTE_TRACE_POINT_REGISTER(rte_ethdev_trace_get_eeprom_length,\n+\tlib.ethdev.get_eeprom_length)\n+\n+RTE_TRACE_POINT_REGISTER(rte_ethdev_trace_get_eeprom,\n+\tlib.ethdev.get_eeprom)\n+\n+RTE_TRACE_POINT_REGISTER(rte_ethdev_trace_set_eeprom,\n+\tlib.ethdev.set_eeprom)\n+\n+RTE_TRACE_POINT_REGISTER(rte_ethdev_trace_get_module_info,\n+\tlib.ethdev.get_module_info)\n+\n+RTE_TRACE_POINT_REGISTER(rte_ethdev_trace_get_module_eeprom,\n+\tlib.ethdev.get_module_eeprom)\n+\n+RTE_TRACE_POINT_REGISTER(rte_ethdev_trace_get_dcb_info,\n+\tlib.ethdev.get_dcb_info)\n+\n+RTE_TRACE_POINT_REGISTER(rte_ethdev_trace_adjust_nb_rx_tx_desc,\n+\tlib.ethdev.adjust_nb_rx_tx_desc)\n+\n+RTE_TRACE_POINT_REGISTER(rte_ethdev_trace_hairpin_capability_get,\n+\tlib.ethdev.hairpin_capability_get)\n+\n+RTE_TRACE_POINT_REGISTER(rte_ethdev_trace_pool_ops_supported,\n+\tlib.ethdev.pool_ops_supported)\n+\n+RTE_TRACE_POINT_REGISTER(rte_eth_trace_representor_info_get,\n+\tlib.ethdev.representor_info_get)\n+\n+RTE_TRACE_POINT_REGISTER(rte_eth_trace_rx_metadata_negotiate,\n+\tlib.ethdev.rx_metadata_negotiate)\n+\n+RTE_TRACE_POINT_REGISTER(rte_eth_trace_ip_reassembly_capability_get,\n+\tlib.ethdev.ip_reassembly_capability_get)\n+\n+RTE_TRACE_POINT_REGISTER(rte_eth_trace_ip_reassembly_conf_get,\n+\tlib.ethdev.ip_reassembly_conf_get)\n+\n+RTE_TRACE_POINT_REGISTER(rte_eth_trace_ip_reassembly_conf_set,\n+\tlib.ethdev.ip_reassembly_conf_set)\n+\n+RTE_TRACE_POINT_REGISTER(rte_eth_trace_buffer_split_get_supported_hdr_ptypes,\n+\tlib.ethdev.buffer_split_get_supported_hdr_ptypes)\n+\n+RTE_TRACE_POINT_REGISTER(rte_eth_trace_cman_info_get,\n+\tlib.ethdev.cman_info_get)\n+\n+RTE_TRACE_POINT_REGISTER(rte_eth_trace_cman_config_init,\n+\tlib.ethdev.cman_config_init)\n+\n+RTE_TRACE_POINT_REGISTER(rte_eth_trace_cman_config_set,\n+\tlib.ethdev.cman_config_set)\n+\n+RTE_TRACE_POINT_REGISTER(rte_eth_trace_cman_config_get,\n+\tlib.ethdev.cman_config_get)\ndiff --git a/lib/ethdev/rte_ethdev.c b/lib/ethdev/rte_ethdev.c\nindex 6aaae66b83..dc0a4eb12c 100644\n--- a/lib/ethdev/rte_ethdev.c\n+++ b/lib/ethdev/rte_ethdev.c\n@@ -3627,6 +3627,8 @@ rte_eth_dev_info_get(uint16_t port_id, struct rte_eth_dev_info *dev_info)\n \n \tdev_info->dev_flags = &dev->data->dev_flags;\n \n+\trte_ethdev_trace_info_get(port_id, dev_info);\n+\n \treturn 0;\n }\n \n@@ -3647,6 +3649,8 @@ rte_eth_dev_conf_get(uint16_t port_id, struct rte_eth_conf *dev_conf)\n \n \tmemcpy(dev_conf, &dev->data->dev_conf, sizeof(struct rte_eth_conf));\n \n+\trte_ethdev_trace_conf_get(port_id, dev_conf);\n+\n \treturn 0;\n }\n \n@@ -3677,8 +3681,12 @@ rte_eth_dev_get_supported_ptypes(uint16_t port_id, uint32_t ptype_mask,\n \n \tfor (i = 0, j = 0; all_ptypes[i] != RTE_PTYPE_UNKNOWN; ++i)\n \t\tif (all_ptypes[i] & ptype_mask) {\n-\t\t\tif (j < num)\n+\t\t\tif (j < num) {\n \t\t\t\tptypes[j] = all_ptypes[i];\n+\n+\t\t\t\trte_ethdev_trace_get_supported_ptypes(port_id,\n+\t\t\t\t\t\tj, num, ptypes[j]);\n+\t\t\t}\n \t\t\tj++;\n \t\t}\n \n@@ -3756,6 +3764,10 @@ rte_eth_dev_set_ptypes(uint16_t port_id, uint32_t ptype_mask,\n \t\tif (ptype_mask & all_ptypes[i]) {\n \t\t\tif (j < num - 1) {\n \t\t\t\tset_ptypes[j] = all_ptypes[i];\n+\n+\t\t\t\trte_ethdev_trace_set_ptypes(port_id, j, num,\n+\t\t\t\t\t\tset_ptypes[j]);\n+\n \t\t\t\tj++;\n \t\t\t\tcontinue;\n \t\t\t}\n@@ -3797,6 +3809,8 @@ rte_eth_macaddrs_get(uint16_t port_id, struct rte_ether_addr *ma,\n \tnum = RTE_MIN(dev_info.max_mac_addrs, num);\n \tmemcpy(ma, dev->data->mac_addrs, num * sizeof(ma[0]));\n \n+\trte_eth_trace_macaddrs_get(port_id, num);\n+\n \treturn num;\n }\n \n@@ -3817,6 +3831,8 @@ rte_eth_macaddr_get(uint16_t port_id, struct rte_ether_addr *mac_addr)\n \n \trte_ether_addr_copy(&dev->data->mac_addrs[0], mac_addr);\n \n+\trte_eth_trace_macaddr_get(port_id, mac_addr);\n+\n \treturn 0;\n }\n \n@@ -3835,6 +3851,9 @@ rte_eth_dev_get_mtu(uint16_t port_id, uint16_t *mtu)\n \t}\n \n \t*mtu = dev->data->mtu;\n+\n+\trte_ethdev_trace_get_mtu(port_id, *mtu);\n+\n \treturn 0;\n }\n \n@@ -3877,7 +3896,11 @@ rte_eth_dev_set_mtu(uint16_t port_id, uint16_t mtu)\n \tif (ret == 0)\n \t\tdev->data->mtu = mtu;\n \n-\treturn eth_err(port_id, ret);\n+\tret = eth_err(port_id, ret);\n+\n+\trte_ethdev_trace_set_mtu(port_id, mtu, ret);\n+\n+\treturn ret;\n }\n \n int\n@@ -3920,7 +3943,11 @@ rte_eth_dev_vlan_filter(uint16_t port_id, uint16_t vlan_id, int on)\n \t\t\tvfc->ids[vidx] &= ~RTE_BIT64(vbit);\n \t}\n \n-\treturn eth_err(port_id, ret);\n+\tret = eth_err(port_id, ret);\n+\n+\trte_ethdev_trace_vlan_filter(port_id, vlan_id, on, ret);\n+\n+\treturn ret;\n }\n \n int\n@@ -3941,6 +3968,8 @@ rte_eth_dev_set_vlan_strip_on_queue(uint16_t port_id, uint16_t rx_queue_id,\n \t\treturn -ENOTSUP;\n \t(*dev->dev_ops->vlan_strip_queue_set)(dev, rx_queue_id, on);\n \n+\trte_ethdev_trace_set_vlan_strip_on_queue(port_id, rx_queue_id, on);\n+\n \treturn 0;\n }\n \n@@ -3950,14 +3979,19 @@ rte_eth_dev_set_vlan_ether_type(uint16_t port_id,\n \t\t\t\tuint16_t tpid)\n {\n \tstruct rte_eth_dev *dev;\n+\tint ret;\n \n \tRTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);\n \tdev = &rte_eth_devices[port_id];\n \n \tif (*dev->dev_ops->vlan_tpid_set == NULL)\n \t\treturn -ENOTSUP;\n-\treturn eth_err(port_id, (*dev->dev_ops->vlan_tpid_set)(dev, vlan_type,\n-\t\t\t\t\t\t\t       tpid));\n+\tret = eth_err(port_id, (*dev->dev_ops->vlan_tpid_set)(dev, vlan_type,\n+\t\t\t\t\t\t\t      tpid));\n+\n+\trte_ethdev_trace_set_vlan_ether_type(port_id, vlan_type, tpid, ret);\n+\n+\treturn ret;\n }\n \n int\n@@ -4049,7 +4083,11 @@ rte_eth_dev_set_vlan_offload(uint16_t port_id, int offload_mask)\n \t\tdev->data->dev_conf.rxmode.offloads = orig_offloads;\n \t}\n \n-\treturn eth_err(port_id, ret);\n+\tret = eth_err(port_id, ret);\n+\n+\trte_ethdev_trace_set_vlan_offload(port_id, offload_mask, ret);\n+\n+\treturn ret;\n }\n \n int\n@@ -4075,6 +4113,8 @@ rte_eth_dev_get_vlan_offload(uint16_t port_id)\n \tif (*dev_offloads & RTE_ETH_RX_OFFLOAD_QINQ_STRIP)\n \t\tret |= RTE_ETH_QINQ_STRIP_OFFLOAD;\n \n+\trte_ethdev_trace_get_vlan_offload(port_id, ret);\n+\n \treturn ret;\n }\n \n@@ -4082,19 +4122,25 @@ int\n rte_eth_dev_set_vlan_pvid(uint16_t port_id, uint16_t pvid, int on)\n {\n \tstruct rte_eth_dev *dev;\n+\tint ret;\n \n \tRTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);\n \tdev = &rte_eth_devices[port_id];\n \n \tif (*dev->dev_ops->vlan_pvid_set == NULL)\n \t\treturn -ENOTSUP;\n-\treturn eth_err(port_id, (*dev->dev_ops->vlan_pvid_set)(dev, pvid, on));\n+\tret = eth_err(port_id, (*dev->dev_ops->vlan_pvid_set)(dev, pvid, on));\n+\n+\trte_ethdev_trace_set_vlan_pvid(port_id, pvid, on, ret);\n+\n+\treturn ret;\n }\n \n int\n rte_eth_dev_flow_ctrl_get(uint16_t port_id, struct rte_eth_fc_conf *fc_conf)\n {\n \tstruct rte_eth_dev *dev;\n+\tint ret;\n \n \tRTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);\n \tdev = &rte_eth_devices[port_id];\n@@ -4109,13 +4155,18 @@ rte_eth_dev_flow_ctrl_get(uint16_t port_id, struct rte_eth_fc_conf *fc_conf)\n \tif (*dev->dev_ops->flow_ctrl_get == NULL)\n \t\treturn -ENOTSUP;\n \tmemset(fc_conf, 0, sizeof(*fc_conf));\n-\treturn eth_err(port_id, (*dev->dev_ops->flow_ctrl_get)(dev, fc_conf));\n+\tret = eth_err(port_id, (*dev->dev_ops->flow_ctrl_get)(dev, fc_conf));\n+\n+\trte_ethdev_trace_flow_ctrl_get(port_id, fc_conf, ret);\n+\n+\treturn ret;\n }\n \n int\n rte_eth_dev_flow_ctrl_set(uint16_t port_id, struct rte_eth_fc_conf *fc_conf)\n {\n \tstruct rte_eth_dev *dev;\n+\tint ret;\n \n \tRTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);\n \tdev = &rte_eth_devices[port_id];\n@@ -4134,7 +4185,11 @@ rte_eth_dev_flow_ctrl_set(uint16_t port_id, struct rte_eth_fc_conf *fc_conf)\n \n \tif (*dev->dev_ops->flow_ctrl_set == NULL)\n \t\treturn -ENOTSUP;\n-\treturn eth_err(port_id, (*dev->dev_ops->flow_ctrl_set)(dev, fc_conf));\n+\tret = eth_err(port_id, (*dev->dev_ops->flow_ctrl_set)(dev, fc_conf));\n+\n+\trte_ethdev_trace_flow_ctrl_set(port_id, fc_conf, ret);\n+\n+\treturn ret;\n }\n \n int\n@@ -4142,6 +4197,7 @@ rte_eth_dev_priority_flow_ctrl_set(uint16_t port_id,\n \t\t\t\t   struct rte_eth_pfc_conf *pfc_conf)\n {\n \tstruct rte_eth_dev *dev;\n+\tint ret;\n \n \tRTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);\n \tdev = &rte_eth_devices[port_id];\n@@ -4159,10 +4215,14 @@ rte_eth_dev_priority_flow_ctrl_set(uint16_t port_id,\n \t}\n \n \t/* High water, low water validation are device specific */\n-\tif  (*dev->dev_ops->priority_flow_ctrl_set)\n-\t\treturn eth_err(port_id, (*dev->dev_ops->priority_flow_ctrl_set)\n-\t\t\t\t\t(dev, pfc_conf));\n-\treturn -ENOTSUP;\n+\tif  (*dev->dev_ops->priority_flow_ctrl_set == NULL)\n+\t\treturn -ENOTSUP;\n+\tret = eth_err(port_id, (*dev->dev_ops->priority_flow_ctrl_set)\n+\t\t\t       (dev, pfc_conf));\n+\n+\trte_ethdev_trace_priority_flow_ctrl_set(port_id, pfc_conf, ret);\n+\n+\treturn ret;\n }\n \n static int\n@@ -4220,6 +4280,7 @@ rte_eth_dev_priority_flow_ctrl_queue_info_get(uint16_t port_id,\n \t\tstruct rte_eth_pfc_queue_info *pfc_queue_info)\n {\n \tstruct rte_eth_dev *dev;\n+\tint ret;\n \n \tRTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);\n \tdev = &rte_eth_devices[port_id];\n@@ -4230,10 +4291,15 @@ rte_eth_dev_priority_flow_ctrl_queue_info_get(uint16_t port_id,\n \t\treturn -EINVAL;\n \t}\n \n-\tif (*dev->dev_ops->priority_flow_ctrl_queue_info_get)\n-\t\treturn eth_err(port_id, (*dev->dev_ops->priority_flow_ctrl_queue_info_get)\n+\tif (*dev->dev_ops->priority_flow_ctrl_queue_info_get == NULL)\n+\t\treturn -ENOTSUP;\n+\tret = eth_err(port_id, (*dev->dev_ops->priority_flow_ctrl_queue_info_get)\n \t\t\t(dev, pfc_queue_info));\n-\treturn -ENOTSUP;\n+\n+\trte_ethdev_trace_priority_flow_ctrl_queue_info_get(port_id,\n+\t\t\t\t\t\tpfc_queue_info, ret);\n+\n+\treturn ret;\n }\n \n int\n@@ -4301,11 +4367,15 @@ rte_eth_dev_priority_flow_ctrl_queue_configure(uint16_t port_id,\n \t\t\treturn ret;\n \t}\n \n-\tif (*dev->dev_ops->priority_flow_ctrl_queue_config)\n-\t\treturn eth_err(port_id,\n-\t\t\t       (*dev->dev_ops->priority_flow_ctrl_queue_config)(\n-\t\t\t\tdev, pfc_queue_conf));\n-\treturn -ENOTSUP;\n+\tif (*dev->dev_ops->priority_flow_ctrl_queue_config == NULL)\n+\t\treturn -ENOTSUP;\n+\tret = eth_err(port_id, (*dev->dev_ops->priority_flow_ctrl_queue_config)\n+\t\t\t(dev, pfc_queue_conf));\n+\n+\trte_ethdev_trace_priority_flow_ctrl_queue_configure(port_id,\n+\t\t\t\t\t\tpfc_queue_conf, ret);\n+\n+\treturn ret;\n }\n \n static int\n@@ -4396,8 +4466,12 @@ rte_eth_dev_rss_reta_update(uint16_t port_id,\n \n \tif (*dev->dev_ops->reta_update == NULL)\n \t\treturn -ENOTSUP;\n-\treturn eth_err(port_id, (*dev->dev_ops->reta_update)(dev, reta_conf,\n-\t\t\t\t\t\t\t     reta_size));\n+\tret = eth_err(port_id, (*dev->dev_ops->reta_update)(dev, reta_conf,\n+\t\t\t\t\t\t\t    reta_size));\n+\n+\trte_ethdev_trace_rss_reta_update(port_id, reta_conf, reta_size, ret);\n+\n+\treturn ret;\n }\n \n int\n@@ -4425,8 +4499,12 @@ rte_eth_dev_rss_reta_query(uint16_t port_id,\n \n \tif (*dev->dev_ops->reta_query == NULL)\n \t\treturn -ENOTSUP;\n-\treturn eth_err(port_id, (*dev->dev_ops->reta_query)(dev, reta_conf,\n-\t\t\t\t\t\t\t    reta_size));\n+\tret = eth_err(port_id, (*dev->dev_ops->reta_query)(dev, reta_conf,\n+\t\t\t\t\t\t\t   reta_size));\n+\n+\trte_ethdev_trace_rss_reta_query(port_id, reta_conf, reta_size, ret);\n+\n+\treturn ret;\n }\n \n int\n@@ -4470,8 +4548,12 @@ rte_eth_dev_rss_hash_update(uint16_t port_id,\n \n \tif (*dev->dev_ops->rss_hash_update == NULL)\n \t\treturn -ENOTSUP;\n-\treturn eth_err(port_id, (*dev->dev_ops->rss_hash_update)(dev,\n-\t\t\t\t\t\t\t\t rss_conf));\n+\tret = eth_err(port_id, (*dev->dev_ops->rss_hash_update)(dev,\n+\t\t\t\t\t\t\t\trss_conf));\n+\n+\trte_ethdev_trace_rss_hash_update(port_id, rss_conf, ret);\n+\n+\treturn ret;\n }\n \n int\n@@ -4479,6 +4561,7 @@ rte_eth_dev_rss_hash_conf_get(uint16_t port_id,\n \t\t\t      struct rte_eth_rss_conf *rss_conf)\n {\n \tstruct rte_eth_dev *dev;\n+\tint ret;\n \n \tRTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);\n \tdev = &rte_eth_devices[port_id];\n@@ -4492,8 +4575,12 @@ rte_eth_dev_rss_hash_conf_get(uint16_t port_id,\n \n \tif (*dev->dev_ops->rss_hash_conf_get == NULL)\n \t\treturn -ENOTSUP;\n-\treturn eth_err(port_id, (*dev->dev_ops->rss_hash_conf_get)(dev,\n-\t\t\t\t\t\t\t\t   rss_conf));\n+\tret = eth_err(port_id, (*dev->dev_ops->rss_hash_conf_get)(dev,\n+\t\t\t\t\t\t\t\t  rss_conf));\n+\n+\trte_ethdev_trace_rss_hash_conf_get(port_id, rss_conf, ret);\n+\n+\treturn ret;\n }\n \n int\n@@ -4501,6 +4588,7 @@ rte_eth_dev_udp_tunnel_port_add(uint16_t port_id,\n \t\t\t\tstruct rte_eth_udp_tunnel *udp_tunnel)\n {\n \tstruct rte_eth_dev *dev;\n+\tint ret;\n \n \tRTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);\n \tdev = &rte_eth_devices[port_id];\n@@ -4519,8 +4607,12 @@ rte_eth_dev_udp_tunnel_port_add(uint16_t port_id,\n \n \tif (*dev->dev_ops->udp_tunnel_port_add == NULL)\n \t\treturn -ENOTSUP;\n-\treturn eth_err(port_id, (*dev->dev_ops->udp_tunnel_port_add)(dev,\n+\tret = eth_err(port_id, (*dev->dev_ops->udp_tunnel_port_add)(dev,\n \t\t\t\t\t\t\t\tudp_tunnel));\n+\n+\trte_ethdev_trace_udp_tunnel_port_add(port_id, udp_tunnel, ret);\n+\n+\treturn ret;\n }\n \n int\n@@ -4528,6 +4620,7 @@ rte_eth_dev_udp_tunnel_port_delete(uint16_t port_id,\n \t\t\t\t   struct rte_eth_udp_tunnel *udp_tunnel)\n {\n \tstruct rte_eth_dev *dev;\n+\tint ret;\n \n \tRTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);\n \tdev = &rte_eth_devices[port_id];\n@@ -4546,34 +4639,48 @@ rte_eth_dev_udp_tunnel_port_delete(uint16_t port_id,\n \n \tif (*dev->dev_ops->udp_tunnel_port_del == NULL)\n \t\treturn -ENOTSUP;\n-\treturn eth_err(port_id, (*dev->dev_ops->udp_tunnel_port_del)(dev,\n+\tret = eth_err(port_id, (*dev->dev_ops->udp_tunnel_port_del)(dev,\n \t\t\t\t\t\t\t\tudp_tunnel));\n+\n+\trte_ethdev_trace_udp_tunnel_port_delete(port_id, udp_tunnel, ret);\n+\n+\treturn ret;\n }\n \n int\n rte_eth_led_on(uint16_t port_id)\n {\n \tstruct rte_eth_dev *dev;\n+\tint ret;\n \n \tRTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);\n \tdev = &rte_eth_devices[port_id];\n \n \tif (*dev->dev_ops->dev_led_on == NULL)\n \t\treturn -ENOTSUP;\n-\treturn eth_err(port_id, (*dev->dev_ops->dev_led_on)(dev));\n+\tret = eth_err(port_id, (*dev->dev_ops->dev_led_on)(dev));\n+\n+\trte_eth_trace_led_on(port_id, ret);\n+\n+\treturn ret;\n }\n \n int\n rte_eth_led_off(uint16_t port_id)\n {\n \tstruct rte_eth_dev *dev;\n+\tint ret;\n \n \tRTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);\n \tdev = &rte_eth_devices[port_id];\n \n \tif (*dev->dev_ops->dev_led_off == NULL)\n \t\treturn -ENOTSUP;\n-\treturn eth_err(port_id, (*dev->dev_ops->dev_led_off)(dev));\n+\tret = eth_err(port_id, (*dev->dev_ops->dev_led_off)(dev));\n+\n+\trte_eth_trace_led_off(port_id, ret);\n+\n+\treturn ret;\n }\n \n int\n@@ -4598,6 +4705,8 @@ rte_eth_fec_get_capability(uint16_t port_id,\n \t\treturn -ENOTSUP;\n \tret = (*dev->dev_ops->fec_get_capability)(dev, speed_fec_capa, num);\n \n+\trte_eth_trace_fec_get_capability(port_id, speed_fec_capa, num, ret);\n+\n \treturn ret;\n }\n \n@@ -4605,6 +4714,7 @@ int\n rte_eth_fec_get(uint16_t port_id, uint32_t *fec_capa)\n {\n \tstruct rte_eth_dev *dev;\n+\tint ret;\n \n \tRTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);\n \tdev = &rte_eth_devices[port_id];\n@@ -4618,20 +4728,29 @@ rte_eth_fec_get(uint16_t port_id, uint32_t *fec_capa)\n \n \tif (*dev->dev_ops->fec_get == NULL)\n \t\treturn -ENOTSUP;\n-\treturn eth_err(port_id, (*dev->dev_ops->fec_get)(dev, fec_capa));\n+\tret = eth_err(port_id, (*dev->dev_ops->fec_get)(dev, fec_capa));\n+\n+\trte_eth_trace_fec_get(port_id, fec_capa, ret);\n+\n+\treturn ret;\n }\n \n int\n rte_eth_fec_set(uint16_t port_id, uint32_t fec_capa)\n {\n \tstruct rte_eth_dev *dev;\n+\tint ret;\n \n \tRTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);\n \tdev = &rte_eth_devices[port_id];\n \n \tif (*dev->dev_ops->fec_set == NULL)\n \t\treturn -ENOTSUP;\n-\treturn eth_err(port_id, (*dev->dev_ops->fec_set)(dev, fec_capa));\n+\tret = eth_err(port_id, (*dev->dev_ops->fec_set)(dev, fec_capa));\n+\n+\trte_eth_trace_fec_set(port_id, fec_capa, ret);\n+\n+\treturn ret;\n }\n \n /*\n@@ -4719,7 +4838,11 @@ rte_eth_dev_mac_addr_add(uint16_t port_id, struct rte_ether_addr *addr,\n \t\tdev->data->mac_pool_sel[index] |= RTE_BIT64(pool);\n \t}\n \n-\treturn eth_err(port_id, ret);\n+\tret = eth_err(port_id, ret);\n+\n+\trte_ethdev_trace_mac_addr_add(port_id, addr, pool, ret);\n+\n+\treturn ret;\n }\n \n int\n@@ -4759,6 +4882,8 @@ rte_eth_dev_mac_addr_remove(uint16_t port_id, struct rte_ether_addr *addr)\n \t/* reset pool bitmap */\n \tdev->data->mac_pool_sel[index] = 0;\n \n+\trte_ethdev_trace_mac_addr_remove(port_id, addr);\n+\n \treturn 0;\n }\n \n@@ -4791,6 +4916,8 @@ rte_eth_dev_default_mac_addr_set(uint16_t port_id, struct rte_ether_addr *addr)\n \t/* Update default address in NIC data structure */\n \trte_ether_addr_copy(addr, &dev->data->mac_addrs[0]);\n \n+\trte_ethdev_trace_default_mac_addr_set(port_id, addr);\n+\n \treturn 0;\n }\n \n@@ -4881,21 +5008,29 @@ rte_eth_dev_uc_hash_table_set(uint16_t port_id, struct rte_ether_addr *addr,\n \t\t\t\t\t&dev->data->hash_mac_addrs[index]);\n \t}\n \n-\treturn eth_err(port_id, ret);\n+\tret = eth_err(port_id, ret);\n+\n+\trte_ethdev_trace_uc_hash_table_set(port_id, on, ret);\n+\n+\treturn ret;\n }\n \n int\n rte_eth_dev_uc_all_hash_table_set(uint16_t port_id, uint8_t on)\n {\n \tstruct rte_eth_dev *dev;\n+\tint ret;\n \n \tRTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);\n \tdev = &rte_eth_devices[port_id];\n \n \tif (*dev->dev_ops->uc_all_hash_table_set == NULL)\n \t\treturn -ENOTSUP;\n-\treturn eth_err(port_id, (*dev->dev_ops->uc_all_hash_table_set)(dev,\n-\t\t\t\t\t\t\t\t       on));\n+\tret = eth_err(port_id, (*dev->dev_ops->uc_all_hash_table_set)(dev, on));\n+\n+\trte_ethdev_trace_uc_all_hash_table_set(port_id, on, ret);\n+\n+\treturn ret;\n }\n \n int rte_eth_set_queue_rate_limit(uint16_t port_id, uint16_t queue_idx,\n@@ -4931,14 +5066,19 @@ int rte_eth_set_queue_rate_limit(uint16_t port_id, uint16_t queue_idx,\n \n \tif (*dev->dev_ops->set_queue_rate_limit == NULL)\n \t\treturn -ENOTSUP;\n-\treturn eth_err(port_id, (*dev->dev_ops->set_queue_rate_limit)(dev,\n+\tret = eth_err(port_id, (*dev->dev_ops->set_queue_rate_limit)(dev,\n \t\t\t\t\t\t\tqueue_idx, tx_rate));\n+\n+\trte_eth_trace_set_queue_rate_limit(port_id, queue_idx, tx_rate, ret);\n+\n+\treturn ret;\n }\n \n int rte_eth_rx_avail_thresh_set(uint16_t port_id, uint16_t queue_id,\n \t\t\t       uint8_t avail_thresh)\n {\n \tstruct rte_eth_dev *dev;\n+\tint ret;\n \n \tRTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);\n \tdev = &rte_eth_devices[port_id];\n@@ -4958,14 +5098,19 @@ int rte_eth_rx_avail_thresh_set(uint16_t port_id, uint16_t queue_id,\n \t}\n \tif (*dev->dev_ops->rx_queue_avail_thresh_set == NULL)\n \t\treturn -ENOTSUP;\n-\treturn eth_err(port_id, (*dev->dev_ops->rx_queue_avail_thresh_set)(dev,\n+\tret = eth_err(port_id, (*dev->dev_ops->rx_queue_avail_thresh_set)(dev,\n \t\t\t\t\t\t\t     queue_id, avail_thresh));\n+\n+\trte_eth_trace_rx_avail_thresh_set(port_id, queue_id, avail_thresh, ret);\n+\n+\treturn ret;\n }\n \n int rte_eth_rx_avail_thresh_query(uint16_t port_id, uint16_t *queue_id,\n \t\t\t\t uint8_t *avail_thresh)\n {\n \tstruct rte_eth_dev *dev;\n+\tint ret;\n \n \tRTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);\n \tdev = &rte_eth_devices[port_id];\n@@ -4977,8 +5122,12 @@ int rte_eth_rx_avail_thresh_query(uint16_t port_id, uint16_t *queue_id,\n \n \tif (*dev->dev_ops->rx_queue_avail_thresh_query == NULL)\n \t\treturn -ENOTSUP;\n-\treturn eth_err(port_id, (*dev->dev_ops->rx_queue_avail_thresh_query)(dev,\n+\tret = eth_err(port_id, (*dev->dev_ops->rx_queue_avail_thresh_query)(dev,\n \t\t\t\t\t\t\t     queue_id, avail_thresh));\n+\n+\trte_eth_trace_rx_avail_thresh_query(port_id, *queue_id, ret);\n+\n+\treturn ret;\n }\n \n RTE_INIT(eth_dev_init_fp_ops)\n@@ -5060,6 +5209,9 @@ rte_eth_dev_callback_register(uint16_t port_id,\n \t} while (++next_port <= last_port);\n \n \trte_spinlock_unlock(&eth_dev_cb_lock);\n+\n+\trte_ethdev_trace_callback_register(port_id, event, cb_fn, cb_arg);\n+\n \treturn 0;\n }\n \n@@ -5121,6 +5273,10 @@ rte_eth_dev_callback_unregister(uint16_t port_id,\n \t} while (++next_port <= last_port);\n \n \trte_spinlock_unlock(&eth_dev_cb_lock);\n+\n+\trte_ethdev_trace_callback_unregister(port_id, event, cb_fn, cb_arg,\n+\t\t\t\t\t     ret);\n+\n \treturn ret;\n }\n \n@@ -5150,6 +5306,9 @@ rte_eth_dev_rx_intr_ctl(uint16_t port_id, int epfd, int op, void *data)\n \tfor (qid = 0; qid < dev->data->nb_rx_queues; qid++) {\n \t\tvec = rte_intr_vec_list_index_get(intr_handle, qid);\n \t\trc = rte_intr_rx_ctl(intr_handle, epfd, op, vec, data);\n+\n+\t\trte_ethdev_trace_rx_intr_ctl(port_id, qid, epfd, op, data, rc);\n+\n \t\tif (rc && rc != -EEXIST) {\n \t\t\tRTE_ETHDEV_LOG(ERR,\n \t\t\t\t\"p %u q %u Rx ctl error op %d epfd %d vec %u\\n\",\n@@ -5193,6 +5352,8 @@ rte_eth_dev_rx_intr_ctl_q_get_fd(uint16_t port_id, uint16_t queue_id)\n \t\t(vec - RTE_INTR_VEC_RXTX_OFFSET) : vec;\n \tfd = rte_intr_efds_index_get(intr_handle, efd_idx);\n \n+\trte_ethdev_trace_rx_intr_ctl_q_get_fd(port_id, queue_id, fd);\n+\n \treturn fd;\n }\n \n@@ -5226,6 +5387,9 @@ rte_eth_dev_rx_intr_ctl_q(uint16_t port_id, uint16_t queue_id,\n \n \tvec = rte_intr_vec_list_index_get(intr_handle, queue_id);\n \trc = rte_intr_rx_ctl(intr_handle, epfd, op, vec, data);\n+\n+\trte_ethdev_trace_rx_intr_ctl_q(port_id, queue_id, epfd, op, data, rc);\n+\n \tif (rc && rc != -EEXIST) {\n \t\tRTE_ETHDEV_LOG(ERR,\n \t\t\t\"p %u q %u Rx ctl error op %d epfd %d vec %u\\n\",\n@@ -5252,7 +5416,11 @@ rte_eth_dev_rx_intr_enable(uint16_t port_id,\n \n \tif (*dev->dev_ops->rx_queue_intr_enable == NULL)\n \t\treturn -ENOTSUP;\n-\treturn eth_err(port_id, (*dev->dev_ops->rx_queue_intr_enable)(dev, queue_id));\n+\tret = eth_err(port_id, (*dev->dev_ops->rx_queue_intr_enable)(dev, queue_id));\n+\n+\trte_ethdev_trace_rx_intr_enable(port_id, queue_id, ret);\n+\n+\treturn ret;\n }\n \n int\n@@ -5271,7 +5439,11 @@ rte_eth_dev_rx_intr_disable(uint16_t port_id,\n \n \tif (*dev->dev_ops->rx_queue_intr_disable == NULL)\n \t\treturn -ENOTSUP;\n-\treturn eth_err(port_id, (*dev->dev_ops->rx_queue_intr_disable)(dev, queue_id));\n+\tret = eth_err(port_id, (*dev->dev_ops->rx_queue_intr_disable)(dev, queue_id));\n+\n+\trte_ethdev_trace_rx_intr_disable(port_id, queue_id, ret);\n+\n+\treturn ret;\n }\n \n \n@@ -5329,6 +5501,8 @@ rte_eth_add_rx_callback(uint16_t port_id, uint16_t queue_id,\n \t}\n \trte_spinlock_unlock(&eth_dev_rx_cb_lock);\n \n+\trte_eth_trace_add_rx_callback(port_id, queue_id, fn, user_param, cb);\n+\n \treturn cb;\n }\n \n@@ -5368,6 +5542,9 @@ rte_eth_add_first_rx_callback(uint16_t port_id, uint16_t queue_id,\n \t\tcb, __ATOMIC_RELEASE);\n \trte_spinlock_unlock(&eth_dev_rx_cb_lock);\n \n+\trte_eth_trace_add_first_rx_callback(port_id, queue_id, fn, user_param,\n+\t\t\t\t\t    cb);\n+\n \treturn cb;\n }\n \n@@ -5427,6 +5604,8 @@ rte_eth_add_tx_callback(uint16_t port_id, uint16_t queue_id,\n \t}\n \trte_spinlock_unlock(&eth_dev_tx_cb_lock);\n \n+\trte_eth_trace_add_tx_callback(port_id, queue_id, fn, user_param, cb);\n+\n \treturn cb;\n }\n \n@@ -5461,6 +5640,8 @@ rte_eth_remove_rx_callback(uint16_t port_id, uint16_t queue_id,\n \t}\n \trte_spinlock_unlock(&eth_dev_rx_cb_lock);\n \n+\trte_eth_trace_remove_rx_callback(port_id, queue_id, user_cb, ret);\n+\n \treturn ret;\n }\n \n@@ -5495,6 +5676,8 @@ rte_eth_remove_tx_callback(uint16_t port_id, uint16_t queue_id,\n \t}\n \trte_spinlock_unlock(&eth_dev_tx_cb_lock);\n \n+\trte_eth_trace_remove_tx_callback(port_id, queue_id, user_cb, ret);\n+\n \treturn ret;\n }\n \n@@ -5541,6 +5724,8 @@ rte_eth_rx_queue_info_get(uint16_t port_id, uint16_t queue_id,\n \tdev->dev_ops->rxq_info_get(dev, queue_id, qinfo);\n \tqinfo->queue_state = dev->data->rx_queue_state[queue_id];\n \n+\trte_eth_trace_rx_queue_info_get(port_id, queue_id, qinfo);\n+\n \treturn 0;\n }\n \n@@ -5587,6 +5772,8 @@ rte_eth_tx_queue_info_get(uint16_t port_id, uint16_t queue_id,\n \tdev->dev_ops->txq_info_get(dev, queue_id, qinfo);\n \tqinfo->queue_state = dev->data->tx_queue_state[queue_id];\n \n+\trte_eth_trace_tx_queue_info_get(port_id, queue_id, qinfo);\n+\n \treturn 0;\n }\n \n@@ -5595,6 +5782,7 @@ rte_eth_rx_burst_mode_get(uint16_t port_id, uint16_t queue_id,\n \t\t\t  struct rte_eth_burst_mode *mode)\n {\n \tstruct rte_eth_dev *dev;\n+\tint ret;\n \n \tRTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);\n \tdev = &rte_eth_devices[port_id];\n@@ -5614,8 +5802,12 @@ rte_eth_rx_burst_mode_get(uint16_t port_id, uint16_t queue_id,\n \tif (*dev->dev_ops->rx_burst_mode_get == NULL)\n \t\treturn -ENOTSUP;\n \tmemset(mode, 0, sizeof(*mode));\n-\treturn eth_err(port_id,\n-\t\t       dev->dev_ops->rx_burst_mode_get(dev, queue_id, mode));\n+\tret = eth_err(port_id,\n+\t\t      dev->dev_ops->rx_burst_mode_get(dev, queue_id, mode));\n+\n+\trte_eth_trace_rx_burst_mode_get(port_id, queue_id, mode, ret);\n+\n+\treturn ret;\n }\n \n int\n@@ -5623,6 +5815,7 @@ rte_eth_tx_burst_mode_get(uint16_t port_id, uint16_t queue_id,\n \t\t\t  struct rte_eth_burst_mode *mode)\n {\n \tstruct rte_eth_dev *dev;\n+\tint ret;\n \n \tRTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);\n \tdev = &rte_eth_devices[port_id];\n@@ -5642,8 +5835,12 @@ rte_eth_tx_burst_mode_get(uint16_t port_id, uint16_t queue_id,\n \tif (*dev->dev_ops->tx_burst_mode_get == NULL)\n \t\treturn -ENOTSUP;\n \tmemset(mode, 0, sizeof(*mode));\n-\treturn eth_err(port_id,\n-\t\t       dev->dev_ops->tx_burst_mode_get(dev, queue_id, mode));\n+\tret = eth_err(port_id,\n+\t\t      dev->dev_ops->tx_burst_mode_get(dev, queue_id, mode));\n+\n+\trte_eth_trace_tx_burst_mode_get(port_id, queue_id, mode, ret);\n+\n+\treturn ret;\n }\n \n int\n@@ -5651,6 +5848,7 @@ rte_eth_get_monitor_addr(uint16_t port_id, uint16_t queue_id,\n \t\tstruct rte_power_monitor_cond *pmc)\n {\n \tstruct rte_eth_dev *dev;\n+\tint ret;\n \n \tRTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);\n \tdev = &rte_eth_devices[port_id];\n@@ -5669,8 +5867,12 @@ rte_eth_get_monitor_addr(uint16_t port_id, uint16_t queue_id,\n \n \tif (*dev->dev_ops->get_monitor_addr == NULL)\n \t\treturn -ENOTSUP;\n-\treturn eth_err(port_id,\n+\tret = eth_err(port_id,\n \t\tdev->dev_ops->get_monitor_addr(dev->data->rx_queues[queue_id], pmc));\n+\n+\trte_eth_trace_get_monitor_addr(port_id, queue_id, pmc, ret);\n+\n+\treturn ret;\n }\n \n int\n@@ -5679,40 +5881,56 @@ rte_eth_dev_set_mc_addr_list(uint16_t port_id,\n \t\t\t     uint32_t nb_mc_addr)\n {\n \tstruct rte_eth_dev *dev;\n+\tint ret;\n \n \tRTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);\n \tdev = &rte_eth_devices[port_id];\n \n \tif (*dev->dev_ops->set_mc_addr_list == NULL)\n \t\treturn -ENOTSUP;\n-\treturn eth_err(port_id, dev->dev_ops->set_mc_addr_list(dev,\n+\tret = eth_err(port_id, dev->dev_ops->set_mc_addr_list(dev,\n \t\t\t\t\t\tmc_addr_set, nb_mc_addr));\n+\n+\trte_ethdev_trace_set_mc_addr_list(port_id, mc_addr_set, nb_mc_addr,\n+\t\t\t\t\t  ret);\n+\n+\treturn ret;\n }\n \n int\n rte_eth_timesync_enable(uint16_t port_id)\n {\n \tstruct rte_eth_dev *dev;\n+\tint ret;\n \n \tRTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);\n \tdev = &rte_eth_devices[port_id];\n \n \tif (*dev->dev_ops->timesync_enable == NULL)\n \t\treturn -ENOTSUP;\n-\treturn eth_err(port_id, (*dev->dev_ops->timesync_enable)(dev));\n+\tret = eth_err(port_id, (*dev->dev_ops->timesync_enable)(dev));\n+\n+\trte_eth_trace_timesync_enable(port_id, ret);\n+\n+\treturn ret;\n }\n \n int\n rte_eth_timesync_disable(uint16_t port_id)\n {\n \tstruct rte_eth_dev *dev;\n+\tint ret;\n \n \tRTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);\n \tdev = &rte_eth_devices[port_id];\n \n \tif (*dev->dev_ops->timesync_disable == NULL)\n \t\treturn -ENOTSUP;\n-\treturn eth_err(port_id, (*dev->dev_ops->timesync_disable)(dev));\n+\tret = eth_err(port_id, (*dev->dev_ops->timesync_disable)(dev));\n+\n+\trte_eth_trace_timesync_disable(port_id, ret);\n+\n+\treturn ret;\n }\n \n int\n@@ -5720,6 +5938,7 @@ rte_eth_timesync_read_rx_timestamp(uint16_t port_id, struct timespec *timestamp,\n \t\t\t\t   uint32_t flags)\n {\n \tstruct rte_eth_dev *dev;\n+\tint ret;\n \n \tRTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);\n \tdev = &rte_eth_devices[port_id];\n@@ -5733,8 +5952,14 @@ rte_eth_timesync_read_rx_timestamp(uint16_t port_id, struct timespec *timestamp,\n \n \tif (*dev->dev_ops->timesync_read_rx_timestamp == NULL)\n \t\treturn -ENOTSUP;\n-\treturn eth_err(port_id, (*dev->dev_ops->timesync_read_rx_timestamp)\n-\t\t\t\t(dev, timestamp, flags));\n+\n+\tret = eth_err(port_id, (*dev->dev_ops->timesync_read_rx_timestamp)\n+\t\t\t       (dev, timestamp, flags));\n+\n+\trte_eth_trace_timesync_read_rx_timestamp(port_id, timestamp, flags,\n+\t\t\t\t\t\t ret);\n+\n+\treturn ret;\n }\n \n int\n@@ -5742,6 +5967,7 @@ rte_eth_timesync_read_tx_timestamp(uint16_t port_id,\n \t\t\t\t   struct timespec *timestamp)\n {\n \tstruct rte_eth_dev *dev;\n+\tint ret;\n \n \tRTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);\n \tdev = &rte_eth_devices[port_id];\n@@ -5755,27 +5981,39 @@ rte_eth_timesync_read_tx_timestamp(uint16_t port_id,\n \n \tif (*dev->dev_ops->timesync_read_tx_timestamp == NULL)\n \t\treturn -ENOTSUP;\n-\treturn eth_err(port_id, (*dev->dev_ops->timesync_read_tx_timestamp)\n-\t\t\t\t(dev, timestamp));\n+\n+\tret = eth_err(port_id, (*dev->dev_ops->timesync_read_tx_timestamp)\n+\t\t\t       (dev, timestamp));\n+\n+\trte_eth_trace_timesync_read_tx_timestamp(port_id, timestamp, ret);\n+\n+\treturn ret;\n+\n }\n \n int\n rte_eth_timesync_adjust_time(uint16_t port_id, int64_t delta)\n {\n \tstruct rte_eth_dev *dev;\n+\tint ret;\n \n \tRTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);\n \tdev = &rte_eth_devices[port_id];\n \n \tif (*dev->dev_ops->timesync_adjust_time == NULL)\n \t\treturn -ENOTSUP;\n-\treturn eth_err(port_id, (*dev->dev_ops->timesync_adjust_time)(dev, delta));\n+\tret = eth_err(port_id, (*dev->dev_ops->timesync_adjust_time)(dev, delta));\n+\n+\trte_eth_trace_timesync_adjust_time(port_id, delta, ret);\n+\n+\treturn ret;\n }\n \n int\n rte_eth_timesync_read_time(uint16_t port_id, struct timespec *timestamp)\n {\n \tstruct rte_eth_dev *dev;\n+\tint ret;\n \n \tRTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);\n \tdev = &rte_eth_devices[port_id];\n@@ -5789,14 +6027,19 @@ rte_eth_timesync_read_time(uint16_t port_id, struct timespec *timestamp)\n \n \tif (*dev->dev_ops->timesync_read_time == NULL)\n \t\treturn -ENOTSUP;\n-\treturn eth_err(port_id, (*dev->dev_ops->timesync_read_time)(dev,\n+\tret = eth_err(port_id, (*dev->dev_ops->timesync_read_time)(dev,\n \t\t\t\t\t\t\t\ttimestamp));\n+\n+\trte_eth_trace_timesync_read_time(port_id, timestamp, ret);\n+\n+\treturn ret;\n }\n \n int\n rte_eth_timesync_write_time(uint16_t port_id, const struct timespec *timestamp)\n {\n \tstruct rte_eth_dev *dev;\n+\tint ret;\n \n \tRTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);\n \tdev = &rte_eth_devices[port_id];\n@@ -5810,14 +6053,19 @@ rte_eth_timesync_write_time(uint16_t port_id, const struct timespec *timestamp)\n \n \tif (*dev->dev_ops->timesync_write_time == NULL)\n \t\treturn -ENOTSUP;\n-\treturn eth_err(port_id, (*dev->dev_ops->timesync_write_time)(dev,\n+\tret = eth_err(port_id, (*dev->dev_ops->timesync_write_time)(dev,\n \t\t\t\t\t\t\t\ttimestamp));\n+\n+\trte_eth_trace_timesync_write_time(port_id, timestamp, ret);\n+\n+\treturn ret;\n }\n \n int\n rte_eth_read_clock(uint16_t port_id, uint64_t *clock)\n {\n \tstruct rte_eth_dev *dev;\n+\tint ret;\n \n \tRTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);\n \tdev = &rte_eth_devices[port_id];\n@@ -5830,13 +6078,18 @@ rte_eth_read_clock(uint16_t port_id, uint64_t *clock)\n \n \tif (*dev->dev_ops->read_clock == NULL)\n \t\treturn -ENOTSUP;\n-\treturn eth_err(port_id, (*dev->dev_ops->read_clock)(dev, clock));\n+\tret = eth_err(port_id, (*dev->dev_ops->read_clock)(dev, clock));\n+\n+\trte_eth_trace_read_clock(port_id, clock, ret);\n+\n+\treturn ret;\n }\n \n int\n rte_eth_dev_get_reg_info(uint16_t port_id, struct rte_dev_reg_info *info)\n {\n \tstruct rte_eth_dev *dev;\n+\tint ret;\n \n \tRTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);\n \tdev = &rte_eth_devices[port_id];\n@@ -5850,26 +6103,36 @@ rte_eth_dev_get_reg_info(uint16_t port_id, struct rte_dev_reg_info *info)\n \n \tif (*dev->dev_ops->get_reg == NULL)\n \t\treturn -ENOTSUP;\n-\treturn eth_err(port_id, (*dev->dev_ops->get_reg)(dev, info));\n+\tret = eth_err(port_id, (*dev->dev_ops->get_reg)(dev, info));\n+\n+\trte_ethdev_trace_get_reg_info(port_id, info, ret);\n+\n+\treturn ret;\n }\n \n int\n rte_eth_dev_get_eeprom_length(uint16_t port_id)\n {\n \tstruct rte_eth_dev *dev;\n+\tint ret;\n \n \tRTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);\n \tdev = &rte_eth_devices[port_id];\n \n \tif (*dev->dev_ops->get_eeprom_length == NULL)\n \t\treturn -ENOTSUP;\n-\treturn eth_err(port_id, (*dev->dev_ops->get_eeprom_length)(dev));\n+\tret = eth_err(port_id, (*dev->dev_ops->get_eeprom_length)(dev));\n+\n+\trte_ethdev_trace_get_eeprom_length(port_id, ret);\n+\n+\treturn ret;\n }\n \n int\n rte_eth_dev_get_eeprom(uint16_t port_id, struct rte_dev_eeprom_info *info)\n {\n \tstruct rte_eth_dev *dev;\n+\tint ret;\n \n \tRTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);\n \tdev = &rte_eth_devices[port_id];\n@@ -5883,13 +6146,18 @@ rte_eth_dev_get_eeprom(uint16_t port_id, struct rte_dev_eeprom_info *info)\n \n \tif (*dev->dev_ops->get_eeprom == NULL)\n \t\treturn -ENOTSUP;\n-\treturn eth_err(port_id, (*dev->dev_ops->get_eeprom)(dev, info));\n+\tret = eth_err(port_id, (*dev->dev_ops->get_eeprom)(dev, info));\n+\n+\trte_ethdev_trace_get_eeprom(port_id, info, ret);\n+\n+\treturn ret;\n }\n \n int\n rte_eth_dev_set_eeprom(uint16_t port_id, struct rte_dev_eeprom_info *info)\n {\n \tstruct rte_eth_dev *dev;\n+\tint ret;\n \n \tRTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);\n \tdev = &rte_eth_devices[port_id];\n@@ -5903,7 +6171,11 @@ rte_eth_dev_set_eeprom(uint16_t port_id, struct rte_dev_eeprom_info *info)\n \n \tif (*dev->dev_ops->set_eeprom == NULL)\n \t\treturn -ENOTSUP;\n-\treturn eth_err(port_id, (*dev->dev_ops->set_eeprom)(dev, info));\n+\tret = eth_err(port_id, (*dev->dev_ops->set_eeprom)(dev, info));\n+\n+\trte_ethdev_trace_set_eeprom(port_id, info, ret);\n+\n+\treturn ret;\n }\n \n int\n@@ -5911,6 +6183,7 @@ rte_eth_dev_get_module_info(uint16_t port_id,\n \t\t\t    struct rte_eth_dev_module_info *modinfo)\n {\n \tstruct rte_eth_dev *dev;\n+\tint ret;\n \n \tRTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);\n \tdev = &rte_eth_devices[port_id];\n@@ -5924,7 +6197,11 @@ rte_eth_dev_get_module_info(uint16_t port_id,\n \n \tif (*dev->dev_ops->get_module_info == NULL)\n \t\treturn -ENOTSUP;\n-\treturn (*dev->dev_ops->get_module_info)(dev, modinfo);\n+\tret = (*dev->dev_ops->get_module_info)(dev, modinfo);\n+\n+\trte_ethdev_trace_get_module_info(port_id, modinfo, ret);\n+\n+\treturn ret;\n }\n \n int\n@@ -5932,6 +6209,7 @@ rte_eth_dev_get_module_eeprom(uint16_t port_id,\n \t\t\t      struct rte_dev_eeprom_info *info)\n {\n \tstruct rte_eth_dev *dev;\n+\tint ret;\n \n \tRTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);\n \tdev = &rte_eth_devices[port_id];\n@@ -5959,7 +6237,11 @@ rte_eth_dev_get_module_eeprom(uint16_t port_id,\n \n \tif (*dev->dev_ops->get_module_eeprom == NULL)\n \t\treturn -ENOTSUP;\n-\treturn (*dev->dev_ops->get_module_eeprom)(dev, info);\n+\tret = (*dev->dev_ops->get_module_eeprom)(dev, info);\n+\n+\trte_ethdev_trace_get_module_eeprom(port_id, info, ret);\n+\n+\treturn ret;\n }\n \n int\n@@ -5967,6 +6249,7 @@ rte_eth_dev_get_dcb_info(uint16_t port_id,\n \t\t\t     struct rte_eth_dcb_info *dcb_info)\n {\n \tstruct rte_eth_dev *dev;\n+\tint ret;\n \n \tRTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);\n \tdev = &rte_eth_devices[port_id];\n@@ -5982,7 +6265,11 @@ rte_eth_dev_get_dcb_info(uint16_t port_id,\n \n \tif (*dev->dev_ops->get_dcb_info == NULL)\n \t\treturn -ENOTSUP;\n-\treturn eth_err(port_id, (*dev->dev_ops->get_dcb_info)(dev, dcb_info));\n+\tret = eth_err(port_id, (*dev->dev_ops->get_dcb_info)(dev, dcb_info));\n+\n+\trte_ethdev_trace_get_dcb_info(port_id, dcb_info, ret);\n+\n+\treturn ret;\n }\n \n static void\n@@ -6018,6 +6305,8 @@ rte_eth_dev_adjust_nb_rx_tx_desc(uint16_t port_id,\n \tif (nb_tx_desc != NULL)\n \t\teth_dev_adjust_nb_desc(nb_tx_desc, &dev_info.tx_desc_lim);\n \n+\trte_ethdev_trace_adjust_nb_rx_tx_desc(port_id);\n+\n \treturn 0;\n }\n \n@@ -6026,6 +6315,7 @@ rte_eth_dev_hairpin_capability_get(uint16_t port_id,\n \t\t\t\t   struct rte_eth_hairpin_cap *cap)\n {\n \tstruct rte_eth_dev *dev;\n+\tint ret;\n \n \tRTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);\n \tdev = &rte_eth_devices[port_id];\n@@ -6040,13 +6330,18 @@ rte_eth_dev_hairpin_capability_get(uint16_t port_id,\n \tif (*dev->dev_ops->hairpin_cap_get == NULL)\n \t\treturn -ENOTSUP;\n \tmemset(cap, 0, sizeof(*cap));\n-\treturn eth_err(port_id, (*dev->dev_ops->hairpin_cap_get)(dev, cap));\n+\tret = eth_err(port_id, (*dev->dev_ops->hairpin_cap_get)(dev, cap));\n+\n+\trte_ethdev_trace_hairpin_capability_get(port_id, cap, ret);\n+\n+\treturn ret;\n }\n \n int\n rte_eth_dev_pool_ops_supported(uint16_t port_id, const char *pool)\n {\n \tstruct rte_eth_dev *dev;\n+\tint ret;\n \n \tRTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);\n \tdev = &rte_eth_devices[port_id];\n@@ -6061,7 +6356,11 @@ rte_eth_dev_pool_ops_supported(uint16_t port_id, const char *pool)\n \tif (*dev->dev_ops->pool_ops_supported == NULL)\n \t\treturn 1; /* all pools are supported */\n \n-\treturn (*dev->dev_ops->pool_ops_supported)(dev, pool);\n+\tret = (*dev->dev_ops->pool_ops_supported)(dev, pool);\n+\n+\trte_ethdev_trace_pool_ops_supported(port_id, pool, ret);\n+\n+\treturn ret;\n }\n \n static int\n@@ -6352,19 +6651,25 @@ rte_eth_representor_info_get(uint16_t port_id,\n \t\t\t     struct rte_eth_representor_info *info)\n {\n \tstruct rte_eth_dev *dev;\n+\tint ret;\n \n \tRTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);\n \tdev = &rte_eth_devices[port_id];\n \n \tif (*dev->dev_ops->representor_info_get == NULL)\n \t\treturn -ENOTSUP;\n-\treturn eth_err(port_id, (*dev->dev_ops->representor_info_get)(dev, info));\n+\tret = eth_err(port_id, (*dev->dev_ops->representor_info_get)(dev, info));\n+\n+\trte_eth_trace_representor_info_get(port_id, info, ret);\n+\n+\treturn ret;\n }\n \n int\n rte_eth_rx_metadata_negotiate(uint16_t port_id, uint64_t *features)\n {\n \tstruct rte_eth_dev *dev;\n+\tint ret;\n \n \tRTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);\n \tdev = &rte_eth_devices[port_id];\n@@ -6383,8 +6688,12 @@ rte_eth_rx_metadata_negotiate(uint16_t port_id, uint64_t *features)\n \n \tif (*dev->dev_ops->rx_metadata_negotiate == NULL)\n \t\treturn -ENOTSUP;\n-\treturn eth_err(port_id,\n-\t\t       (*dev->dev_ops->rx_metadata_negotiate)(dev, features));\n+\tret = eth_err(port_id,\n+\t\t      (*dev->dev_ops->rx_metadata_negotiate)(dev, features));\n+\n+\trte_eth_trace_rx_metadata_negotiate(port_id, *features, ret);\n+\n+\treturn ret;\n }\n \n int\n@@ -6392,6 +6701,7 @@ rte_eth_ip_reassembly_capability_get(uint16_t port_id,\n \t\tstruct rte_eth_ip_reassembly_params *reassembly_capa)\n {\n \tstruct rte_eth_dev *dev;\n+\tint ret;\n \n \tRTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);\n \tdev = &rte_eth_devices[port_id];\n@@ -6413,8 +6723,13 @@ rte_eth_ip_reassembly_capability_get(uint16_t port_id,\n \t\treturn -ENOTSUP;\n \tmemset(reassembly_capa, 0, sizeof(struct rte_eth_ip_reassembly_params));\n \n-\treturn eth_err(port_id, (*dev->dev_ops->ip_reassembly_capability_get)\n+\tret = eth_err(port_id, (*dev->dev_ops->ip_reassembly_capability_get)\n \t\t\t\t\t(dev, reassembly_capa));\n+\n+\trte_eth_trace_ip_reassembly_capability_get(port_id, reassembly_capa,\n+\t\t\t\t\t\t   ret);\n+\n+\treturn ret;\n }\n \n int\n@@ -6422,6 +6737,7 @@ rte_eth_ip_reassembly_conf_get(uint16_t port_id,\n \t\tstruct rte_eth_ip_reassembly_params *conf)\n {\n \tstruct rte_eth_dev *dev;\n+\tint ret;\n \n \tRTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);\n \tdev = &rte_eth_devices[port_id];\n@@ -6442,8 +6758,12 @@ rte_eth_ip_reassembly_conf_get(uint16_t port_id,\n \tif (*dev->dev_ops->ip_reassembly_conf_get == NULL)\n \t\treturn -ENOTSUP;\n \tmemset(conf, 0, sizeof(struct rte_eth_ip_reassembly_params));\n-\treturn eth_err(port_id,\n-\t\t       (*dev->dev_ops->ip_reassembly_conf_get)(dev, conf));\n+\tret = eth_err(port_id,\n+\t\t      (*dev->dev_ops->ip_reassembly_conf_get)(dev, conf));\n+\n+\trte_eth_trace_ip_reassembly_conf_get(port_id, conf, ret);\n+\n+\treturn ret;\n }\n \n int\n@@ -6451,6 +6771,7 @@ rte_eth_ip_reassembly_conf_set(uint16_t port_id,\n \t\tconst struct rte_eth_ip_reassembly_params *conf)\n {\n \tstruct rte_eth_dev *dev;\n+\tint ret;\n \n \tRTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);\n \tdev = &rte_eth_devices[port_id];\n@@ -6479,8 +6800,12 @@ rte_eth_ip_reassembly_conf_set(uint16_t port_id,\n \n \tif (*dev->dev_ops->ip_reassembly_conf_set == NULL)\n \t\treturn -ENOTSUP;\n-\treturn eth_err(port_id,\n-\t\t       (*dev->dev_ops->ip_reassembly_conf_set)(dev, conf));\n+\tret = eth_err(port_id,\n+\t\t      (*dev->dev_ops->ip_reassembly_conf_set)(dev, conf));\n+\n+\trte_eth_trace_ip_reassembly_conf_set(port_id, conf, ret);\n+\n+\treturn ret;\n }\n \n int\n@@ -6578,8 +6903,12 @@ rte_eth_buffer_split_get_supported_hdr_ptypes(uint16_t port_id, uint32_t *ptypes\n \t\treturn 0;\n \n \tfor (i = 0, j = 0; all_types[i] != RTE_PTYPE_UNKNOWN; ++i) {\n-\t\tif (j < num)\n+\t\tif (j < num) {\n \t\t\tptypes[j] = all_types[i];\n+\n+\t\t\trte_eth_trace_buffer_split_get_supported_hdr_ptypes(\n+\t\t\t\t\t\t\tport_id, j, ptypes[j]);\n+\t\t}\n \t\tj++;\n \t}\n \ndiff --git a/lib/ethdev/rte_ethdev_cman.c b/lib/ethdev/rte_ethdev_cman.c\nindex 4a1bdd7bd0..a9c4637521 100644\n--- a/lib/ethdev/rte_ethdev_cman.c\n+++ b/lib/ethdev/rte_ethdev_cman.c\n@@ -8,12 +8,14 @@\n #include \"rte_ethdev.h\"\n #include \"ethdev_driver.h\"\n #include \"ethdev_private.h\"\n+#include \"ethdev_trace.h\"\n \n /* Get congestion management information for a port */\n int\n rte_eth_cman_info_get(uint16_t port_id, struct rte_eth_cman_info *info)\n {\n \tstruct rte_eth_dev *dev;\n+\tint ret;\n \n \tRTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);\n \tdev = &rte_eth_devices[port_id];\n@@ -29,7 +31,11 @@ rte_eth_cman_info_get(uint16_t port_id, struct rte_eth_cman_info *info)\n \t}\n \n \tmemset(info, 0, sizeof(struct rte_eth_cman_info));\n-\treturn eth_err(port_id, (*dev->dev_ops->cman_info_get)(dev, info));\n+\tret = eth_err(port_id, (*dev->dev_ops->cman_info_get)(dev, info));\n+\n+\trte_eth_trace_cman_info_get(port_id, info, ret);\n+\n+\treturn ret;\n }\n \n /* Initialize congestion management structure with default values */\n@@ -37,6 +43,7 @@ int\n rte_eth_cman_config_init(uint16_t port_id, struct rte_eth_cman_config *config)\n {\n \tstruct rte_eth_dev *dev;\n+\tint ret;\n \n \tRTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);\n \tdev = &rte_eth_devices[port_id];\n@@ -52,7 +59,11 @@ rte_eth_cman_config_init(uint16_t port_id, struct rte_eth_cman_config *config)\n \t}\n \n \tmemset(config, 0, sizeof(struct rte_eth_cman_config));\n-\treturn eth_err(port_id, (*dev->dev_ops->cman_config_init)(dev, config));\n+\tret = eth_err(port_id, (*dev->dev_ops->cman_config_init)(dev, config));\n+\n+\trte_eth_trace_cman_config_init(port_id, config, ret);\n+\n+\treturn ret;\n }\n \n /* Configure congestion management on a port */\n@@ -60,6 +71,7 @@ int\n rte_eth_cman_config_set(uint16_t port_id, const struct rte_eth_cman_config *config)\n {\n \tstruct rte_eth_dev *dev;\n+\tint ret;\n \n \tRTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);\n \tdev = &rte_eth_devices[port_id];\n@@ -74,7 +86,11 @@ rte_eth_cman_config_set(uint16_t port_id, const struct rte_eth_cman_config *conf\n \t\treturn -ENOTSUP;\n \t}\n \n-\treturn eth_err(port_id, (*dev->dev_ops->cman_config_set)(dev, config));\n+\tret = eth_err(port_id, (*dev->dev_ops->cman_config_set)(dev, config));\n+\n+\trte_eth_trace_cman_config_set(port_id, config, ret);\n+\n+\treturn ret;\n }\n \n /* Retrieve congestion management configuration of a port */\n@@ -82,6 +98,7 @@ int\n rte_eth_cman_config_get(uint16_t port_id, struct rte_eth_cman_config *config)\n {\n \tstruct rte_eth_dev *dev;\n+\tint ret;\n \n \tRTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);\n \tdev = &rte_eth_devices[port_id];\n@@ -97,5 +114,9 @@ rte_eth_cman_config_get(uint16_t port_id, struct rte_eth_cman_config *config)\n \t}\n \n \tmemset(config, 0, sizeof(struct rte_eth_cman_config));\n-\treturn eth_err(port_id, (*dev->dev_ops->cman_config_get)(dev, config));\n+\tret = eth_err(port_id, (*dev->dev_ops->cman_config_get)(dev, config));\n+\n+\trte_eth_trace_cman_config_get(port_id, config, ret);\n+\n+\treturn ret;\n }\n",
    "prefixes": [
        "v10",
        "3/6"
    ]
}