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GET /api/patches/122978/?format=api
{ "id": 122978, "url": "http://patches.dpdk.org/api/patches/122978/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20230202162537.1067595-7-michaelba@nvidia.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20230202162537.1067595-7-michaelba@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20230202162537.1067595-7-michaelba@nvidia.com", "date": "2023-02-02T16:25:35", "name": "[v2,6/8] compress/mlx5: add xform validate function", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "03ddfe3506845659f0f3003172f128e6067c66b4", "submitter": { "id": 1949, "url": "http://patches.dpdk.org/api/people/1949/?format=api", "name": "Michael Baum", "email": "michaelba@nvidia.com" }, "delegate": { "id": 6690, "url": "http://patches.dpdk.org/api/users/6690/?format=api", "username": "akhil", "first_name": "akhil", "last_name": "goyal", "email": "gakhil@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20230202162537.1067595-7-michaelba@nvidia.com/mbox/", "series": [ { "id": 26766, "url": "http://patches.dpdk.org/api/series/26766/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=26766", "date": "2023-02-02T16:25:29", "name": "compress/mlx5: add LZ4 support", "version": 2, "mbox": "http://patches.dpdk.org/series/26766/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/122978/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/122978/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": 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b=Nb/dizjzrzSaLxBSKFrhAIDwG1hvEU2xf7f84UJDM9HmjWKzclJp4PadXCz4lhoX0vKhYoXa1GRSlVyVxy5gZuHE/gDhbAlpfVoVAYVsiYqlN7LpqiIUoRITnTyyokDaBM0fYBUjvh9ZTV+s5qWwolFF2JHf/qaqJGKkZJLgVhvWVaA8e0e8G6HyhU9s1xFNL4YF+Oc+HHlJoAXlYHoyqVsM4yDUnuTD1L9fSOumqs1P+EBMKwzHoWBu5AZDCP3bArv+YILlIGLHeYdvISMQFlQsmWxm/APD76e7jgvR8xUISDWJz7o4wzdtphcY2TfQkv/CC+t/syBh8pIfJjFSjg==", "X-MS-Exchange-Authentication-Results": "spf=pass (sender IP is 216.228.117.161)\n smtp.mailfrom=nvidia.com;\n dkim=none (message not signed)\n header.d=none;dmarc=pass action=none header.from=nvidia.com;", "Received-SPF": "Pass (protection.outlook.com: domain of nvidia.com designates\n 216.228.117.161 as permitted sender) receiver=protection.outlook.com;\n client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C", "From": "Michael Baum <michaelba@nvidia.com>", "To": "<dev@dpdk.org>", "CC": "Matan Azrad <matan@nvidia.com>, Akhil Goyal <gakhil@marvell.com>, \"Thomas\n Monjalon\" <thomas@monjalon.net>", "Subject": "[PATCH v2 6/8] compress/mlx5: add xform validate function", "Date": "Thu, 2 Feb 2023 18:25:35 +0200", "Message-ID": "<20230202162537.1067595-7-michaelba@nvidia.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20230202162537.1067595-1-michaelba@nvidia.com>", "References": "<20230109075838.2508039-1-michaelba@nvidia.com>\n <20230202162537.1067595-1-michaelba@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "DM6NAM11FT113:EE_|MW3PR12MB4379:EE_", "X-MS-Office365-Filtering-Correlation-Id": "dbefb4f3-7f10-4dac-146c-08db053a30ae", "X-LD-Processed": "43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n lqEhfr1kTt+3aDwDr6VzbPJ8CHsnTBqFMBhv+fGPEEAzrYcO4zc7vcInd7ivXrpx7h2G/Dz/mRByX+UVqkU1mjH8N+KLYQGGCjmULKLjLyeFEi8vBEbiB01WSazuJJVx85TuUZHWd1W/nNsMNkUXVpDhqAudx+9WKfKNfLJd+FXsLfh1Inadh/l0ZcLE9CcnuPJsSGn8Gol1T0gvt0/ODtRlQ8TwbKjrQCfxRlVd1UGMIWHdW2kYR0Y9JSK/AL476MPn9ruCQkVvJ2bDZOBF086OAaIHReo34rPXKXjNCERrlcBFkjGAZiAXKNNHBdh9Mc80KyqNrjvFPMZtZO5cfpE170K6ECuMgqbG1DWz+S6FRLme0zjwQpgVo0H13WfOluJRzuAp3ojCN1WKiFgL5/V68X9L6ZSagyk3sEHOhIlk33+kzYsNsoPNzY7LcAHndk3g39UgUcw+WTYaCjymyZRVyFthw0av04pcthxdMVKmEV18ib6xsXgmKr1j0yhCj9R3wiDoNfmA8od0eEJpCle2+nZpG3YNfkfTjudUXEMFe9/62y2Xph6KdDkZ6oKSw2BDLg7cbEw6VCqo27Kw8ta7PWUqJfzVI3fGxfoxDqKv+j0X6pFmlCNa+6YDe32DsyxnASflrScfDrNnAEtTIFQH9832TDLgio/k7zGMqDoVtrXhfbx9uxO7rJDVO7sH", "X-Forefront-Antispam-Report": "CIP:216.228.117.161; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE;\n SFS:(13230025)(4636009)(39860400002)(136003)(376002)(396003)(346002)(451199018)(40470700004)(36840700001)(46966006)(6916009)(70206006)(7636003)(82310400005)(356005)(70586007)(4326008)(55016003)(41300700001)(5660300002)(316002)(8676002)(8936002)(86362001)(54906003)(82740400003)(36756003)(40480700001)(478600001)(2906002)(40460700003)(426003)(47076005)(7696005)(83380400001)(36860700001)(336012)(6666004)(1076003)(26005)(2616005)(186003)(6286002);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "02 Feb 2023 16:26:08.4607 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n dbefb4f3-7f10-4dac-146c-08db053a30ae", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n DM6NAM11FT113.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "MW3PR12MB4379", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Separate the xform validations from create function into new function.\nThe new function checks caps directly from HCA attr structure, so all\ncapabilities in priv structure were removed.\n\nSigned-off-by: Michael Baum <michaelba@nvidia.com>\n---\n drivers/compress/mlx5/mlx5_compress.c | 75 +++++++++++++++------------\n 1 file changed, 42 insertions(+), 33 deletions(-)", "diff": "diff --git a/drivers/compress/mlx5/mlx5_compress.c b/drivers/compress/mlx5/mlx5_compress.c\nindex d54e49db97..7841f57b9c 100644\n--- a/drivers/compress/mlx5/mlx5_compress.c\n+++ b/drivers/compress/mlx5/mlx5_compress.c\n@@ -45,13 +45,6 @@ struct mlx5_compress_priv {\n \tstruct rte_compressdev_config dev_config;\n \tLIST_HEAD(xform_list, mlx5_compress_xform) xform_list;\n \trte_spinlock_t xform_sl;\n-\t/* HCA caps */\n-\tuint32_t mmo_decomp_sq:1;\n-\tuint32_t mmo_decomp_qp:1;\n-\tuint32_t mmo_comp_sq:1;\n-\tuint32_t mmo_comp_qp:1;\n-\tuint32_t mmo_dma_sq:1;\n-\tuint32_t mmo_dma_qp:1;\n \tuint32_t log_block_sz;\n \tuint32_t crc32_opaq_offs;\n };\n@@ -178,6 +171,7 @@ mlx5_compress_qp_setup(struct rte_compressdev *dev, uint16_t qp_id,\n \t\t uint32_t max_inflight_ops, int socket_id)\n {\n \tstruct mlx5_compress_priv *priv = dev->data->dev_private;\n+\tstruct mlx5_hca_attr *attr = &priv->cdev->config.hca_attr;\n \tstruct mlx5_compress_qp *qp;\n \tstruct mlx5_devx_cq_attr cq_attr = {\n \t\t.uar_page_id = mlx5_os_get_devx_uar_page_id(priv->uar.obj),\n@@ -238,12 +232,11 @@ mlx5_compress_qp_setup(struct rte_compressdev *dev, uint16_t qp_id,\n \t\tgoto err;\n \t}\n \tqp_attr.cqn = qp->cq.cq->id;\n-\tqp_attr.ts_format =\n-\t\tmlx5_ts_format_conv(priv->cdev->config.hca_attr.qp_ts_format);\n+\tqp_attr.ts_format = mlx5_ts_format_conv(attr->qp_ts_format);\n \tqp_attr.num_of_receive_wqes = 0;\n \tqp_attr.num_of_send_wqbbs = RTE_BIT32(log_ops_n);\n-\tqp_attr.mmo = priv->mmo_decomp_qp || priv->mmo_comp_qp ||\n-\t\t priv->mmo_dma_qp;\n+\tqp_attr.mmo = attr->mmo_compress_qp_en || attr->mmo_dma_qp_en ||\n+\t\t attr->decomp_deflate_v1_en || attr->decomp_deflate_v2_en;\n \tret = mlx5_devx_qp_create(priv->cdev->ctx, &qp->qp,\n \t\t\t\t\tqp_attr.num_of_send_wqbbs *\n \t\t\t\t\tMLX5_WQE_SIZE, &qp_attr, socket_id);\n@@ -276,21 +269,17 @@ mlx5_compress_xform_free(struct rte_compressdev *dev, void *xform)\n }\n \n static int\n-mlx5_compress_xform_create(struct rte_compressdev *dev,\n-\t\t\t const struct rte_comp_xform *xform,\n-\t\t\t void **private_xform)\n+mlx5_compress_xform_validate(const struct rte_comp_xform *xform,\n+\t\t\t const struct mlx5_hca_attr *attr)\n {\n-\tstruct mlx5_compress_priv *priv = dev->data->dev_private;\n-\tstruct mlx5_compress_xform *xfrm;\n-\tuint32_t size;\n-\n \tswitch (xform->type) {\n \tcase RTE_COMP_COMPRESS:\n \t\tif (xform->compress.algo == RTE_COMP_ALGO_NULL &&\n-\t\t\t\t!priv->mmo_dma_qp && !priv->mmo_dma_sq) {\n+\t\t !attr->mmo_dma_qp_en && !attr->mmo_dma_sq_en) {\n \t\t\tDRV_LOG(ERR, \"Not enough capabilities to support DMA operation, maybe old FW/OFED version?\");\n \t\t\treturn -ENOTSUP;\n-\t\t} else if (!priv->mmo_comp_qp && !priv->mmo_comp_sq) {\n+\t\t} else if (!attr->mmo_compress_qp_en &&\n+\t\t\t !attr->mmo_compress_sq_en) {\n \t\t\tDRV_LOG(ERR, \"Not enough capabilities to support compress operation, maybe old FW/OFED version?\");\n \t\t\treturn -ENOTSUP;\n \t\t}\n@@ -304,12 +293,24 @@ mlx5_compress_xform_create(struct rte_compressdev *dev,\n \t\t}\n \t\tbreak;\n \tcase RTE_COMP_DECOMPRESS:\n-\t\tif (xform->decompress.algo == RTE_COMP_ALGO_NULL &&\n-\t\t\t\t!priv->mmo_dma_qp && !priv->mmo_dma_sq) {\n-\t\t\tDRV_LOG(ERR, \"Not enough capabilities to support DMA operation, maybe old FW/OFED version?\");\n-\t\t\treturn -ENOTSUP;\n-\t\t} else if (!priv->mmo_decomp_qp && !priv->mmo_decomp_sq) {\n-\t\t\tDRV_LOG(ERR, \"Not enough capabilities to support decompress operation, maybe old FW/OFED version?\");\n+\t\tswitch (xform->decompress.algo) {\n+\t\tcase RTE_COMP_ALGO_NULL:\n+\t\t\tif (attr->mmo_dma_qp_en && !attr->mmo_dma_sq_en) {\n+\t\t\t\tDRV_LOG(ERR, \"Not enough capabilities to support DMA operation, maybe old FW/OFED version?\");\n+\t\t\t\treturn -ENOTSUP;\n+\t\t\t}\n+\t\t\tbreak;\n+\t\tcase RTE_COMP_ALGO_DEFLATE:\n+\t\t\tif (!attr->decomp_deflate_v1_en &&\n+\t\t\t !attr->decomp_deflate_v2_en &&\n+\t\t\t !attr->mmo_decompress_sq_en) {\n+\t\t\t\tDRV_LOG(ERR, \"Not enough capabilities to support decompress DEFLATE algorithm, maybe old FW/OFED version?\");\n+\t\t\t\treturn -ENOTSUP;\n+\t\t\t}\n+\t\t\tbreak;\n+\t\tdefault:\n+\t\t\tDRV_LOG(ERR, \"Algorithm %u is not supported.\",\n+\t\t\t\txform->decompress.algo);\n \t\t\treturn -ENOTSUP;\n \t\t}\n \t\tif (xform->decompress.hash_algo != RTE_COMP_HASH_ALGO_NONE) {\n@@ -321,7 +322,22 @@ mlx5_compress_xform_create(struct rte_compressdev *dev,\n \t\tDRV_LOG(ERR, \"Xform type should be compress/decompress\");\n \t\treturn -ENOTSUP;\n \t}\n+\treturn 0;\n+}\n+\n+static int\n+mlx5_compress_xform_create(struct rte_compressdev *dev,\n+\t\t\t const struct rte_comp_xform *xform,\n+\t\t\t void **private_xform)\n+{\n+\tstruct mlx5_compress_priv *priv = dev->data->dev_private;\n+\tstruct mlx5_compress_xform *xfrm;\n+\tuint32_t size;\n+\tint ret;\n \n+\tret = mlx5_compress_xform_validate(xform, &priv->cdev->config.hca_attr);\n+\tif (ret < 0)\n+\t\treturn ret;\n \txfrm = rte_zmalloc_socket(__func__, sizeof(*xfrm), 0,\n \t\t\t\t\t\t priv->dev_config.socket_id);\n \tif (xfrm == NULL)\n@@ -747,13 +763,6 @@ mlx5_compress_dev_probe(struct mlx5_common_device *cdev,\n \tcompressdev->feature_flags = RTE_COMPDEV_FF_HW_ACCELERATED;\n \tpriv = compressdev->data->dev_private;\n \tpriv->log_block_sz = devarg_prms.log_block_sz;\n-\tpriv->mmo_decomp_sq = attr->mmo_decompress_sq_en;\n-\tpriv->mmo_decomp_qp =\n-\t\t\tattr->decomp_deflate_v1_en | attr->decomp_deflate_v2_en;\n-\tpriv->mmo_comp_sq = attr->mmo_compress_sq_en;\n-\tpriv->mmo_comp_qp = attr->mmo_compress_qp_en;\n-\tpriv->mmo_dma_sq = attr->mmo_dma_sq_en;\n-\tpriv->mmo_dma_qp = attr->mmo_dma_qp_en;\n \tif (attr->decomp_deflate_v2_en)\n \t\tcrc32_opaq_offset = offsetof(union mlx5_gga_compress_opaque,\n \t\t\t\t\t v2.crc32);\n", "prefixes": [ "v2", "6/8" ] }