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GET /api/patches/122974/?format=api
{ "id": 122974, "url": "http://patches.dpdk.org/api/patches/122974/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20230202162537.1067595-5-michaelba@nvidia.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20230202162537.1067595-5-michaelba@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20230202162537.1067595-5-michaelba@nvidia.com", "date": "2023-02-02T16:25:33", "name": "[v2,4/8] compress/mlx5: support new metadata layout added in BF3", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "cf2c9b26566b0698b3e75de6997f190a1d26e839", "submitter": { "id": 1949, "url": "http://patches.dpdk.org/api/people/1949/?format=api", "name": "Michael Baum", "email": "michaelba@nvidia.com" }, "delegate": { "id": 6690, "url": "http://patches.dpdk.org/api/users/6690/?format=api", "username": "akhil", "first_name": "akhil", "last_name": "goyal", "email": "gakhil@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20230202162537.1067595-5-michaelba@nvidia.com/mbox/", "series": [ { "id": 26766, "url": "http://patches.dpdk.org/api/series/26766/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=26766", "date": "2023-02-02T16:25:29", "name": "compress/mlx5: add LZ4 support", "version": 2, "mbox": "http://patches.dpdk.org/series/26766/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/122974/comments/", "check": "warning", "checks": "http://patches.dpdk.org/api/patches/122974/checks/", "tags": {}, "related": [], "headers": { "Return-Path": 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b=TXey6qlDo/U6aoq+axY6BQJlvuQFMpkGGY8K/QPSDpn0DGp2CdJNNG1m6Ndjz30EMPONUTBF9UqoUY/4TZJpaYL8Pd4SKdUyShshIQxt5yS6jyiQjZNQlZrEV9A1kEUf6W3TQ3JV1VIf9cYgCtUKaUe2erGOAgDJPbBDvGvdgd+auS4xCMF7Bxzu+tdmrCsy456QuzcKfn6LlSXX0KXLy6+JXCBcJt6I9on68JhP9Rf4En4dNTPgxsr0g7+Z3hO0km4dSYDzM5aj6A/mTzGw0HJIRDAHWXS3cSvFDB/Ji58hCd6AdZrnJ/NEswpMA9f+nmsUi+/vgceO0xQ3AA1fRg==", "X-MS-Exchange-Authentication-Results": "spf=pass (sender IP is 216.228.117.160)\n smtp.mailfrom=nvidia.com;\n dkim=none (message not signed)\n header.d=none;dmarc=pass action=none header.from=nvidia.com;", "Received-SPF": "Pass (protection.outlook.com: domain of nvidia.com designates\n 216.228.117.160 as permitted sender) receiver=protection.outlook.com;\n client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C", "From": "Michael Baum <michaelba@nvidia.com>", "To": "<dev@dpdk.org>", "CC": "Matan Azrad <matan@nvidia.com>, Akhil Goyal <gakhil@marvell.com>, \"Thomas\n Monjalon\" <thomas@monjalon.net>", "Subject": "[PATCH v2 4/8] compress/mlx5: support new metadata layout added in\n BF3", "Date": "Thu, 2 Feb 2023 18:25:33 +0200", "Message-ID": "<20230202162537.1067595-5-michaelba@nvidia.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20230202162537.1067595-1-michaelba@nvidia.com>", "References": "<20230109075838.2508039-1-michaelba@nvidia.com>\n <20230202162537.1067595-1-michaelba@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "DM6NAM11FT052:EE_|DM4PR12MB7622:EE_", "X-MS-Office365-Filtering-Correlation-Id": "91d3c478-248d-4810-ff36-08db053a2bd8", "X-LD-Processed": "43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n 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SFS:(13230025)(4636009)(396003)(136003)(39860400002)(346002)(376002)(451199018)(36840700001)(46966006)(40470700004)(336012)(83380400001)(6666004)(2616005)(54906003)(426003)(316002)(36756003)(82310400005)(2906002)(7636003)(82740400003)(36860700001)(1076003)(70586007)(70206006)(6916009)(4326008)(8676002)(7696005)(40460700003)(478600001)(186003)(6286002)(26005)(47076005)(55016003)(40480700001)(5660300002)(86362001)(41300700001)(356005)(8936002);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "02 Feb 2023 16:26:00.3534 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 91d3c478-248d-4810-ff36-08db053a2bd8", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n DM6NAM11FT052.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "DM4PR12MB7622", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Commit [1] add support in Bluefield-3, but Bluefield-3 has different\nGGA opaque structure than Bluefield-2.\n\nThis patch updates the PRM structure to include both versions, and\nculculate the relevant offset for each version in control path.\n\nCommit [1] 559014f232b4 (\"compress/mlx5: add Bluefield-3 device ID\")\n\nSigned-off-by: Michael Baum <michaelba@nvidia.com>\n---\n drivers/common/mlx5/mlx5_devx_cmds.c | 6 ++--\n drivers/common/mlx5/mlx5_devx_cmds.h | 3 +-\n drivers/common/mlx5/mlx5_prm.h | 40 +++++++++++++++---------\n drivers/compress/mlx5/mlx5_compress.c | 45 +++++++++++++++++----------\n 4 files changed, 61 insertions(+), 33 deletions(-)", "diff": "diff --git a/drivers/common/mlx5/mlx5_devx_cmds.c b/drivers/common/mlx5/mlx5_devx_cmds.c\nindex 59cebb530f..dfec4dcf1b 100644\n--- a/drivers/common/mlx5/mlx5_devx_cmds.c\n+++ b/drivers/common/mlx5/mlx5_devx_cmds.c\n@@ -978,8 +978,10 @@ mlx5_devx_cmd_query_hca_attr(void *ctx,\n \tattr->mmo_dma_qp_en = MLX5_GET(cmd_hca_cap, hcattr, dma_mmo_qp);\n \tattr->mmo_compress_qp_en = MLX5_GET(cmd_hca_cap, hcattr,\n \t\t\tcompress_mmo_qp);\n-\tattr->mmo_decompress_qp_en = MLX5_GET(cmd_hca_cap, hcattr,\n-\t\t\tdecompress_mmo_qp);\n+\tattr->decomp_deflate_v1_en = MLX5_GET(cmd_hca_cap, hcattr,\n+\t\t\t\t\t decompress_deflate_v1);\n+\tattr->decomp_deflate_v2_en = MLX5_GET(cmd_hca_cap, hcattr,\n+\t\t\t\t\t decompress_deflate_v2);\n \tattr->compress_min_block_size = MLX5_GET(cmd_hca_cap, hcattr,\n \t\t\t\t\t\t compress_min_block_size);\n \tattr->log_max_mmo_dma = MLX5_GET(cmd_hca_cap, hcattr, log_dma_mmo_size);\ndiff --git a/drivers/common/mlx5/mlx5_devx_cmds.h b/drivers/common/mlx5/mlx5_devx_cmds.h\nindex c94b9eac06..edb387e272 100644\n--- a/drivers/common/mlx5/mlx5_devx_cmds.h\n+++ b/drivers/common/mlx5/mlx5_devx_cmds.h\n@@ -259,7 +259,8 @@ struct mlx5_hca_attr {\n \tuint32_t mmo_decompress_sq_en:1;\n \tuint32_t mmo_dma_qp_en:1;\n \tuint32_t mmo_compress_qp_en:1;\n-\tuint32_t mmo_decompress_qp_en:1;\n+\tuint32_t decomp_deflate_v1_en:1;\n+\tuint32_t decomp_deflate_v2_en:1;\n \tuint32_t mmo_regex_qp_en:1;\n \tuint32_t mmo_regex_sq_en:1;\n \tuint32_t compress_min_block_size:4;\ndiff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h\nindex 2b5c43ee6e..377cbfab87 100644\n--- a/drivers/common/mlx5/mlx5_prm.h\n+++ b/drivers/common/mlx5/mlx5_prm.h\n@@ -607,17 +607,27 @@ struct mlx5_gga_wqe {\n \tstruct mlx5_wqe_dseg scatter;\n } __rte_packed;\n \n-struct mlx5_gga_compress_opaque {\n-\tuint32_t syndrom;\n-\tuint32_t reserved0;\n-\tuint32_t scattered_length;\n-\tuint32_t gathered_length;\n-\tuint64_t scatter_crc;\n-\tuint64_t gather_crc;\n-\tuint32_t crc32;\n-\tuint32_t adler32;\n-\tuint8_t reserved1[216];\n-} __rte_packed;\n+union mlx5_gga_compress_opaque {\n+\tstruct {\n+\t\tuint32_t syndrome;\n+\t\tuint32_t reserved0;\n+\t\tuint32_t scattered_length;\n+\t\tunion {\n+\t\t\tstruct {\n+\t\t\t\tuint32_t reserved1[5];\n+\t\t\t\tuint32_t crc32;\n+\t\t\t\tuint32_t adler32;\n+\t\t\t} v1 __rte_packed;\n+\t\t\tstruct {\n+\t\t\t\tuint32_t crc32;\n+\t\t\t\tuint32_t adler32;\n+\t\t\t\tuint32_t crc32c;\n+\t\t\t\tuint32_t xxh32;\n+\t\t\t} v2 __rte_packed;\n+\t\t};\n+\t} __rte_packed;\n+\tuint32_t data[64];\n+};\n \n struct mlx5_ifc_regexp_mmo_control_bits {\n \tuint8_t reserved_at_31[0x2];\n@@ -1463,7 +1473,7 @@ struct mlx5_ifc_cmd_hca_cap_bits {\n \tu8 log_max_bsf_list_size[0x6];\n \tu8 umr_extended_translation_offset[0x1];\n \tu8 null_mkey[0x1];\n-\tu8 log_max_klm_list_size[0x6];\n+\tu8 log_maxklm_list_size[0x6];\n \tu8 non_wire_sq[0x1];\n \tu8 reserved_at_121[0x9];\n \tu8 log_max_ra_req_dc[0x6];\n@@ -1749,8 +1759,10 @@ struct mlx5_ifc_cmd_hca_cap_bits {\n \tu8 dma_mmo_qp[0x1];\n \tu8 regexp_mmo_qp[0x1];\n \tu8 compress_mmo_qp[0x1];\n-\tu8 decompress_mmo_qp[0x1];\n-\tu8 reserved_at_74c[0x14];\n+\tu8 decompress_deflate_v1[0x1];\n+\tu8 reserved_at_74c[0x4];\n+\tu8 decompress_deflate_v2[0x1];\n+\tu8 reserved_at_751[0xf];\n \tu8 reserved_at_760[0x3];\n \tu8 log_max_num_header_modify_argument[0x5];\n \tu8 log_header_modify_argument_granularity_offset[0x4];\ndiff --git a/drivers/compress/mlx5/mlx5_compress.c b/drivers/compress/mlx5/mlx5_compress.c\nindex c4bf62ed41..11fad72a4f 100644\n--- a/drivers/compress/mlx5/mlx5_compress.c\n+++ b/drivers/compress/mlx5/mlx5_compress.c\n@@ -55,6 +55,7 @@ struct mlx5_compress_priv {\n \tuint32_t mmo_dma_sq:1;\n \tuint32_t mmo_dma_qp:1;\n \tuint32_t log_block_sz;\n+\tuint32_t crc32_opaq_offs;\n };\n \n struct mlx5_compress_qp {\n@@ -157,7 +158,7 @@ mlx5_compress_init_qp(struct mlx5_compress_qp *qp)\n {\n \tvolatile struct mlx5_gga_wqe *restrict wqe =\n \t\t\t\t (volatile struct mlx5_gga_wqe *)qp->qp.wqes;\n-\tvolatile struct mlx5_gga_compress_opaque *opaq = qp->opaque_mr.addr;\n+\tvolatile union mlx5_gga_compress_opaque *opaq = qp->opaque_mr.addr;\n \tconst uint32_t sq_ds = rte_cpu_to_be_32((qp->qp.qp->id << 8) | 4u);\n \tconst uint32_t flags = RTE_BE32(MLX5_COMP_ALWAYS <<\n \t\t\t\t\tMLX5_COMP_MODE_OFFSET);\n@@ -211,8 +212,8 @@ mlx5_compress_qp_setup(struct rte_compressdev *dev, uint16_t qp_id,\n \t\tgoto err;\n \t}\n \topaq_buf = rte_calloc(__func__, (size_t)1 << log_ops_n,\n-\t\t\t sizeof(struct mlx5_gga_compress_opaque),\n-\t\t\t sizeof(struct mlx5_gga_compress_opaque));\n+\t\t\t sizeof(union mlx5_gga_compress_opaque),\n+\t\t\t sizeof(union mlx5_gga_compress_opaque));\n \tif (opaq_buf == NULL) {\n \t\tDRV_LOG(ERR, \"Failed to allocate opaque memory.\");\n \t\trte_errno = ENOMEM;\n@@ -225,7 +226,7 @@ mlx5_compress_qp_setup(struct rte_compressdev *dev, uint16_t qp_id,\n \tqp->ops = (struct rte_comp_op **)RTE_ALIGN((uintptr_t)(qp + 1),\n \t\t\t\t\t\t RTE_CACHE_LINE_SIZE);\n \tif (mlx5_common_verbs_reg_mr(priv->cdev->pd, opaq_buf, qp->entries_n *\n-\t\t\t\t\tsizeof(struct mlx5_gga_compress_opaque),\n+\t\t\t\t\tsizeof(union mlx5_gga_compress_opaque),\n \t\t\t\t\t\t\t &qp->opaque_mr) != 0) {\n \t\trte_free(opaq_buf);\n \t\tDRV_LOG(ERR, \"Failed to register opaque MR.\");\n@@ -544,7 +545,7 @@ mlx5_compress_dump_err_objs(volatile uint32_t *cqe, volatile uint32_t *wqe,\n \t\tDRV_LOG(ERR, \"%08X %08X %08X %08X\", wqe[i], wqe[i + 1],\n \t\t\twqe[i + 2], wqe[i + 3]);\n \tDRV_LOG(ERR, \"\\nError opaq:\");\n-\tfor (i = 0; i < sizeof(struct mlx5_gga_compress_opaque) >> 2; i += 4)\n+\tfor (i = 0; i < sizeof(union mlx5_gga_compress_opaque) >> 2; i += 4)\n \t\tDRV_LOG(ERR, \"%08X %08X %08X %08X\", opaq[i], opaq[i + 1],\n \t\t\topaq[i + 2], opaq[i + 3]);\n }\n@@ -558,7 +559,7 @@ mlx5_compress_cqe_err_handle(struct mlx5_compress_qp *qp,\n \t\t\t\t\t\t\t &qp->cq.cqes[idx];\n \tvolatile struct mlx5_gga_wqe *wqes = (volatile struct mlx5_gga_wqe *)\n \t\t\t\t\t\t\t\t qp->qp.wqes;\n-\tvolatile struct mlx5_gga_compress_opaque *opaq = qp->opaque_mr.addr;\n+\tvolatile union mlx5_gga_compress_opaque *opaq = qp->opaque_mr.addr;\n \n \tvolatile uint32_t *synd_word = RTE_PTR_ADD(cqe, MLX5_ERROR_CQE_SYNDROME_OFFSET);\n \tswitch (*synd_word) {\n@@ -575,7 +576,7 @@ mlx5_compress_cqe_err_handle(struct mlx5_compress_qp *qp,\n \top->consumed = 0;\n \top->produced = 0;\n \top->output_chksum = 0;\n-\top->debug_status = rte_be_to_cpu_32(opaq[idx].syndrom) |\n+\top->debug_status = rte_be_to_cpu_32(opaq[idx].syndrome) |\n \t\t\t ((uint64_t)rte_be_to_cpu_32(cqe->syndrome) << 32);\n \tmlx5_compress_dump_err_objs((volatile uint32_t *)cqe,\n \t\t\t\t (volatile uint32_t *)&wqes[idx],\n@@ -590,13 +591,14 @@ mlx5_compress_dequeue_burst(void *queue_pair, struct rte_comp_op **ops,\n \tstruct mlx5_compress_qp *qp = queue_pair;\n \tvolatile struct mlx5_compress_xform *restrict xform;\n \tvolatile struct mlx5_cqe *restrict cqe;\n-\tvolatile struct mlx5_gga_compress_opaque *opaq = qp->opaque_mr.addr;\n+\tvolatile union mlx5_gga_compress_opaque *opaq = qp->opaque_mr.addr;\n \tstruct rte_comp_op *restrict op;\n \tconst unsigned int cq_size = qp->entries_n;\n \tconst unsigned int mask = cq_size - 1;\n \tuint32_t idx;\n \tuint32_t next_idx = qp->ci & mask;\n \tconst uint16_t max = RTE_MIN((uint16_t)(qp->pi - qp->ci), nb_ops);\n+\tuint32_t crc32_idx = qp->priv->crc32_opaq_offs;\n \tuint16_t i = 0;\n \tint ret;\n \n@@ -629,17 +631,17 @@ mlx5_compress_dequeue_burst(void *queue_pair, struct rte_comp_op **ops,\n \t\t\tswitch (xform->csum_type) {\n \t\t\tcase RTE_COMP_CHECKSUM_CRC32:\n \t\t\t\top->output_chksum = (uint64_t)rte_be_to_cpu_32\n-\t\t\t\t\t\t (opaq[idx].crc32);\n+\t\t\t\t\t\t (opaq[idx].data[crc32_idx]);\n \t\t\t\tbreak;\n \t\t\tcase RTE_COMP_CHECKSUM_ADLER32:\n \t\t\t\top->output_chksum = (uint64_t)rte_be_to_cpu_32\n-\t\t\t\t\t\t (opaq[idx].adler32);\n+\t\t\t\t\t\t(opaq[idx].data[crc32_idx + 1]);\n \t\t\t\tbreak;\n \t\t\tcase RTE_COMP_CHECKSUM_CRC32_ADLER32:\n \t\t\t\top->output_chksum = (uint64_t)rte_be_to_cpu_32\n-\t\t\t\t\t\t\t (opaq[idx].crc32) |\n+\t\t\t\t\t\t (opaq[idx].data[crc32_idx]) |\n \t\t\t\t\t\t ((uint64_t)rte_be_to_cpu_32\n-\t\t\t\t\t\t (opaq[idx].adler32) << 32);\n+\t\t\t\t\t (opaq[idx].data[crc32_idx + 1]) << 32);\n \t\t\t\tbreak;\n \t\t\tdefault:\n \t\t\t\tbreak;\n@@ -717,15 +719,17 @@ mlx5_compress_dev_probe(struct mlx5_common_device *cdev,\n \t\t.socket_id = cdev->dev->numa_node,\n \t};\n \tconst char *ibdev_name = mlx5_os_get_ctx_device_name(cdev->ctx);\n+\tuint32_t crc32_opaq_offset;\n \n \tif (rte_eal_process_type() != RTE_PROC_PRIMARY) {\n \t\tDRV_LOG(ERR, \"Non-primary process type is not supported.\");\n \t\trte_errno = ENOTSUP;\n \t\treturn -rte_errno;\n \t}\n-\tif (!attr->mmo_decompress_qp_en && !attr->mmo_decompress_sq_en\n-\t\t&& !attr->mmo_compress_qp_en && !attr->mmo_compress_sq_en\n-\t\t&& !attr->mmo_dma_qp_en && !attr->mmo_dma_sq_en) {\n+\tif (!attr->decomp_deflate_v1_en && !attr->decomp_deflate_v2_en &&\n+\t !attr->mmo_decompress_sq_en && !attr->mmo_compress_qp_en &&\n+\t !attr->mmo_compress_sq_en && !attr->mmo_dma_qp_en &&\n+\t !attr->mmo_dma_sq_en) {\n \t\tDRV_LOG(ERR, \"Not enough capabilities to support compress operations, maybe old FW/OFED version?\");\n \t\trte_errno = ENOTSUP;\n \t\treturn -ENOTSUP;\n@@ -746,11 +750,20 @@ mlx5_compress_dev_probe(struct mlx5_common_device *cdev,\n \tpriv = compressdev->data->dev_private;\n \tpriv->log_block_sz = devarg_prms.log_block_sz;\n \tpriv->mmo_decomp_sq = attr->mmo_decompress_sq_en;\n-\tpriv->mmo_decomp_qp = attr->mmo_decompress_qp_en;\n+\tpriv->mmo_decomp_qp =\n+\t\t\tattr->decomp_deflate_v1_en | attr->decomp_deflate_v2_en;\n \tpriv->mmo_comp_sq = attr->mmo_compress_sq_en;\n \tpriv->mmo_comp_qp = attr->mmo_compress_qp_en;\n \tpriv->mmo_dma_sq = attr->mmo_dma_sq_en;\n \tpriv->mmo_dma_qp = attr->mmo_dma_qp_en;\n+\tif (attr->decomp_deflate_v2_en)\n+\t\tcrc32_opaq_offset = offsetof(union mlx5_gga_compress_opaque,\n+\t\t\t\t\t v2.crc32);\n+\telse\n+\t\tcrc32_opaq_offset = offsetof(union mlx5_gga_compress_opaque,\n+\t\t\t\t\t v1.crc32);\n+\tMLX5_ASSERT((crc32_opaq_offset % 4) == 0);\n+\tpriv->crc32_opaq_offs = crc32_opaq_offset / 4;\n \tpriv->cdev = cdev;\n \tpriv->compressdev = compressdev;\n \tpriv->min_block_size = attr->compress_min_block_size;\n", "prefixes": [ "v2", "4/8" ] }