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GET /api/patches/122953/?format=api
{ "id": 122953, "url": "http://patches.dpdk.org/api/patches/122953/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20230202124951.2915770-3-tduszynski@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20230202124951.2915770-3-tduszynski@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20230202124951.2915770-3-tduszynski@marvell.com", "date": "2023-02-02T12:49:49", "name": "[v9,2/4] pmu: support reading ARM PMU events in runtime", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "8104af5b56d0907c403d39ae0ddc9e552cec05a3", "submitter": { "id": 2215, "url": "http://patches.dpdk.org/api/people/2215/?format=api", "name": "Tomasz Duszynski", "email": "tduszynski@marvell.com" }, "delegate": { "id": 24651, "url": "http://patches.dpdk.org/api/users/24651/?format=api", "username": "dmarchand", "first_name": "David", "last_name": "Marchand", "email": "david.marchand@redhat.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20230202124951.2915770-3-tduszynski@marvell.com/mbox/", "series": [ { "id": 26761, "url": "http://patches.dpdk.org/api/series/26761/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=26761", "date": "2023-02-02T12:49:47", "name": "add support for self monitoring", "version": 9, "mbox": "http://patches.dpdk.org/series/26761/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/122953/comments/", "check": "warning", "checks": "http://patches.dpdk.org/api/patches/122953/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 51F9341BAE;\n\tThu, 2 Feb 2023 13:50:17 +0100 (CET)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 8714E42FB6;\n\tThu, 2 Feb 2023 13:50:11 +0100 (CET)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n [67.231.156.173])\n by mails.dpdk.org (Postfix) with ESMTP id 03EE040689\n for <dev@dpdk.org>; Thu, 2 Feb 2023 13:50:07 +0100 (CET)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n by mx0b-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id\n 3127GW79007589; Thu, 2 Feb 2023 04:50:06 -0800", "from dc5-exch02.marvell.com ([199.233.59.182])\n by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3nfjrj832q-2\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT);\n Thu, 02 Feb 2023 04:50:05 -0800", "from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.42;\n Thu, 2 Feb 2023 04:50:04 -0800", "from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.42 via Frontend\n Transport; Thu, 2 Feb 2023 04:50:04 -0800", "from cavium-DT10.. (unknown [10.28.34.39])\n by maili.marvell.com (Postfix) with ESMTP id 6CDD75B6931;\n Thu, 2 Feb 2023 04:50:01 -0800 (PST)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-type : content-transfer-encoding; s=pfpt0220;\n bh=Cp1lVwMbd5oxrNrXOXoisHQCT8RuRKgYFKz4rv66aSc=;\n b=J99+P+/XU81CVKOR4sA2LM3gFRqst5lnn0tSlPsgfe5VJFwaVuLkzRRpNJgq5PKtKEmY\n 0hvw6xPLSZCstglacj05g4CZ2jmY8yVtrjx46Tzgo4cJJwDOmXy1x8UuZnEXfPGY8lJe\n IaHChyhesUlB7e+UGTTu8iBxaq2wl2fyVIAG1eEVsPTbWelKlToLCcQd5Aqa4s0HXERl\n T7fuq/+uv/lM/0zERaHDvE8mN41V9dIQWAlHaB3lFCI7lgcvvnhZoWO0QPcJ0xL+0nVo\n WMRJJRSySbk62KMt/kPiFgelNWMcKnF5LxyTcWHCWZiJkYLBTOq6SIkRe0MYJVE9OxTZ qg==", "From": "Tomasz Duszynski <tduszynski@marvell.com>", "To": "<dev@dpdk.org>, Tomasz Duszynski <tduszynski@marvell.com>, Ruifeng Wang\n <ruifeng.wang@arm.com>", "CC": "<roretzla@linux.microsoft.com>, <Ruifeng.Wang@arm.com>,\n <bruce.richardson@intel.com>, <jerinj@marvell.com>,\n <mattias.ronnblom@ericsson.com>, <mb@smartsharesystems.com>,\n <thomas@monjalon.net>, <zhoumin@loongson.cn>", "Subject": "[PATCH v9 2/4] pmu: support reading ARM PMU events in runtime", "Date": "Thu, 2 Feb 2023 13:49:49 +0100", "Message-ID": "<20230202124951.2915770-3-tduszynski@marvell.com>", "X-Mailer": "git-send-email 2.34.1", "In-Reply-To": "<20230202124951.2915770-1-tduszynski@marvell.com>", "References": "<20230202094358.2838758-1-tduszynski@marvell.com>\n <20230202124951.2915770-1-tduszynski@marvell.com>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"UTF-8\"", "Content-Transfer-Encoding": "8bit", "X-Proofpoint-ORIG-GUID": "TjOABKCEvoIXTCgGUu9nhbZ8i0MDVEcs", "X-Proofpoint-GUID": "TjOABKCEvoIXTCgGUu9nhbZ8i0MDVEcs", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.219,Aquarius:18.0.930,Hydra:6.0.562,FMLib:17.11.122.1\n definitions=2023-02-02_04,2023-02-02_01,2022-06-22_01", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Add support for reading ARM PMU events in runtime.\n\nSigned-off-by: Tomasz Duszynski <tduszynski@marvell.com>\nAcked-by: Morten Brørup <mb@smartsharesystems.com>\n---\n app/test/test_pmu.c | 4 ++\n lib/pmu/meson.build | 7 +++\n lib/pmu/pmu_arm64.c | 94 +++++++++++++++++++++++++++++++++++++\n lib/pmu/rte_pmu.h | 4 ++\n lib/pmu/rte_pmu_pmc_arm64.h | 30 ++++++++++++\n 5 files changed, 139 insertions(+)\n create mode 100644 lib/pmu/pmu_arm64.c\n create mode 100644 lib/pmu/rte_pmu_pmc_arm64.h", "diff": "diff --git a/app/test/test_pmu.c b/app/test/test_pmu.c\nindex a9bfb1a427..623e04b691 100644\n--- a/app/test/test_pmu.c\n+++ b/app/test/test_pmu.c\n@@ -26,6 +26,10 @@ test_pmu_read(void)\n \tif (rte_pmu_init() < 0)\n \t\treturn TEST_FAILED;\n \n+#if defined(RTE_ARCH_ARM64)\n+\tevent = rte_pmu_add_event(\"cpu_cycles\");\n+#endif\n+\n \twhile (tries--)\n \t\tval += rte_pmu_read(event);\n \ndiff --git a/lib/pmu/meson.build b/lib/pmu/meson.build\nindex a4160b494e..e857681137 100644\n--- a/lib/pmu/meson.build\n+++ b/lib/pmu/meson.build\n@@ -11,3 +11,10 @@ includes = [global_inc]\n \n sources = files('rte_pmu.c')\n headers = files('rte_pmu.h')\n+indirect_headers += files(\n+ 'rte_pmu_pmc_arm64.h',\n+)\n+\n+if dpdk_conf.has('RTE_ARCH_ARM64')\n+ sources += files('pmu_arm64.c')\n+endif\ndiff --git a/lib/pmu/pmu_arm64.c b/lib/pmu/pmu_arm64.c\nnew file mode 100644\nindex 0000000000..9e15727948\n--- /dev/null\n+++ b/lib/pmu/pmu_arm64.c\n@@ -0,0 +1,94 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2023 Marvell International Ltd.\n+ */\n+\n+#include <errno.h>\n+#include <fcntl.h>\n+#include <stdlib.h>\n+#include <unistd.h>\n+\n+#include <rte_bitops.h>\n+#include <rte_common.h>\n+\n+#include \"pmu_private.h\"\n+\n+#define PERF_USER_ACCESS_PATH \"/proc/sys/kernel/perf_user_access\"\n+\n+static int restore_uaccess;\n+\n+static int\n+read_attr_int(const char *path, int *val)\n+{\n+\tchar buf[BUFSIZ];\n+\tint ret, fd;\n+\n+\tfd = open(path, O_RDONLY);\n+\tif (fd == -1)\n+\t\treturn -errno;\n+\n+\tret = read(fd, buf, sizeof(buf));\n+\tif (ret == -1) {\n+\t\tclose(fd);\n+\n+\t\treturn -errno;\n+\t}\n+\n+\t*val = strtol(buf, NULL, 10);\n+\tclose(fd);\n+\n+\treturn 0;\n+}\n+\n+static int\n+write_attr_int(const char *path, int val)\n+{\n+\tchar buf[BUFSIZ];\n+\tint num, ret, fd;\n+\n+\tfd = open(path, O_WRONLY);\n+\tif (fd == -1)\n+\t\treturn -errno;\n+\n+\tnum = snprintf(buf, sizeof(buf), \"%d\", val);\n+\tret = write(fd, buf, num);\n+\tif (ret == -1) {\n+\t\tclose(fd);\n+\n+\t\treturn -errno;\n+\t}\n+\n+\tclose(fd);\n+\n+\treturn 0;\n+}\n+\n+int\n+pmu_arch_init(void)\n+{\n+\tint ret;\n+\n+\tret = read_attr_int(PERF_USER_ACCESS_PATH, &restore_uaccess);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\t/* user access already enabled */\n+\tif (restore_uaccess == 1)\n+\t\treturn 0;\n+\n+\treturn write_attr_int(PERF_USER_ACCESS_PATH, 1);\n+}\n+\n+void\n+pmu_arch_fini(void)\n+{\n+\twrite_attr_int(PERF_USER_ACCESS_PATH, restore_uaccess);\n+}\n+\n+void\n+pmu_arch_fixup_config(uint64_t config[3])\n+{\n+\t/* select 64 bit counters */\n+\tconfig[1] |= RTE_BIT64(0);\n+\t/* enable userspace access */\n+\tconfig[1] |= RTE_BIT64(1);\n+}\ndiff --git a/lib/pmu/rte_pmu.h b/lib/pmu/rte_pmu.h\nindex e360375a0c..b18938dab1 100644\n--- a/lib/pmu/rte_pmu.h\n+++ b/lib/pmu/rte_pmu.h\n@@ -26,6 +26,10 @@ extern \"C\" {\n #include <rte_compat.h>\n #include <rte_spinlock.h>\n \n+#if defined(RTE_ARCH_ARM64)\n+#include \"rte_pmu_pmc_arm64.h\"\n+#endif\n+\n /** Maximum number of events in a group */\n #define MAX_NUM_GROUP_EVENTS 8\n \ndiff --git a/lib/pmu/rte_pmu_pmc_arm64.h b/lib/pmu/rte_pmu_pmc_arm64.h\nnew file mode 100644\nindex 0000000000..10648f0c5f\n--- /dev/null\n+++ b/lib/pmu/rte_pmu_pmc_arm64.h\n@@ -0,0 +1,30 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2023 Marvell.\n+ */\n+#ifndef _RTE_PMU_PMC_ARM64_H_\n+#define _RTE_PMU_PMC_ARM64_H_\n+\n+#include <rte_common.h>\n+\n+static __rte_always_inline uint64_t\n+rte_pmu_pmc_read(int index)\n+{\n+\tuint64_t val;\n+\n+\tif (index == 31) {\n+\t\t/* CPU Cycles (0x11) must be read via pmccntr_el0 */\n+\t\tasm volatile(\"mrs %0, pmccntr_el0\" : \"=r\" (val));\n+\t} else {\n+\t\tasm volatile(\n+\t\t\t\"msr pmselr_el0, %x0\\n\"\n+\t\t\t\"mrs %0, pmxevcntr_el0\\n\"\n+\t\t\t: \"=r\" (val)\n+\t\t\t: \"rZ\" (index)\n+\t\t);\n+\t}\n+\n+\treturn val;\n+}\n+#define rte_pmu_pmc_read rte_pmu_pmc_read\n+\n+#endif /* _RTE_PMU_PMC_ARM64_H_ */\n", "prefixes": [ "v9", "2/4" ] }