Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/122844/?format=api
{ "id": 122844, "url": "http://patches.dpdk.org/api/patches/122844/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20230201092310.23252-38-syalavarthi@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20230201092310.23252-38-syalavarthi@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20230201092310.23252-38-syalavarthi@marvell.com", "date": "2023-02-01T09:23:08", "name": "[v4,37/39] ml/cnxk: add support to select poll memory region", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "9c3c35f5a09f3b5f816b2b91573c34cd542ccc90", "submitter": { "id": 2480, "url": "http://patches.dpdk.org/api/people/2480/?format=api", "name": "Srikanth Yalavarthi", "email": "syalavarthi@marvell.com" }, "delegate": { "id": 1, "url": "http://patches.dpdk.org/api/users/1/?format=api", "username": "tmonjalo", "first_name": "Thomas", "last_name": "Monjalon", "email": "thomas@monjalon.net" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20230201092310.23252-38-syalavarthi@marvell.com/mbox/", "series": [ { "id": 26732, "url": "http://patches.dpdk.org/api/series/26732/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=26732", "date": "2023-02-01T09:22:31", "name": "Implementation of ML CNXK driver", "version": 4, "mbox": "http://patches.dpdk.org/series/26732/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/122844/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/122844/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 9D37341B9D;\n\tWed, 1 Feb 2023 10:27:05 +0100 (CET)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 7D3904302A;\n\tWed, 1 Feb 2023 10:24:00 +0100 (CET)", "from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com\n [67.231.148.174])\n by mails.dpdk.org (Postfix) with ESMTP id A005D42D81\n for <dev@dpdk.org>; Wed, 1 Feb 2023 10:23:27 +0100 (CET)", "from pps.filterd (m0045849.ppops.net [127.0.0.1])\n by mx0a-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id\n 3116LbgY026195 for <dev@dpdk.org>; Wed, 1 Feb 2023 01:23:26 -0800", "from dc5-exch01.marvell.com ([199.233.59.181])\n by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3nfjr8rgv8-3\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Wed, 01 Feb 2023 01:23:26 -0800", "from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.42;\n Wed, 1 Feb 2023 01:23:25 -0800", "from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.42 via Frontend\n Transport; Wed, 1 Feb 2023 01:23:24 -0800", "from ml-host-33.caveonetworks.com (unknown [10.110.143.233])\n by maili.marvell.com (Postfix) with ESMTP id 645EB3F704E;\n Wed, 1 Feb 2023 01:23:24 -0800 (PST)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-type; s=pfpt0220; bh=lnFuOOA+WhV94CTV99/O4YjNJ7XfhL6nNm3Mtt8ZFyE=;\n b=TPZU9Xv1H9zYWf4Bpz1hq0J4NDZbWYDwR/dWVd/JnM02exCd9k/Uvk0cBJt2Yipg3CQ2\n 75lbqAKYsMOX3fbiKEd69s8IV9RewI9PrL7/h928UQwh2L08Mv0q3DgbRu431aKAJz9L\n f9MAb5cnOihZdE3/c3f/P1wMp6Sjb7fEsCz10XmVNtzsnQx20CUdtg4a5wMQhRFBb6rp\n Nqylbp/Cq/Snvs01m2pm/VuKqkmnNMQN6+2QjjIZbRw5UHQtaSXX+2FZBWE5pIThHG0M\n vyiATR9WRghUh+ZR4fCNrfhoZETNQ9KIh61ZD/UPGyyDYAMNdRsaP80y+ahYHEK/zjLj mA==", "From": "Srikanth Yalavarthi <syalavarthi@marvell.com>", "To": "Srikanth Yalavarthi <syalavarthi@marvell.com>", "CC": "<dev@dpdk.org>, <sshankarnara@marvell.com>, <jerinj@marvell.com>,\n <aprabhu@marvell.com>", "Subject": "[PATCH v4 37/39] ml/cnxk: add support to select poll memory region", "Date": "Wed, 1 Feb 2023 01:23:08 -0800", "Message-ID": "<20230201092310.23252-38-syalavarthi@marvell.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": "<20230201092310.23252-1-syalavarthi@marvell.com>", "References": "<20221208200220.20267-1-syalavarthi@marvell.com>\n <20230201092310.23252-1-syalavarthi@marvell.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Proofpoint-GUID": "g5mnRPC-qSVN9ThLk0B0bzjgpJGnwdSI", "X-Proofpoint-ORIG-GUID": "g5mnRPC-qSVN9ThLk0B0bzjgpJGnwdSI", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.219,Aquarius:18.0.930,Hydra:6.0.562,FMLib:17.11.122.1\n definitions=2023-02-01_03,2023-01-31_01,2022-06-22_01", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Added device argument \"poll_mem\" to select the memory\nregion to be used for polling in fast-path requests.\n\nImplemented support to use scratch registers for polling.\nAvailable pool of scratch registers one-to-one mapped with\nthe internal request queue.\n\npoll_mem:\nddr: Use DDR memory location for polling (default)\nregister: Use scratch registers polling\n\nSigned-off-by: Srikanth Yalavarthi <syalavarthi@marvell.com>\n---\n drivers/ml/cnxk/cn10k_ml_dev.c | 47 +++++++++++--\n drivers/ml/cnxk/cn10k_ml_dev.h | 24 +++++++\n drivers/ml/cnxk/cn10k_ml_ops.c | 124 +++++++++++++++++++++++++++++++--\n drivers/ml/cnxk/cn10k_ml_ops.h | 9 +++\n 4 files changed, 192 insertions(+), 12 deletions(-)", "diff": "diff --git a/drivers/ml/cnxk/cn10k_ml_dev.c b/drivers/ml/cnxk/cn10k_ml_dev.c\nindex aa503b2691..a746a66849 100644\n--- a/drivers/ml/cnxk/cn10k_ml_dev.c\n+++ b/drivers/ml/cnxk/cn10k_ml_dev.c\n@@ -23,6 +23,7 @@\n #define CN10K_ML_DEV_CACHE_MODEL_DATA\t\"cache_model_data\"\n #define CN10K_ML_OCM_ALLOC_MODE\t\t\"ocm_alloc_mode\"\n #define CN10K_ML_DEV_HW_QUEUE_LOCK\t\"hw_queue_lock\"\n+#define CN10K_ML_FW_POLL_MEM\t\t\"poll_mem\"\n \n #define CN10K_ML_FW_PATH_DEFAULT\t\t\"/lib/firmware/mlip-fw.bin\"\n #define CN10K_ML_FW_ENABLE_DPE_WARNINGS_DEFAULT 1\n@@ -30,6 +31,7 @@\n #define CN10K_ML_DEV_CACHE_MODEL_DATA_DEFAULT\t1\n #define CN10K_ML_OCM_ALLOC_MODE_DEFAULT\t\t\"lowest\"\n #define CN10K_ML_DEV_HW_QUEUE_LOCK_DEFAULT\t1\n+#define CN10K_ML_FW_POLL_MEM_DEFAULT\t\t\"ddr\"\n \n /* ML firmware macros */\n #define FW_MEMZONE_NAME\t\t \"ml_cn10k_fw_mz\"\n@@ -42,6 +44,7 @@\n /* Firmware flags */\n #define FW_ENABLE_DPE_WARNING_BITMASK BIT(0)\n #define FW_REPORT_DPE_WARNING_BITMASK BIT(1)\n+#define FW_USE_DDR_POLL_ADDR_FP\t BIT(2)\n \n static const char *const valid_args[] = {CN10K_ML_FW_PATH,\n \t\t\t\t\t CN10K_ML_FW_ENABLE_DPE_WARNINGS,\n@@ -49,6 +52,7 @@ static const char *const valid_args[] = {CN10K_ML_FW_PATH,\n \t\t\t\t\t CN10K_ML_DEV_CACHE_MODEL_DATA,\n \t\t\t\t\t CN10K_ML_OCM_ALLOC_MODE,\n \t\t\t\t\t CN10K_ML_DEV_HW_QUEUE_LOCK,\n+\t\t\t\t\t CN10K_ML_FW_POLL_MEM,\n \t\t\t\t\t NULL};\n \n /* Dummy operations for ML device */\n@@ -92,7 +96,9 @@ cn10k_mldev_parse_devargs(struct rte_devargs *devargs, struct cn10k_ml_dev *mlde\n \tbool ocm_alloc_mode_set = false;\n \tbool hw_queue_lock_set = false;\n \tchar *ocm_alloc_mode = NULL;\n+\tbool poll_mem_set = false;\n \tbool fw_path_set = false;\n+\tchar *poll_mem = NULL;\n \tchar *fw_path = NULL;\n \tint ret = 0;\n \n@@ -174,6 +180,17 @@ cn10k_mldev_parse_devargs(struct rte_devargs *devargs, struct cn10k_ml_dev *mlde\n \t\thw_queue_lock_set = true;\n \t}\n \n+\tif (rte_kvargs_count(kvlist, CN10K_ML_FW_POLL_MEM) == 1) {\n+\t\tret = rte_kvargs_process(kvlist, CN10K_ML_FW_POLL_MEM, &parse_string_arg,\n+\t\t\t\t\t &poll_mem);\n+\t\tif (ret < 0) {\n+\t\t\tplt_err(\"Error processing arguments, key = %s\\n\", CN10K_ML_FW_POLL_MEM);\n+\t\t\tret = -EINVAL;\n+\t\t\tgoto exit;\n+\t\t}\n+\t\tpoll_mem_set = true;\n+\t}\n+\n check_args:\n \tif (!fw_path_set)\n \t\tmldev->fw.path = CN10K_ML_FW_PATH_DEFAULT;\n@@ -243,6 +260,18 @@ cn10k_mldev_parse_devargs(struct rte_devargs *devargs, struct cn10k_ml_dev *mlde\n \t}\n \tplt_info(\"ML: %s = %d\", CN10K_ML_DEV_HW_QUEUE_LOCK, mldev->hw_queue_lock);\n \n+\tif (!poll_mem_set) {\n+\t\tmldev->fw.poll_mem = CN10K_ML_FW_POLL_MEM_DEFAULT;\n+\t} else {\n+\t\tif (!((strcmp(poll_mem, \"ddr\") == 0) || (strcmp(poll_mem, \"register\") == 0))) {\n+\t\t\tplt_err(\"Invalid argument, %s = %s\\n\", CN10K_ML_FW_POLL_MEM, poll_mem);\n+\t\t\tret = -EINVAL;\n+\t\t\tgoto exit;\n+\t\t}\n+\t\tmldev->fw.poll_mem = poll_mem;\n+\t}\n+\tplt_info(\"ML: %s = %s\", CN10K_ML_FW_POLL_MEM, mldev->fw.poll_mem);\n+\n exit:\n \tif (kvlist)\n \t\trte_kvargs_free(kvlist);\n@@ -376,6 +405,11 @@ cn10k_ml_fw_flags_get(struct cn10k_ml_fw *fw)\n \tif (fw->report_dpe_warnings)\n \t\tflags = flags | FW_REPORT_DPE_WARNING_BITMASK;\n \n+\tif (strcmp(fw->poll_mem, \"ddr\") == 0)\n+\t\tflags = flags | FW_USE_DDR_POLL_ADDR_FP;\n+\telse if (strcmp(fw->poll_mem, \"register\") == 0)\n+\t\tflags = flags & ~FW_USE_DDR_POLL_ADDR_FP;\n+\n \treturn flags;\n }\n \n@@ -780,9 +814,10 @@ RTE_PMD_REGISTER_PCI(MLDEV_NAME_CN10K_PMD, cn10k_mldev_pmd);\n RTE_PMD_REGISTER_PCI_TABLE(MLDEV_NAME_CN10K_PMD, pci_id_ml_table);\n RTE_PMD_REGISTER_KMOD_DEP(MLDEV_NAME_CN10K_PMD, \"vfio-pci\");\n \n-RTE_PMD_REGISTER_PARAM_STRING(MLDEV_NAME_CN10K_PMD, CN10K_ML_FW_PATH\n-\t\t\t \"=<path>\" CN10K_ML_FW_ENABLE_DPE_WARNINGS\n-\t\t\t \"=<0|1>\" CN10K_ML_FW_REPORT_DPE_WARNINGS\n-\t\t\t \"=<0|1>\" CN10K_ML_DEV_CACHE_MODEL_DATA\n-\t\t\t \"=<0|1>\" CN10K_ML_OCM_ALLOC_MODE\n-\t\t\t \"=<lowest|largest>\" CN10K_ML_DEV_HW_QUEUE_LOCK \"=<0|1>\");\n+RTE_PMD_REGISTER_PARAM_STRING(MLDEV_NAME_CN10K_PMD,\n+\t\t\t CN10K_ML_FW_PATH \"=<path>\" CN10K_ML_FW_ENABLE_DPE_WARNINGS\n+\t\t\t\t\t \"=<0|1>\" CN10K_ML_FW_REPORT_DPE_WARNINGS\n+\t\t\t\t\t \"=<0|1>\" CN10K_ML_DEV_CACHE_MODEL_DATA\n+\t\t\t\t\t \"=<0|1>\" CN10K_ML_OCM_ALLOC_MODE\n+\t\t\t\t\t \"=<lowest|largest>\" CN10K_ML_DEV_HW_QUEUE_LOCK\n+\t\t\t\t\t \"=<0|1>\" CN10K_ML_FW_POLL_MEM \"=<ddr|register>\");\ndiff --git a/drivers/ml/cnxk/cn10k_ml_dev.h b/drivers/ml/cnxk/cn10k_ml_dev.h\nindex 49676ac9e7..966d92e027 100644\n--- a/drivers/ml/cnxk/cn10k_ml_dev.h\n+++ b/drivers/ml/cnxk/cn10k_ml_dev.h\n@@ -43,6 +43,18 @@\n #define ML_CN10K_POLL_JOB_START\t 0\n #define ML_CN10K_POLL_JOB_FINISH 1\n \n+/* Memory barrier macros */\n+#if defined(RTE_ARCH_ARM)\n+#define dmb_st ({ asm volatile(\"dmb st\" : : : \"memory\"); })\n+#define dsb_st ({ asm volatile(\"dsb st\" : : : \"memory\"); })\n+#else\n+#define dmb_st\n+#define dsb_st\n+#endif\n+\n+struct cn10k_ml_req;\n+struct cn10k_ml_qp;\n+\n /* Job types */\n enum cn10k_ml_job_type {\n \tML_CN10K_JOB_TYPE_MODEL_RUN = 0,\n@@ -358,6 +370,9 @@ struct cn10k_ml_fw {\n \t/* Report DPE warnings */\n \tint report_dpe_warnings;\n \n+\t/* Memory to be used for polling in fast-path requests */\n+\tconst char *poll_mem;\n+\n \t/* Data buffer */\n \tuint8_t *data;\n \n@@ -393,6 +408,15 @@ struct cn10k_ml_dev {\n \n \t/* JCMD enqueue function handler */\n \tbool (*ml_jcmdq_enqueue)(struct roc_ml *roc_ml, struct ml_job_cmd_s *job_cmd);\n+\n+\t/* Poll handling function pointers */\n+\tvoid (*set_poll_addr)(struct cn10k_ml_qp *qp, struct cn10k_ml_req *req, uint64_t idx);\n+\tvoid (*set_poll_ptr)(struct roc_ml *roc_ml, struct cn10k_ml_req *req);\n+\tuint64_t (*get_poll_ptr)(struct roc_ml *roc_ml, struct cn10k_ml_req *req);\n+\n+\t/* Memory barrier function pointers to handle synchronization */\n+\tvoid (*set_enq_barrier)(void);\n+\tvoid (*set_deq_barrier)(void);\n };\n \n uint64_t cn10k_ml_fw_flags_get(struct cn10k_ml_fw *fw);\ndiff --git a/drivers/ml/cnxk/cn10k_ml_ops.c b/drivers/ml/cnxk/cn10k_ml_ops.c\nindex 3c96db4514..947f6a6490 100644\n--- a/drivers/ml/cnxk/cn10k_ml_ops.c\n+++ b/drivers/ml/cnxk/cn10k_ml_ops.c\n@@ -23,6 +23,11 @@\n #define ML_FLAGS_POLL_COMPL BIT(0)\n #define ML_FLAGS_SSO_COMPL BIT(1)\n \n+/* Scratch register range for poll mode requests */\n+#define ML_POLL_REGISTER_SYNC 1023\n+#define ML_POLL_REGISTER_START 1024\n+#define ML_POLL_REGISTER_END 2047\n+\n /* Error message length */\n #define ERRMSG_LEN 32\n \n@@ -76,6 +81,80 @@ print_line(FILE *fp, int len)\n \tfprintf(fp, \"\\n\");\n }\n \n+static inline void\n+cn10k_ml_set_poll_addr_ddr(struct cn10k_ml_qp *qp, struct cn10k_ml_req *req, uint64_t idx)\n+{\n+\tPLT_SET_USED(qp);\n+\tPLT_SET_USED(idx);\n+\n+\treq->compl_W1 = PLT_U64_CAST(&req->status);\n+}\n+\n+static inline void\n+cn10k_ml_set_poll_addr_reg(struct cn10k_ml_qp *qp, struct cn10k_ml_req *req, uint64_t idx)\n+{\n+\treq->compl_W1 = ML_SCRATCH(qp->block_start + idx % qp->block_size);\n+}\n+\n+static inline void\n+cn10k_ml_set_poll_ptr_ddr(struct roc_ml *roc_ml, struct cn10k_ml_req *req)\n+{\n+\tPLT_SET_USED(roc_ml);\n+\n+\tplt_write64(ML_CN10K_POLL_JOB_START, req->compl_W1);\n+}\n+\n+static inline void\n+cn10k_ml_set_poll_ptr_reg(struct roc_ml *roc_ml, struct cn10k_ml_req *req)\n+{\n+\troc_ml_reg_write64(roc_ml, ML_CN10K_POLL_JOB_START, req->compl_W1);\n+}\n+\n+static inline uint64_t\n+cn10k_ml_get_poll_ptr_ddr(struct roc_ml *roc_ml, struct cn10k_ml_req *req)\n+{\n+\tPLT_SET_USED(roc_ml);\n+\n+\treturn plt_read64(req->compl_W1);\n+}\n+\n+static inline uint64_t\n+cn10k_ml_get_poll_ptr_reg(struct roc_ml *roc_ml, struct cn10k_ml_req *req)\n+{\n+\treturn roc_ml_reg_read64(roc_ml, req->compl_W1);\n+}\n+\n+static inline void\n+cn10k_ml_set_sync_addr(struct cn10k_ml_dev *mldev, struct cn10k_ml_req *req)\n+{\n+\tif (strcmp(mldev->fw.poll_mem, \"ddr\") == 0)\n+\t\treq->compl_W1 = PLT_U64_CAST(&req->status);\n+\telse if (strcmp(mldev->fw.poll_mem, \"register\") == 0)\n+\t\treq->compl_W1 = ML_SCRATCH(ML_POLL_REGISTER_SYNC);\n+}\n+\n+static inline void\n+cn10k_ml_enq_barrier_ddr(void)\n+{\n+}\n+\n+static inline void\n+cn10k_ml_deq_barrier_ddr(void)\n+{\n+}\n+\n+static inline void\n+cn10k_ml_enq_barrier_register(void)\n+{\n+\tdmb_st;\n+}\n+\n+static inline void\n+cn10k_ml_deq_barrier_register(void)\n+{\n+\tdsb_st;\n+}\n+\n static void\n qp_memzone_name_get(char *name, int size, int dev_id, int qp_id)\n {\n@@ -163,6 +242,9 @@ cn10k_ml_qp_create(const struct rte_ml_dev *dev, uint16_t qp_id, uint32_t nb_des\n \tqp->stats.dequeued_count = 0;\n \tqp->stats.enqueue_err_count = 0;\n \tqp->stats.dequeue_err_count = 0;\n+\tqp->block_size =\n+\t\t(ML_POLL_REGISTER_END - ML_POLL_REGISTER_START + 1) / dev->data->nb_queue_pairs;\n+\tqp->block_start = ML_POLL_REGISTER_START + qp_id * qp->block_size;\n \n \t/* Initialize job command */\n \tfor (i = 0; i < qp->nb_desc; i++) {\n@@ -341,7 +423,7 @@ cn10k_ml_prep_fp_job_descriptor(struct rte_ml_dev *dev, struct cn10k_ml_req *req\n \tmldev = dev->data->dev_private;\n \n \treq->jd.hdr.jce.w0.u64 = 0;\n-\treq->jd.hdr.jce.w1.u64 = PLT_U64_CAST(&req->status);\n+\treq->jd.hdr.jce.w1.u64 = req->compl_W1;\n \treq->jd.hdr.model_id = op->model_id;\n \treq->jd.hdr.job_type = ML_CN10K_JOB_TYPE_MODEL_RUN;\n \treq->jd.hdr.fp_flags = ML_FLAGS_POLL_COMPL;\n@@ -549,7 +631,11 @@ cn10k_ml_dev_info_get(struct rte_ml_dev *dev, struct rte_ml_dev_info *dev_info)\n \telse\n \t\tdev_info->max_queue_pairs = ML_CN10K_MAX_QP_PER_DEVICE_LF;\n \n-\tdev_info->max_desc = ML_CN10K_MAX_DESC_PER_QP;\n+\tif (strcmp(mldev->fw.poll_mem, \"register\") == 0)\n+\t\tdev_info->max_desc = ML_CN10K_MAX_DESC_PER_QP / dev_info->max_queue_pairs;\n+\telse if (strcmp(mldev->fw.poll_mem, \"ddr\") == 0)\n+\t\tdev_info->max_desc = ML_CN10K_MAX_DESC_PER_QP;\n+\n \tdev_info->max_segments = ML_CN10K_MAX_SEGMENTS;\n \tdev_info->min_align_size = ML_CN10K_ALIGN_SIZE;\n \n@@ -717,6 +803,26 @@ cn10k_ml_dev_configure(struct rte_ml_dev *dev, const struct rte_ml_dev_config *c\n \telse\n \t\tmldev->ml_jcmdq_enqueue = roc_ml_jcmdq_enqueue_lf;\n \n+\t/* Set polling function pointers */\n+\tif (strcmp(mldev->fw.poll_mem, \"ddr\") == 0) {\n+\t\tmldev->set_poll_addr = cn10k_ml_set_poll_addr_ddr;\n+\t\tmldev->set_poll_ptr = cn10k_ml_set_poll_ptr_ddr;\n+\t\tmldev->get_poll_ptr = cn10k_ml_get_poll_ptr_ddr;\n+\t} else if (strcmp(mldev->fw.poll_mem, \"register\") == 0) {\n+\t\tmldev->set_poll_addr = cn10k_ml_set_poll_addr_reg;\n+\t\tmldev->set_poll_ptr = cn10k_ml_set_poll_ptr_reg;\n+\t\tmldev->get_poll_ptr = cn10k_ml_get_poll_ptr_reg;\n+\t}\n+\n+\t/* Set barrier function pointers */\n+\tif (strcmp(mldev->fw.poll_mem, \"ddr\") == 0) {\n+\t\tmldev->set_enq_barrier = cn10k_ml_enq_barrier_ddr;\n+\t\tmldev->set_deq_barrier = cn10k_ml_deq_barrier_ddr;\n+\t} else if (strcmp(mldev->fw.poll_mem, \"register\") == 0) {\n+\t\tmldev->set_enq_barrier = cn10k_ml_enq_barrier_register;\n+\t\tmldev->set_deq_barrier = cn10k_ml_deq_barrier_register;\n+\t}\n+\n \tdev->enqueue_burst = cn10k_ml_enqueue_burst;\n \tdev->dequeue_burst = cn10k_ml_dequeue_burst;\n \tdev->op_error_get = cn10k_ml_op_error_get;\n@@ -2000,13 +2106,15 @@ cn10k_ml_enqueue_burst(struct rte_ml_dev *dev, uint16_t qp_id, struct rte_ml_op\n \top = ops[count];\n \treq = &queue->reqs[head];\n \n+\tmldev->set_poll_addr(qp, req, head);\n \tcn10k_ml_prep_fp_job_descriptor(dev, req, op);\n \n \tmemset(&req->result, 0, sizeof(struct cn10k_ml_result));\n \treq->result.error_code.s.etype = ML_ETYPE_UNKNOWN;\n \treq->result.user_ptr = op->user_ptr;\n+\tmldev->set_enq_barrier();\n \n-\tplt_write64(ML_CN10K_POLL_JOB_START, &req->status);\n+\tmldev->set_poll_ptr(&mldev->roc, req);\n \tenqueued = mldev->ml_jcmdq_enqueue(&mldev->roc, &req->jcmd);\n \tif (unlikely(!enqueued))\n \t\tgoto jcmdq_full;\n@@ -2032,6 +2140,7 @@ cn10k_ml_dequeue_burst(struct rte_ml_dev *dev, uint16_t qp_id, struct rte_ml_op\n \t\t uint16_t nb_ops)\n {\n \tstruct cn10k_ml_queue *queue;\n+\tstruct cn10k_ml_dev *mldev;\n \tstruct cn10k_ml_req *req;\n \tstruct cn10k_ml_qp *qp;\n \n@@ -2039,6 +2148,7 @@ cn10k_ml_dequeue_burst(struct rte_ml_dev *dev, uint16_t qp_id, struct rte_ml_op\n \tuint16_t count;\n \tuint64_t tail;\n \n+\tmldev = dev->data->dev_private;\n \tqp = dev->data->queue_pairs[qp_id];\n \tqueue = &qp->queue;\n \n@@ -2051,7 +2161,7 @@ cn10k_ml_dequeue_burst(struct rte_ml_dev *dev, uint16_t qp_id, struct rte_ml_op\n \n dequeue_req:\n \treq = &queue->reqs[tail];\n-\tstatus = plt_read64(&req->status);\n+\tstatus = mldev->get_poll_ptr(&mldev->roc, req);\n \tif (unlikely(status != ML_CN10K_POLL_JOB_FINISH)) {\n \t\tif (plt_tsc_cycles() < req->timeout)\n \t\t\tgoto empty_or_active;\n@@ -2059,6 +2169,7 @@ cn10k_ml_dequeue_burst(struct rte_ml_dev *dev, uint16_t qp_id, struct rte_ml_op\n \t\t\treq->result.error_code.s.etype = ML_ETYPE_DRIVER;\n \t}\n \n+\tmldev->set_deq_barrier();\n \tcn10k_ml_result_update(dev, qp_id, &req->result, req->op);\n \tops[count] = req->op;\n \n@@ -2116,13 +2227,14 @@ cn10k_ml_inference_sync(struct rte_ml_dev *dev, struct rte_ml_op *op)\n \tmodel = dev->data->models[op->model_id];\n \treq = model->req;\n \n+\tcn10k_ml_set_sync_addr(mldev, req);\n \tcn10k_ml_prep_fp_job_descriptor(dev, req, op);\n \n \tmemset(&req->result, 0, sizeof(struct cn10k_ml_result));\n \treq->result.error_code.s.etype = ML_ETYPE_UNKNOWN;\n \treq->result.user_ptr = op->user_ptr;\n \n-\tplt_write64(ML_CN10K_POLL_JOB_START, &req->status);\n+\tmldev->set_poll_ptr(&mldev->roc, req);\n \treq->jcmd.w1.s.jobptr = PLT_U64_CAST(&req->jd);\n \n \ttimeout = true;\n@@ -2142,7 +2254,7 @@ cn10k_ml_inference_sync(struct rte_ml_dev *dev, struct rte_ml_op *op)\n \n \ttimeout = true;\n \tdo {\n-\t\tif (plt_read64(&req->status) == ML_CN10K_POLL_JOB_FINISH) {\n+\t\tif (mldev->get_poll_ptr(&mldev->roc, req) == ML_CN10K_POLL_JOB_FINISH) {\n \t\t\ttimeout = false;\n \t\t\tbreak;\n \t\t}\ndiff --git a/drivers/ml/cnxk/cn10k_ml_ops.h b/drivers/ml/cnxk/cn10k_ml_ops.h\nindex fb82af414a..995ed27e4e 100644\n--- a/drivers/ml/cnxk/cn10k_ml_ops.h\n+++ b/drivers/ml/cnxk/cn10k_ml_ops.h\n@@ -26,6 +26,9 @@ struct cn10k_ml_req {\n \t/* Job command */\n \tstruct ml_job_cmd_s jcmd;\n \n+\t/* Job completion W1 */\n+\tuint64_t compl_W1;\n+\n \t/* Timeout cycle */\n \tuint64_t timeout;\n \n@@ -61,6 +64,12 @@ struct cn10k_ml_qp {\n \n \t/* Statistics per queue-pair */\n \tstruct rte_ml_dev_stats stats;\n+\n+\t/* Register block start for polling */\n+\tuint32_t block_start;\n+\n+\t/* Register block end for polling */\n+\tuint32_t block_size;\n };\n \n /* Device ops */\n", "prefixes": [ "v4", "37/39" ] }