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GET /api/patches/122840/?format=api
{ "id": 122840, "url": "http://patches.dpdk.org/api/patches/122840/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20230201092310.23252-36-syalavarthi@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20230201092310.23252-36-syalavarthi@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20230201092310.23252-36-syalavarthi@marvell.com", "date": "2023-02-01T09:23:06", "name": "[v4,35/39] ml/cnxk: add support to select OCM allocation mode", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "c7fca08e3d3bbd46f344c81f609b157d36e62c4c", "submitter": { "id": 2480, "url": "http://patches.dpdk.org/api/people/2480/?format=api", "name": "Srikanth Yalavarthi", "email": "syalavarthi@marvell.com" }, "delegate": { "id": 1, "url": "http://patches.dpdk.org/api/users/1/?format=api", "username": "tmonjalo", "first_name": "Thomas", "last_name": "Monjalon", "email": "thomas@monjalon.net" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20230201092310.23252-36-syalavarthi@marvell.com/mbox/", "series": [ { "id": 26732, "url": "http://patches.dpdk.org/api/series/26732/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=26732", "date": "2023-02-01T09:22:31", "name": "Implementation of ML CNXK driver", "version": 4, "mbox": "http://patches.dpdk.org/series/26732/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/122840/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/122840/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 4B9E141B9D;\n\tWed, 1 Feb 2023 10:26:43 +0100 (CET)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 1830B43020;\n\tWed, 1 Feb 2023 10:23:56 +0100 (CET)", "from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com\n [67.231.148.174])\n by mails.dpdk.org (Postfix) with ESMTP id C889142D79\n for <dev@dpdk.org>; Wed, 1 Feb 2023 10:23:26 +0100 (CET)", "from pps.filterd (m0045849.ppops.net [127.0.0.1])\n by mx0a-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id\n 3116LbgW026195 for <dev@dpdk.org>; Wed, 1 Feb 2023 01:23:26 -0800", "from dc5-exch01.marvell.com ([199.233.59.181])\n by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3nfjr8rgv8-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Wed, 01 Feb 2023 01:23:25 -0800", "from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.42;\n Wed, 1 Feb 2023 01:23:24 -0800", "from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.42 via Frontend\n Transport; Wed, 1 Feb 2023 01:23:24 -0800", "from ml-host-33.caveonetworks.com (unknown [10.110.143.233])\n by maili.marvell.com (Postfix) with ESMTP id BAD7D3F704C;\n Wed, 1 Feb 2023 01:23:23 -0800 (PST)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-type; s=pfpt0220; bh=iuw0K5kQ98LVjo1ynrlqy49QHk8KKEcDbttHTy3p63A=;\n b=D1lcci5WTemfUIX1OImpxx+A3mR3jbphQGLkLxlvpDWp8we6FhiRcnL2Jd3avlVyrFJd\n m8c2ZcF+luUVxY1r+p3LNmZqcBMnn1zLbuD60dqGqfXrkGz3IudWEwaPVTnqkIN258xZ\n aV3YyPpt92YvkGwIcP0rpchY+D54Nb7rqBEZA4rMyY0oL3U4nktMLG6tS+WKq3GAJP70\n z0sbJoAn48JuymPPSG4R4Rz5ZBAfQ7WdyfZHJWE3iaoKls9occVPPapeZqwNaGHeEbnv\n glVJ2UCV9RnYSgn+D5SAHq0RSXzYAZyp5ObT/dhv7k5g2doh8Y+LpYxn5QknxDy/dtc+ IQ==", "From": "Srikanth Yalavarthi <syalavarthi@marvell.com>", "To": "Srikanth Yalavarthi <syalavarthi@marvell.com>", "CC": "<dev@dpdk.org>, <sshankarnara@marvell.com>, <jerinj@marvell.com>,\n <aprabhu@marvell.com>", "Subject": "[PATCH v4 35/39] ml/cnxk: add support to select OCM allocation mode", "Date": "Wed, 1 Feb 2023 01:23:06 -0800", "Message-ID": "<20230201092310.23252-36-syalavarthi@marvell.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": "<20230201092310.23252-1-syalavarthi@marvell.com>", "References": "<20221208200220.20267-1-syalavarthi@marvell.com>\n <20230201092310.23252-1-syalavarthi@marvell.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Proofpoint-GUID": "sKk8L9cmStkRqwVPvINhG-SfXro7E3Kz", "X-Proofpoint-ORIG-GUID": "sKk8L9cmStkRqwVPvINhG-SfXro7E3Kz", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.219,Aquarius:18.0.930,Hydra:6.0.562,FMLib:17.11.122.1\n definitions=2023-02-01_03,2023-01-31_01,2022-06-22_01", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Added device argument \"ocm_alloc_mode\" to select OCM allocation\nmethod during model start. Two modes are supported by the driver.\n\nAdded implementation for ocm_alloc_mode lowest as default.\n\nocm_alloc_mode:\nlowest: Allocate from first available free slot / lowest\n tile ID in OCM (default)\nlargest: Allocate from a slot with maximum free memory\n\nSigned-off-by: Srikanth Yalavarthi <syalavarthi@marvell.com>\n---\n drivers/ml/cnxk/cn10k_ml_dev.c | 45 +++++++++++++++++++++++++++++-----\n drivers/ml/cnxk/cn10k_ml_ocm.c | 6 ++---\n drivers/ml/cnxk/cn10k_ml_ocm.h | 3 +++\n 3 files changed, 44 insertions(+), 10 deletions(-)", "diff": "diff --git a/drivers/ml/cnxk/cn10k_ml_dev.c b/drivers/ml/cnxk/cn10k_ml_dev.c\nindex 948708a420..5c02d67c8e 100644\n--- a/drivers/ml/cnxk/cn10k_ml_dev.c\n+++ b/drivers/ml/cnxk/cn10k_ml_dev.c\n@@ -21,11 +21,13 @@\n #define CN10K_ML_FW_ENABLE_DPE_WARNINGS \"enable_dpe_warnings\"\n #define CN10K_ML_FW_REPORT_DPE_WARNINGS \"report_dpe_warnings\"\n #define CN10K_ML_DEV_CACHE_MODEL_DATA\t\"cache_model_data\"\n+#define CN10K_ML_OCM_ALLOC_MODE\t\t\"ocm_alloc_mode\"\n \n #define CN10K_ML_FW_PATH_DEFAULT\t\t\"/lib/firmware/mlip-fw.bin\"\n #define CN10K_ML_FW_ENABLE_DPE_WARNINGS_DEFAULT 1\n #define CN10K_ML_FW_REPORT_DPE_WARNINGS_DEFAULT 0\n #define CN10K_ML_DEV_CACHE_MODEL_DATA_DEFAULT\t1\n+#define CN10K_ML_OCM_ALLOC_MODE_DEFAULT\t\t\"lowest\"\n \n /* ML firmware macros */\n #define FW_MEMZONE_NAME\t\t \"ml_cn10k_fw_mz\"\n@@ -39,9 +41,12 @@\n #define FW_ENABLE_DPE_WARNING_BITMASK BIT(0)\n #define FW_REPORT_DPE_WARNING_BITMASK BIT(1)\n \n-static const char *const valid_args[] = {CN10K_ML_FW_PATH, CN10K_ML_FW_ENABLE_DPE_WARNINGS,\n+static const char *const valid_args[] = {CN10K_ML_FW_PATH,\n+\t\t\t\t\t CN10K_ML_FW_ENABLE_DPE_WARNINGS,\n \t\t\t\t\t CN10K_ML_FW_REPORT_DPE_WARNINGS,\n-\t\t\t\t\t CN10K_ML_DEV_CACHE_MODEL_DATA, NULL};\n+\t\t\t\t\t CN10K_ML_DEV_CACHE_MODEL_DATA,\n+\t\t\t\t\t CN10K_ML_OCM_ALLOC_MODE,\n+\t\t\t\t\t NULL};\n \n /* Dummy operations for ML device */\n struct rte_ml_dev_ops ml_dev_dummy_ops = {0};\n@@ -81,6 +86,8 @@ cn10k_mldev_parse_devargs(struct rte_devargs *devargs, struct cn10k_ml_dev *mlde\n \tbool report_dpe_warnings_set = false;\n \tbool cache_model_data_set = false;\n \tstruct rte_kvargs *kvlist = NULL;\n+\tbool ocm_alloc_mode_set = false;\n+\tchar *ocm_alloc_mode = NULL;\n \tbool fw_path_set = false;\n \tchar *fw_path = NULL;\n \tint ret = 0;\n@@ -140,6 +147,17 @@ cn10k_mldev_parse_devargs(struct rte_devargs *devargs, struct cn10k_ml_dev *mlde\n \t\tcache_model_data_set = true;\n \t}\n \n+\tif (rte_kvargs_count(kvlist, CN10K_ML_OCM_ALLOC_MODE) == 1) {\n+\t\tret = rte_kvargs_process(kvlist, CN10K_ML_OCM_ALLOC_MODE, &parse_string_arg,\n+\t\t\t\t\t &ocm_alloc_mode);\n+\t\tif (ret < 0) {\n+\t\t\tplt_err(\"Error processing arguments, key = %s\\n\", CN10K_ML_OCM_ALLOC_MODE);\n+\t\t\tret = -EINVAL;\n+\t\t\tgoto exit;\n+\t\t}\n+\t\tocm_alloc_mode_set = true;\n+\t}\n+\n check_args:\n \tif (!fw_path_set)\n \t\tmldev->fw.path = CN10K_ML_FW_PATH_DEFAULT;\n@@ -183,6 +201,20 @@ cn10k_mldev_parse_devargs(struct rte_devargs *devargs, struct cn10k_ml_dev *mlde\n \t}\n \tplt_info(\"ML: %s = %d\", CN10K_ML_DEV_CACHE_MODEL_DATA, mldev->cache_model_data);\n \n+\tif (!ocm_alloc_mode_set) {\n+\t\tmldev->ocm.alloc_mode = CN10K_ML_OCM_ALLOC_MODE_DEFAULT;\n+\t} else {\n+\t\tif (!((strcmp(ocm_alloc_mode, \"lowest\") == 0) ||\n+\t\t (strcmp(ocm_alloc_mode, \"largest\") == 0))) {\n+\t\t\tplt_err(\"Invalid argument, %s = %s\\n\", CN10K_ML_OCM_ALLOC_MODE,\n+\t\t\t\tocm_alloc_mode);\n+\t\t\tret = -EINVAL;\n+\t\t\tgoto exit;\n+\t\t}\n+\t\tmldev->ocm.alloc_mode = ocm_alloc_mode;\n+\t}\n+\tplt_info(\"ML: %s = %s\", CN10K_ML_OCM_ALLOC_MODE, mldev->ocm.alloc_mode);\n+\n exit:\n \tif (kvlist)\n \t\trte_kvargs_free(kvlist);\n@@ -720,7 +752,8 @@ RTE_PMD_REGISTER_PCI(MLDEV_NAME_CN10K_PMD, cn10k_mldev_pmd);\n RTE_PMD_REGISTER_PCI_TABLE(MLDEV_NAME_CN10K_PMD, pci_id_ml_table);\n RTE_PMD_REGISTER_KMOD_DEP(MLDEV_NAME_CN10K_PMD, \"vfio-pci\");\n \n-RTE_PMD_REGISTER_PARAM_STRING(MLDEV_NAME_CN10K_PMD,\n-\t\t\t CN10K_ML_FW_PATH \"=<path>\" CN10K_ML_FW_ENABLE_DPE_WARNINGS\n-\t\t\t\t\t \"=<0|1>\" CN10K_ML_FW_REPORT_DPE_WARNINGS\n-\t\t\t\t\t \"=<0|1>\" CN10K_ML_DEV_CACHE_MODEL_DATA \"=<0|1>\");\n+RTE_PMD_REGISTER_PARAM_STRING(MLDEV_NAME_CN10K_PMD, CN10K_ML_FW_PATH\n+\t\t\t \"=<path>\" CN10K_ML_FW_ENABLE_DPE_WARNINGS\n+\t\t\t \"=<0|1>\" CN10K_ML_FW_REPORT_DPE_WARNINGS\n+\t\t\t \"=<0|1>\" CN10K_ML_DEV_CACHE_MODEL_DATA\n+\t\t\t \"=<0|1>\" CN10K_ML_OCM_ALLOC_MODE \"=<lowest|largest>\");\ndiff --git a/drivers/ml/cnxk/cn10k_ml_ocm.c b/drivers/ml/cnxk/cn10k_ml_ocm.c\nindex 2083d99f81..26e356c107 100644\n--- a/drivers/ml/cnxk/cn10k_ml_ocm.c\n+++ b/drivers/ml/cnxk/cn10k_ml_ocm.c\n@@ -230,7 +230,6 @@ cn10k_ml_ocm_tilemask_find(struct rte_ml_dev *dev, uint8_t num_tiles, uint16_t w\n \tint wb_page_start_curr;\n \tint max_slot_sz_curr;\n \tuint8_t tile_start;\n-\tint ocm_alloc_mode;\n \tint wb_page_start;\n \tuint16_t tile_id;\n \tuint16_t word_id;\n@@ -255,7 +254,6 @@ cn10k_ml_ocm_tilemask_find(struct rte_ml_dev *dev, uint8_t num_tiles, uint16_t w\n \tmax_slot_sz_curr = 0;\n \tmax_slot_sz = 0;\n \ttile_idx = 0;\n-\tocm_alloc_mode = 2;\n \n \tif ((start_tile != -1) && (start_tile % num_tiles != 0)) {\n \t\tplt_err(\"Invalid start_tile, %d\", start_tile);\n@@ -303,13 +301,13 @@ cn10k_ml_ocm_tilemask_find(struct rte_ml_dev *dev, uint8_t num_tiles, uint16_t w\n \t\t}\n \t}\n \n-\tif (ocm_alloc_mode == 1) {\n+\tif (strcmp(ocm->alloc_mode, \"lowest\") == 0) {\n \t\twb_page_start = slot_index_lowest(local_ocm_mask, ocm->mask_words, wb_pages, 0);\n \t\tif (wb_page_start != -1) { /* Have a valid slot for WB, else next set of tiles */\n \t\t\ttile_idx = tile_start;\n \t\t\tgoto found;\n \t\t}\n-\t} else if (ocm_alloc_mode == 2) {\n+\t} else if (strcmp(ocm->alloc_mode, \"largest\") == 0) {\n \t\twb_page_start_curr = slot_index_largest(local_ocm_mask, ocm->mask_words, wb_pages,\n \t\t\t\t\t\t\t&max_slot_sz_curr);\n \t\tif (max_slot_sz_curr > max_slot_sz) {\ndiff --git a/drivers/ml/cnxk/cn10k_ml_ocm.h b/drivers/ml/cnxk/cn10k_ml_ocm.h\nindex 4415bbfb45..6bf71c8da6 100644\n--- a/drivers/ml/cnxk/cn10k_ml_ocm.h\n+++ b/drivers/ml/cnxk/cn10k_ml_ocm.h\n@@ -58,6 +58,9 @@ struct cn10k_ml_ocm {\n \t/* OCM spinlock, used to update OCM state */\n \trte_spinlock_t lock;\n \n+\t/* OCM allocation mode */\n+\tconst char *alloc_mode;\n+\n \t/* Number of OCM tiles */\n \tuint8_t num_tiles;\n \n", "prefixes": [ "v4", "35/39" ] }