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GET /api/patches/122835/?format=api
{ "id": 122835, "url": "http://patches.dpdk.org/api/patches/122835/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20230201092310.23252-19-syalavarthi@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20230201092310.23252-19-syalavarthi@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20230201092310.23252-19-syalavarthi@marvell.com", "date": "2023-02-01T09:22:49", "name": "[v4,18/39] ml/cnxk: enable support to start an ML model", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "6a650a80e24b52386cecf44ba8892dbc3f93a14b", "submitter": { "id": 2480, "url": "http://patches.dpdk.org/api/people/2480/?format=api", "name": "Srikanth Yalavarthi", "email": "syalavarthi@marvell.com" }, "delegate": { "id": 1, "url": "http://patches.dpdk.org/api/users/1/?format=api", "username": "tmonjalo", "first_name": "Thomas", "last_name": "Monjalon", "email": "thomas@monjalon.net" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20230201092310.23252-19-syalavarthi@marvell.com/mbox/", "series": [ { "id": 26732, "url": "http://patches.dpdk.org/api/series/26732/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=26732", "date": "2023-02-01T09:22:31", "name": "Implementation of ML CNXK driver", "version": 4, "mbox": "http://patches.dpdk.org/series/26732/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/122835/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/122835/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 2C0FC41B9D;\n\tWed, 1 Feb 2023 10:26:11 +0100 (CET)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 36FF442FDE;\n\tWed, 1 Feb 2023 10:23:49 +0100 (CET)", "from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com\n [67.231.148.174])\n by mails.dpdk.org (Postfix) with ESMTP id 4B94442D29\n for <dev@dpdk.org>; Wed, 1 Feb 2023 10:23:25 +0100 (CET)", "from pps.filterd (m0045849.ppops.net [127.0.0.1])\n by mx0a-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id\n 3116LRY7024189 for <dev@dpdk.org>; Wed, 1 Feb 2023 01:23:24 -0800", "from dc5-exch02.marvell.com ([199.233.59.182])\n by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3nfjr8rgv6-6\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Wed, 01 Feb 2023 01:23:24 -0800", "from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.42;\n Wed, 1 Feb 2023 01:23:20 -0800", "from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.42 via Frontend\n Transport; Wed, 1 Feb 2023 01:23:20 -0800", "from ml-host-33.caveonetworks.com (unknown [10.110.143.233])\n by maili.marvell.com (Postfix) with ESMTP id 846133F7041;\n Wed, 1 Feb 2023 01:23:18 -0800 (PST)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-type; s=pfpt0220; bh=HYlitpx+p6igE/AWWVGt6X4aHYyLLxtW8w7ZvQ0WXWE=;\n b=E5MGo1DpRU5pG9amMl+gR9IAcFP7PqQjr1W0pBrK1QTGlkzRhJkMHsvCkiPNNsIPP8f1\n a7vR0JACchqnLk3ssWGGhXIvxqfgM1QGASyu110GYAsCr5Kh5JZopw3Kp26RkzXNMyCj\n ssstw+Mx0lC+vueNLAi3R3byfQPZ/VmYdJBbWqRrJLzKc/f3gw+crSq8RhKMAqNXy4s3\n E0OkhcVmlK2sAIYLRO+Lbkr09icvmOB5mkHqS2tvu+0rYUDnrMbghHbcMwCRlyeSu4up\n dh+yzALFfVmb3YfqIO5s/LehRQcUGqZQJ3+LpjIC16ZPcX1R5b3VHx+PzjcmL2TrG//p kg==", "From": "Srikanth Yalavarthi <syalavarthi@marvell.com>", "To": "Srikanth Yalavarthi <syalavarthi@marvell.com>", "CC": "<dev@dpdk.org>, <sshankarnara@marvell.com>, <jerinj@marvell.com>,\n <aprabhu@marvell.com>", "Subject": "[PATCH v4 18/39] ml/cnxk: enable support to start an ML model", "Date": "Wed, 1 Feb 2023 01:22:49 -0800", "Message-ID": "<20230201092310.23252-19-syalavarthi@marvell.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": "<20230201092310.23252-1-syalavarthi@marvell.com>", "References": "<20221208200220.20267-1-syalavarthi@marvell.com>\n <20230201092310.23252-1-syalavarthi@marvell.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Proofpoint-GUID": "WP1bVhEFWGsxyTHZEGdzCwsoR_-LuWA5", "X-Proofpoint-ORIG-GUID": "WP1bVhEFWGsxyTHZEGdzCwsoR_-LuWA5", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.219,Aquarius:18.0.930,Hydra:6.0.562,FMLib:17.11.122.1\n definitions=2023-02-01_03,2023-01-31_01,2022-06-22_01", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Implemented model start driver function. A model start job\nis checked for completion in synchronous mode. Tilemask and\nOCM slot is calculated before starting the model. Model start\nis enqueued through scratch registers. OCM pages are reserved\nafter model start completion.\n\nSigned-off-by: Srikanth Yalavarthi <syalavarthi@marvell.com>\n---\n drivers/ml/cnxk/cn10k_ml_dev.h | 3 +\n drivers/ml/cnxk/cn10k_ml_ops.c | 207 +++++++++++++++++++++++++++++++++\n drivers/ml/cnxk/cn10k_ml_ops.h | 4 +\n 3 files changed, 214 insertions(+)", "diff": "diff --git a/drivers/ml/cnxk/cn10k_ml_dev.h b/drivers/ml/cnxk/cn10k_ml_dev.h\nindex 68fcc957fa..8f6bc24370 100644\n--- a/drivers/ml/cnxk/cn10k_ml_dev.h\n+++ b/drivers/ml/cnxk/cn10k_ml_dev.h\n@@ -33,6 +33,9 @@\n /* ML command timeout in seconds */\n #define ML_CN10K_CMD_TIMEOUT 5\n \n+/* ML slow-path job flags */\n+#define ML_CN10K_SP_FLAGS_OCM_NONRELOCATABLE BIT(0)\n+\n /* Poll mode job state */\n #define ML_CN10K_POLL_JOB_START\t 0\n #define ML_CN10K_POLL_JOB_FINISH 1\ndiff --git a/drivers/ml/cnxk/cn10k_ml_ops.c b/drivers/ml/cnxk/cn10k_ml_ops.c\nindex 8603cba20e..65f69ba8fb 100644\n--- a/drivers/ml/cnxk/cn10k_ml_ops.c\n+++ b/drivers/ml/cnxk/cn10k_ml_ops.c\n@@ -114,6 +114,64 @@ cn10k_ml_qp_create(const struct rte_ml_dev *dev, uint16_t qp_id, uint32_t nb_des\n \treturn NULL;\n }\n \n+static void\n+cn10k_ml_prep_sp_job_descriptor(struct cn10k_ml_dev *mldev, struct cn10k_ml_model *model,\n+\t\t\t\tstruct cn10k_ml_req *req, enum cn10k_ml_job_type job_type)\n+{\n+\tstruct cn10k_ml_model_metadata *metadata;\n+\tstruct cn10k_ml_model_addr *addr;\n+\n+\tmetadata = &model->metadata;\n+\taddr = &model->addr;\n+\n+\tmemset(&req->jd, 0, sizeof(struct cn10k_ml_jd));\n+\treq->jd.hdr.jce.w0.u64 = 0;\n+\treq->jd.hdr.jce.w1.u64 = PLT_U64_CAST(&req->status);\n+\treq->jd.hdr.model_id = model->model_id;\n+\treq->jd.hdr.job_type = job_type;\n+\treq->jd.hdr.fp_flags = 0x0;\n+\treq->jd.hdr.result = roc_ml_addr_ap2mlip(&mldev->roc, &req->result);\n+\n+\tif (job_type == ML_CN10K_JOB_TYPE_MODEL_START) {\n+\t\tif (!model->metadata.model.ocm_relocatable)\n+\t\t\treq->jd.hdr.sp_flags = ML_CN10K_SP_FLAGS_OCM_NONRELOCATABLE;\n+\t\telse\n+\t\t\treq->jd.hdr.sp_flags = 0x0;\n+\t\treq->jd.model_start.model_src_ddr_addr =\n+\t\t\tPLT_U64_CAST(roc_ml_addr_ap2mlip(&mldev->roc, addr->init_load_addr));\n+\t\treq->jd.model_start.model_dst_ddr_addr =\n+\t\t\tPLT_U64_CAST(roc_ml_addr_ap2mlip(&mldev->roc, addr->init_run_addr));\n+\t\treq->jd.model_start.model_init_offset = 0x0;\n+\t\treq->jd.model_start.model_main_offset = metadata->init_model.file_size;\n+\t\treq->jd.model_start.model_finish_offset =\n+\t\t\tmetadata->init_model.file_size + metadata->main_model.file_size;\n+\t\treq->jd.model_start.model_init_size = metadata->init_model.file_size;\n+\t\treq->jd.model_start.model_main_size = metadata->main_model.file_size;\n+\t\treq->jd.model_start.model_finish_size = metadata->finish_model.file_size;\n+\t\treq->jd.model_start.model_wb_offset = metadata->init_model.file_size +\n+\t\t\t\t\t\t metadata->main_model.file_size +\n+\t\t\t\t\t\t metadata->finish_model.file_size;\n+\t\treq->jd.model_start.num_layers = metadata->model.num_layers;\n+\t\treq->jd.model_start.num_gather_entries = 0;\n+\t\treq->jd.model_start.num_scatter_entries = 0;\n+\t\treq->jd.model_start.tilemask = 0; /* Updated after reserving pages */\n+\t\treq->jd.model_start.batch_size = model->batch_size;\n+\t\treq->jd.model_start.ocm_wb_base_address = 0; /* Updated after reserving pages */\n+\t\treq->jd.model_start.ocm_wb_range_start = metadata->model.ocm_wb_range_start;\n+\t\treq->jd.model_start.ocm_wb_range_end = metadata->model.ocm_wb_range_end;\n+\t\treq->jd.model_start.ddr_wb_base_address = PLT_U64_CAST(roc_ml_addr_ap2mlip(\n+\t\t\t&mldev->roc,\n+\t\t\tPLT_PTR_ADD(addr->finish_load_addr, metadata->finish_model.file_size)));\n+\t\treq->jd.model_start.ddr_wb_range_start = metadata->model.ddr_wb_range_start;\n+\t\treq->jd.model_start.ddr_wb_range_end = metadata->model.ddr_wb_range_end;\n+\t\treq->jd.model_start.input.s.ddr_range_start = metadata->model.ddr_input_range_start;\n+\t\treq->jd.model_start.input.s.ddr_range_end = metadata->model.ddr_input_range_end;\n+\t\treq->jd.model_start.output.s.ddr_range_start =\n+\t\t\tmetadata->model.ddr_output_range_start;\n+\t\treq->jd.model_start.output.s.ddr_range_end = metadata->model.ddr_output_range_end;\n+\t}\n+}\n+\n static int\n cn10k_ml_dev_info_get(struct rte_ml_dev *dev, struct rte_ml_dev_info *dev_info)\n {\n@@ -561,6 +619,154 @@ cn10k_ml_model_unload(struct rte_ml_dev *dev, int16_t model_id)\n \treturn plt_memzone_free(plt_memzone_lookup(str));\n }\n \n+int\n+cn10k_ml_model_start(struct rte_ml_dev *dev, int16_t model_id)\n+{\n+\tstruct cn10k_ml_model *model;\n+\tstruct cn10k_ml_dev *mldev;\n+\tstruct cn10k_ml_ocm *ocm;\n+\tstruct cn10k_ml_req *req;\n+\n+\tbool job_enqueued;\n+\tbool job_dequeued;\n+\tuint8_t num_tiles;\n+\tuint64_t tilemask;\n+\tint wb_page_start;\n+\tint tile_start;\n+\tint tile_end;\n+\tbool locked;\n+\tint ret = 0;\n+\n+\tmldev = dev->data->dev_private;\n+\tocm = &mldev->ocm;\n+\tmodel = dev->data->models[model_id];\n+\n+\tif (model == NULL) {\n+\t\tplt_err(\"Invalid model_id = %d\", model_id);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\t/* Prepare JD */\n+\treq = model->req;\n+\tcn10k_ml_prep_sp_job_descriptor(mldev, model, req, ML_CN10K_JOB_TYPE_MODEL_START);\n+\treq->result.error_code = 0x0;\n+\treq->result.user_ptr = NULL;\n+\n+\tplt_write64(ML_CN10K_POLL_JOB_START, &req->status);\n+\tplt_wmb();\n+\n+\tnum_tiles = model->metadata.model.tile_end - model->metadata.model.tile_start + 1;\n+\n+\tlocked = false;\n+\twhile (!locked) {\n+\t\tif (plt_spinlock_trylock(&model->lock) != 0) {\n+\t\t\tif (model->state == ML_CN10K_MODEL_STATE_STARTED) {\n+\t\t\t\tplt_ml_dbg(\"Model already started, model = 0x%016lx\",\n+\t\t\t\t\t PLT_U64_CAST(model));\n+\t\t\t\tplt_spinlock_unlock(&model->lock);\n+\t\t\t\treturn 1;\n+\t\t\t}\n+\n+\t\t\tif (model->state == ML_CN10K_MODEL_STATE_JOB_ACTIVE) {\n+\t\t\t\tplt_err(\"A slow-path job is active for the model = 0x%016lx\",\n+\t\t\t\t\tPLT_U64_CAST(model));\n+\t\t\t\tplt_spinlock_unlock(&model->lock);\n+\t\t\t\treturn -EBUSY;\n+\t\t\t}\n+\n+\t\t\tmodel->state = ML_CN10K_MODEL_STATE_JOB_ACTIVE;\n+\t\t\tplt_spinlock_unlock(&model->lock);\n+\t\t\tlocked = true;\n+\t\t}\n+\t}\n+\n+\twhile (!model->model_mem_map.ocm_reserved) {\n+\t\tif (plt_spinlock_trylock(&ocm->lock) != 0) {\n+\t\t\twb_page_start = cn10k_ml_ocm_tilemask_find(\n+\t\t\t\tdev, num_tiles, model->model_mem_map.wb_pages,\n+\t\t\t\tmodel->model_mem_map.scratch_pages, &tilemask);\n+\n+\t\t\tif (wb_page_start == -1) {\n+\t\t\t\tplt_err(\"Free pages not available on OCM tiles\");\n+\t\t\t\tplt_err(\"Failed to start model = 0x%016lx, name = %s\",\n+\t\t\t\t\tPLT_U64_CAST(model), model->metadata.model.name);\n+\n+\t\t\t\tplt_spinlock_unlock(&ocm->lock);\n+\t\t\t\treturn -ENOMEM;\n+\t\t\t}\n+\n+\t\t\tmodel->model_mem_map.tilemask = tilemask;\n+\t\t\tmodel->model_mem_map.wb_page_start = wb_page_start;\n+\n+\t\t\tcn10k_ml_ocm_reserve_pages(\n+\t\t\t\tdev, model->model_id, model->model_mem_map.tilemask,\n+\t\t\t\tmodel->model_mem_map.wb_page_start, model->model_mem_map.wb_pages,\n+\t\t\t\tmodel->model_mem_map.scratch_pages);\n+\t\t\tmodel->model_mem_map.ocm_reserved = true;\n+\t\t\tplt_spinlock_unlock(&ocm->lock);\n+\t\t}\n+\t}\n+\n+\t/* Update JD */\n+\tcn10k_ml_ocm_tilecount(model->model_mem_map.tilemask, &tile_start, &tile_end);\n+\treq->jd.model_start.tilemask = GENMASK_ULL(tile_end, tile_start);\n+\treq->jd.model_start.ocm_wb_base_address =\n+\t\tmodel->model_mem_map.wb_page_start * ocm->page_size;\n+\n+\tjob_enqueued = false;\n+\tjob_dequeued = false;\n+\tdo {\n+\t\tif (!job_enqueued) {\n+\t\t\treq->timeout = plt_tsc_cycles() + ML_CN10K_CMD_TIMEOUT * plt_tsc_hz();\n+\t\t\tjob_enqueued = roc_ml_scratch_enqueue(&mldev->roc, &req->jd);\n+\t\t}\n+\n+\t\tif (job_enqueued && !job_dequeued)\n+\t\t\tjob_dequeued = roc_ml_scratch_dequeue(&mldev->roc, &req->jd);\n+\n+\t\tif (job_dequeued)\n+\t\t\tbreak;\n+\t} while (plt_tsc_cycles() < req->timeout);\n+\n+\tif (job_dequeued) {\n+\t\tif (plt_read64(&req->status) == ML_CN10K_POLL_JOB_FINISH) {\n+\t\t\tif (req->result.error_code == 0)\n+\t\t\t\tret = 0;\n+\t\t\telse\n+\t\t\t\tret = -1;\n+\t\t}\n+\t} else { /* Reset scratch registers */\n+\t\troc_ml_scratch_queue_reset(&mldev->roc);\n+\t\tret = -ETIME;\n+\t}\n+\n+\tlocked = false;\n+\twhile (!locked) {\n+\t\tif (plt_spinlock_trylock(&model->lock) != 0) {\n+\t\t\tif (ret == 0)\n+\t\t\t\tmodel->state = ML_CN10K_MODEL_STATE_STARTED;\n+\t\t\telse\n+\t\t\t\tmodel->state = ML_CN10K_MODEL_STATE_UNKNOWN;\n+\n+\t\t\tplt_spinlock_unlock(&model->lock);\n+\t\t\tlocked = true;\n+\t\t}\n+\t}\n+\n+\tif (model->state == ML_CN10K_MODEL_STATE_UNKNOWN) {\n+\t\twhile (model->model_mem_map.ocm_reserved) {\n+\t\t\tif (plt_spinlock_trylock(&ocm->lock) != 0) {\n+\t\t\t\tcn10k_ml_ocm_free_pages(dev, model->model_id);\n+\t\t\t\tmodel->model_mem_map.ocm_reserved = false;\n+\t\t\t\tmodel->model_mem_map.tilemask = 0x0;\n+\t\t\t\tplt_spinlock_unlock(&ocm->lock);\n+\t\t\t}\n+\t\t}\n+\t}\n+\n+\treturn ret;\n+}\n+\n struct rte_ml_dev_ops cn10k_ml_ops = {\n \t/* Device control ops */\n \t.dev_info_get = cn10k_ml_dev_info_get,\n@@ -576,4 +782,5 @@ struct rte_ml_dev_ops cn10k_ml_ops = {\n \t/* Model ops */\n \t.model_load = cn10k_ml_model_load,\n \t.model_unload = cn10k_ml_model_unload,\n+\t.model_start = cn10k_ml_model_start,\n };\ndiff --git a/drivers/ml/cnxk/cn10k_ml_ops.h b/drivers/ml/cnxk/cn10k_ml_ops.h\nindex 981aa52655..af2ea19dce 100644\n--- a/drivers/ml/cnxk/cn10k_ml_ops.h\n+++ b/drivers/ml/cnxk/cn10k_ml_ops.h\n@@ -25,6 +25,9 @@ struct cn10k_ml_req {\n \n \t/* Job command */\n \tstruct ml_job_cmd_s jcmd;\n+\n+\t/* Timeout cycle */\n+\tuint64_t timeout;\n } __rte_aligned(ROC_ALIGN);\n \n /* Request queue */\n@@ -61,5 +64,6 @@ extern struct rte_ml_dev_ops cn10k_ml_ops;\n int cn10k_ml_model_load(struct rte_ml_dev *dev, struct rte_ml_model_params *params,\n \t\t\tint16_t *model_id);\n int cn10k_ml_model_unload(struct rte_ml_dev *dev, int16_t model_id);\n+int cn10k_ml_model_start(struct rte_ml_dev *dev, int16_t model_id);\n \n #endif /* _CN10K_ML_OPS_H_ */\n", "prefixes": [ "v4", "18/39" ] }