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GET /api/patches/122826/?format=api
{ "id": 122826, "url": "http://patches.dpdk.org/api/patches/122826/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20230201092310.23252-14-syalavarthi@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20230201092310.23252-14-syalavarthi@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20230201092310.23252-14-syalavarthi@marvell.com", "date": "2023-02-01T09:22:44", "name": "[v4,13/39] ml/cnxk: add internal structures for derived info", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "94cc5612a8cbe4187a5839a958a6bcb70fd8a5d2", "submitter": { "id": 2480, "url": "http://patches.dpdk.org/api/people/2480/?format=api", "name": "Srikanth Yalavarthi", "email": "syalavarthi@marvell.com" }, "delegate": { "id": 1, "url": "http://patches.dpdk.org/api/users/1/?format=api", "username": "tmonjalo", "first_name": "Thomas", "last_name": "Monjalon", "email": "thomas@monjalon.net" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20230201092310.23252-14-syalavarthi@marvell.com/mbox/", "series": [ { "id": 26732, "url": "http://patches.dpdk.org/api/series/26732/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=26732", "date": "2023-02-01T09:22:31", "name": "Implementation of ML CNXK driver", "version": 4, "mbox": "http://patches.dpdk.org/series/26732/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/122826/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/122826/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 310FB41B9D;\n\tWed, 1 Feb 2023 10:25:17 +0100 (CET)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 9F61442F9E;\n\tWed, 1 Feb 2023 10:23:38 +0100 (CET)", "from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com\n [67.231.148.174])\n by mails.dpdk.org (Postfix) with ESMTP id 4003642D59\n for <dev@dpdk.org>; Wed, 1 Feb 2023 10:23:23 +0100 (CET)", "from pps.filterd (m0045849.ppops.net [127.0.0.1])\n by mx0a-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id\n 3116LRXw024189 for <dev@dpdk.org>; Wed, 1 Feb 2023 01:23:22 -0800", "from dc5-exch02.marvell.com ([199.233.59.182])\n by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3nfjr8rgv6-2\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Wed, 01 Feb 2023 01:23:22 -0800", "from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.42;\n Wed, 1 Feb 2023 01:23:19 -0800", "from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.42 via Frontend\n Transport; Wed, 1 Feb 2023 01:23:19 -0800", "from ml-host-33.caveonetworks.com (unknown [10.110.143.233])\n by maili.marvell.com (Postfix) with ESMTP id E8FE83F70C6;\n Wed, 1 Feb 2023 01:23:16 -0800 (PST)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-type; s=pfpt0220; bh=5o1vBcj8nmzJXITTcF9cIjH0n0kuROiM6DZplITPCuA=;\n b=iyw0/lsPsqoT6MDpJsutNZGLf2K8UqYBf/5DRU2mezB+oveM4AQsODsl8WV4SEoKvXLb\n GGi8quWbbTSa9NXHRB4oLJMj5sHx0jX1AoVX2pnalxKJB/+b1UJhmaVfCg2azLPQ010S\n MiLJ4wX88po8l5Xp8r1vH6g2NqKXoHlZOXyo18PhAJgWW9X9gvjA4bZGuoQpXrCT+V4K\n UdggAZwvdPweWZ+1qYpCbH2b9he0dk15r9ugWh/6sEDEVophvk3JJPwMHtCw1osvulUF\n xKiY8/jfNgsN31lHz+rDYaL3pUcVc+8+tkzb6Ds7looda89B+LRTrIaO/Zbo7M7cI8pe vg==", "From": "Srikanth Yalavarthi <syalavarthi@marvell.com>", "To": "Srikanth Yalavarthi <syalavarthi@marvell.com>", "CC": "<dev@dpdk.org>, <sshankarnara@marvell.com>, <jerinj@marvell.com>,\n <aprabhu@marvell.com>", "Subject": "[PATCH v4 13/39] ml/cnxk: add internal structures for derived info", "Date": "Wed, 1 Feb 2023 01:22:44 -0800", "Message-ID": "<20230201092310.23252-14-syalavarthi@marvell.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": "<20230201092310.23252-1-syalavarthi@marvell.com>", "References": "<20221208200220.20267-1-syalavarthi@marvell.com>\n <20230201092310.23252-1-syalavarthi@marvell.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Proofpoint-GUID": "lm3S02fv1WsfsS4i_l5SOQiEveEXo951", "X-Proofpoint-ORIG-GUID": "lm3S02fv1WsfsS4i_l5SOQiEveEXo951", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.219,Aquarius:18.0.930,Hydra:6.0.562,FMLib:17.11.122.1\n definitions=2023-02-01_03,2023-01-31_01,2022-06-22_01", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Added internal structures to handle derived address fields\nand enabled support to compute DMA addresses for model start.\nEnabled updating internal model fields.\n\nSigned-off-by: Srikanth Yalavarthi <syalavarthi@marvell.com>\n---\n drivers/ml/cnxk/cn10k_ml_model.c | 89 ++++++++++++++++++++++++++++++++\n drivers/ml/cnxk/cn10k_ml_model.h | 80 ++++++++++++++++++++++++++++\n drivers/ml/cnxk/cn10k_ml_ops.c | 18 ++++++-\n 3 files changed, 186 insertions(+), 1 deletion(-)", "diff": "diff --git a/drivers/ml/cnxk/cn10k_ml_model.c b/drivers/ml/cnxk/cn10k_ml_model.c\nindex 0fefab9daa..dafcae106b 100644\n--- a/drivers/ml/cnxk/cn10k_ml_model.c\n+++ b/drivers/ml/cnxk/cn10k_ml_model.c\n@@ -214,3 +214,92 @@ cn10k_ml_model_metadata_update(struct cn10k_ml_model_metadata *metadata)\n \t\t\tcn10k_ml_io_type_map(metadata->output[i].model_output_type);\n \t}\n }\n+\n+void\n+cn10k_ml_model_addr_update(struct cn10k_ml_model *model, uint8_t *buffer, uint8_t *base_dma_addr)\n+{\n+\tstruct cn10k_ml_model_metadata *metadata;\n+\tstruct cn10k_ml_model_addr *addr;\n+\tsize_t model_data_size;\n+\tuint8_t *dma_addr_load;\n+\tuint8_t *dma_addr_run;\n+\tuint8_t i;\n+\tint fpos;\n+\n+\tmetadata = &model->metadata;\n+\taddr = &model->addr;\n+\tmodel_data_size = metadata->init_model.file_size + metadata->main_model.file_size +\n+\t\t\t metadata->finish_model.file_size + metadata->weights_bias.file_size;\n+\n+\t/* Base address */\n+\taddr->base_dma_addr_load = base_dma_addr;\n+\taddr->base_dma_addr_run = PLT_PTR_ADD(addr->base_dma_addr_load, model_data_size);\n+\n+\t/* Init section */\n+\tdma_addr_load = addr->base_dma_addr_load;\n+\tdma_addr_run = addr->base_dma_addr_run;\n+\tfpos = sizeof(struct cn10k_ml_model_metadata);\n+\taddr->init_load_addr = dma_addr_load;\n+\taddr->init_run_addr = dma_addr_run;\n+\trte_memcpy(dma_addr_load, PLT_PTR_ADD(buffer, fpos), metadata->init_model.file_size);\n+\n+\t/* Main section */\n+\tdma_addr_load += metadata->init_model.file_size;\n+\tdma_addr_run += metadata->init_model.file_size;\n+\tfpos += metadata->init_model.file_size;\n+\taddr->main_load_addr = dma_addr_load;\n+\taddr->main_run_addr = dma_addr_run;\n+\trte_memcpy(dma_addr_load, PLT_PTR_ADD(buffer, fpos), metadata->main_model.file_size);\n+\n+\t/* Finish section */\n+\tdma_addr_load += metadata->main_model.file_size;\n+\tdma_addr_run += metadata->main_model.file_size;\n+\tfpos += metadata->main_model.file_size;\n+\taddr->finish_load_addr = dma_addr_load;\n+\taddr->finish_run_addr = dma_addr_run;\n+\trte_memcpy(dma_addr_load, PLT_PTR_ADD(buffer, fpos), metadata->finish_model.file_size);\n+\n+\t/* Weights and Bias section */\n+\tdma_addr_load += metadata->finish_model.file_size;\n+\tfpos += metadata->finish_model.file_size;\n+\taddr->wb_base_addr = PLT_PTR_SUB(dma_addr_load, metadata->weights_bias.mem_offset);\n+\taddr->wb_load_addr = PLT_PTR_ADD(addr->wb_base_addr, metadata->weights_bias.mem_offset);\n+\trte_memcpy(addr->wb_load_addr, PLT_PTR_ADD(buffer, fpos), metadata->weights_bias.file_size);\n+\n+\t/* Inputs */\n+\taddr->total_input_sz_d = 0;\n+\taddr->total_input_sz_q = 0;\n+\tfor (i = 0; i < metadata->model.num_input; i++) {\n+\t\taddr->input[i].nb_elements =\n+\t\t\tmodel->metadata.input[i].shape.w * model->metadata.input[i].shape.x *\n+\t\t\tmodel->metadata.input[i].shape.y * model->metadata.input[i].shape.z;\n+\t\taddr->input[i].sz_d = addr->input[i].nb_elements *\n+\t\t\t\t rte_ml_io_type_size_get(metadata->input[i].input_type);\n+\t\taddr->input[i].sz_q = addr->input[i].nb_elements *\n+\t\t\t\t rte_ml_io_type_size_get(metadata->input[i].model_input_type);\n+\t\taddr->total_input_sz_d += addr->input[i].sz_d;\n+\t\taddr->total_input_sz_q += addr->input[i].sz_q;\n+\n+\t\tplt_ml_dbg(\"model_id = %d, input[%u] - w:%u x:%u y:%u z:%u, sz_d = %u sz_q = %u\",\n+\t\t\t model->model_id, i, metadata->input[i].shape.w,\n+\t\t\t metadata->input[i].shape.x, metadata->input[i].shape.y,\n+\t\t\t metadata->input[i].shape.z, addr->input[i].sz_d, addr->input[i].sz_q);\n+\t}\n+\n+\t/* Outputs */\n+\taddr->total_output_sz_q = 0;\n+\taddr->total_output_sz_d = 0;\n+\tfor (i = 0; i < metadata->model.num_output; i++) {\n+\t\taddr->output[i].nb_elements = metadata->output[i].size;\n+\t\taddr->output[i].sz_d = addr->output[i].nb_elements *\n+\t\t\t\t rte_ml_io_type_size_get(metadata->output[i].output_type);\n+\t\taddr->output[i].sz_q =\n+\t\t\taddr->output[i].nb_elements *\n+\t\t\trte_ml_io_type_size_get(metadata->output[i].model_output_type);\n+\t\taddr->total_output_sz_q += addr->output[i].sz_q;\n+\t\taddr->total_output_sz_d += addr->output[i].sz_d;\n+\n+\t\tplt_ml_dbg(\"model_id = %d, output[%u] - sz_d = %u, sz_q = %u\", model->model_id, i,\n+\t\t\t addr->output[i].sz_d, addr->output[i].sz_q);\n+\t}\n+}\ndiff --git a/drivers/ml/cnxk/cn10k_ml_model.h b/drivers/ml/cnxk/cn10k_ml_model.h\nindex e25d6780e9..7e276c3b12 100644\n--- a/drivers/ml/cnxk/cn10k_ml_model.h\n+++ b/drivers/ml/cnxk/cn10k_ml_model.h\n@@ -322,6 +322,81 @@ struct cn10k_ml_model_metadata {\n \tuint8_t reserved3[16];\n };\n \n+/* Model address structure */\n+struct cn10k_ml_model_addr {\n+\t/* Base DMA address for load */\n+\tvoid *base_dma_addr_load;\n+\n+\t/* Base DMA address for run */\n+\tvoid *base_dma_addr_run;\n+\n+\t/* Init section load address */\n+\tvoid *init_load_addr;\n+\n+\t/* Init section run address */\n+\tvoid *init_run_addr;\n+\n+\t/* Main section load address */\n+\tvoid *main_load_addr;\n+\n+\t/* Main section run address */\n+\tvoid *main_run_addr;\n+\n+\t/* Finish section load address */\n+\tvoid *finish_load_addr;\n+\n+\t/* Finish section run address */\n+\tvoid *finish_run_addr;\n+\n+\t/* Weights and Bias base address */\n+\tvoid *wb_base_addr;\n+\n+\t/* Weights and bias load address */\n+\tvoid *wb_load_addr;\n+\n+\t/* Start tile */\n+\tuint8_t tile_start;\n+\n+\t/* End tile */\n+\tuint8_t tile_end;\n+\n+\t/* Input address and size */\n+\tstruct {\n+\t\t/* Number of elements */\n+\t\tuint32_t nb_elements;\n+\n+\t\t/* Dequantized input size */\n+\t\tuint32_t sz_d;\n+\n+\t\t/* Quantized input size */\n+\t\tuint32_t sz_q;\n+\t} input[MRVL_ML_INPUT_OUTPUT_SIZE];\n+\n+\t/* Output address and size */\n+\tstruct {\n+\t\t/* Number of elements */\n+\t\tuint32_t nb_elements;\n+\n+\t\t/* Dequantize output size */\n+\t\tuint32_t sz_d;\n+\n+\t\t/* Quantized output size */\n+\t\tuint32_t sz_q;\n+\t} output[MRVL_ML_INPUT_OUTPUT_SIZE];\n+\n+\t/* Total size of quantized input */\n+\tuint32_t total_input_sz_q;\n+\n+\t/* Total size of dequantized input */\n+\tuint32_t total_input_sz_d;\n+\n+\t/* Total size of quantized output */\n+\tuint32_t total_output_sz_q;\n+\n+\t/* Total size of dequantized output */\n+\tuint32_t total_output_sz_d;\n+};\n+\n /* Model Object */\n struct cn10k_ml_model {\n \t/* Device reference */\n@@ -339,6 +414,9 @@ struct cn10k_ml_model {\n \t/* Metadata */\n \tstruct cn10k_ml_model_metadata metadata;\n \n+\t/* Address structure */\n+\tstruct cn10k_ml_model_addr addr;\n+\n \t/* Spinlock, used to update model state */\n \tplt_spinlock_t lock;\n \n@@ -348,5 +426,7 @@ struct cn10k_ml_model {\n \n int cn10k_ml_model_metadata_check(uint8_t *buffer, uint64_t size);\n void cn10k_ml_model_metadata_update(struct cn10k_ml_model_metadata *metadata);\n+void cn10k_ml_model_addr_update(struct cn10k_ml_model *model, uint8_t *buffer,\n+\t\t\t\tuint8_t *base_dma_addr);\n \n #endif /* _CN10K_ML_MODEL_H_ */\ndiff --git a/drivers/ml/cnxk/cn10k_ml_ops.c b/drivers/ml/cnxk/cn10k_ml_ops.c\nindex f7c1d43aee..20f15ec35d 100644\n--- a/drivers/ml/cnxk/cn10k_ml_ops.c\n+++ b/drivers/ml/cnxk/cn10k_ml_ops.c\n@@ -408,11 +408,14 @@ cn10k_ml_dev_queue_pair_setup(struct rte_ml_dev *dev, uint16_t queue_pair_id,\n int\n cn10k_ml_model_load(struct rte_ml_dev *dev, struct rte_ml_model_params *params, int16_t *model_id)\n {\n+\tstruct cn10k_ml_model_metadata *metadata;\n \tstruct cn10k_ml_model *model;\n \tstruct cn10k_ml_dev *mldev;\n \n \tchar str[RTE_MEMZONE_NAMESIZE];\n \tconst struct plt_memzone *mz;\n+\tsize_t model_data_size;\n+\tuint8_t *base_dma_addr;\n \tuint64_t mz_size;\n \tuint16_t idx;\n \tbool found;\n@@ -439,7 +442,12 @@ cn10k_ml_model_load(struct rte_ml_dev *dev, struct rte_ml_model_params *params,\n \t}\n \n \t/* Compute memzone size */\n-\tmz_size = PLT_ALIGN_CEIL(sizeof(struct cn10k_ml_model), ML_CN10K_ALIGN_SIZE);\n+\tmetadata = (struct cn10k_ml_model_metadata *)params->addr;\n+\tmodel_data_size = metadata->init_model.file_size + metadata->main_model.file_size +\n+\t\t\t metadata->finish_model.file_size + metadata->weights_bias.file_size;\n+\tmodel_data_size = PLT_ALIGN_CEIL(model_data_size, ML_CN10K_ALIGN_SIZE);\n+\tmz_size = PLT_ALIGN_CEIL(sizeof(struct cn10k_ml_model), ML_CN10K_ALIGN_SIZE) +\n+\t\t 2 * model_data_size;\n \n \t/* Allocate memzone for model object and model data */\n \tsnprintf(str, RTE_MEMZONE_NAMESIZE, \"%s_%u\", CN10K_ML_MODEL_MEMZONE_NAME, idx);\n@@ -462,6 +470,14 @@ cn10k_ml_model_load(struct rte_ml_dev *dev, struct rte_ml_model_params *params,\n \telse\n \t\tmodel->batch_size = model->metadata.model.batch_size;\n \n+\t/* Set DMA base address */\n+\tbase_dma_addr = PLT_PTR_ADD(\n+\t\tmz->addr, PLT_ALIGN_CEIL(sizeof(struct cn10k_ml_model), ML_CN10K_ALIGN_SIZE));\n+\tcn10k_ml_model_addr_update(model, params->addr, base_dma_addr);\n+\n+\t/* Copy data from load to run. run address to be used by MLIP */\n+\trte_memcpy(model->addr.base_dma_addr_run, model->addr.base_dma_addr_load, model_data_size);\n+\n \tplt_spinlock_init(&model->lock);\n \tmodel->state = ML_CN10K_MODEL_STATE_LOADED;\n \tdev->data->models[idx] = model;\n", "prefixes": [ "v4", "13/39" ] }