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GET /api/patches/122825/?format=api
{ "id": 122825, "url": "http://patches.dpdk.org/api/patches/122825/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20230201092310.23252-16-syalavarthi@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20230201092310.23252-16-syalavarthi@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20230201092310.23252-16-syalavarthi@marvell.com", "date": "2023-02-01T09:22:46", "name": "[v4,15/39] ml/cnxk: add structures for slow and fast path JDs", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "3199040683364c54996fc621065015809425936b", "submitter": { "id": 2480, "url": "http://patches.dpdk.org/api/people/2480/?format=api", "name": "Srikanth Yalavarthi", "email": "syalavarthi@marvell.com" }, "delegate": { "id": 1, "url": "http://patches.dpdk.org/api/users/1/?format=api", "username": "tmonjalo", "first_name": "Thomas", "last_name": "Monjalon", "email": "thomas@monjalon.net" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20230201092310.23252-16-syalavarthi@marvell.com/mbox/", "series": [ { "id": 26732, "url": "http://patches.dpdk.org/api/series/26732/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=26732", "date": "2023-02-01T09:22:31", "name": "Implementation of ML CNXK driver", "version": 4, "mbox": "http://patches.dpdk.org/series/26732/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/122825/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/122825/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id E29BD41B9D;\n\tWed, 1 Feb 2023 10:25:08 +0100 (CET)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 1CC0142F88;\n\tWed, 1 Feb 2023 10:23:37 +0100 (CET)", "from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com\n [67.231.148.174])\n by mails.dpdk.org (Postfix) with ESMTP id C49F142D49\n for <dev@dpdk.org>; Wed, 1 Feb 2023 10:23:22 +0100 (CET)", "from pps.filterd (m0045849.ppops.net [127.0.0.1])\n by mx0a-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id\n 3116LRXv024189 for <dev@dpdk.org>; Wed, 1 Feb 2023 01:23:22 -0800", "from dc5-exch02.marvell.com ([199.233.59.182])\n by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3nfjr8rgv6-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Wed, 01 Feb 2023 01:23:21 -0800", "from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.42;\n Wed, 1 Feb 2023 01:23:19 -0800", "from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.42 via Frontend\n Transport; Wed, 1 Feb 2023 01:23:19 -0800", "from ml-host-33.caveonetworks.com (unknown [10.110.143.233])\n by maili.marvell.com (Postfix) with ESMTP id 92F9C3F7059;\n Wed, 1 Feb 2023 01:23:17 -0800 (PST)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-type; s=pfpt0220; bh=O4vL8MwGkBo09fq6Iud8rFUipKxQZw6vBmXu6s8IDqI=;\n b=D2GNEe1w0FtXfUw0j05mXli3+gWAkocjuF2nlaAk4UC8OaRwK5bnj/gt/SbMt7Ethe1i\n Txwf28psCldYnu7tnEkk/TxQDKuv7+Eu522uwCpqSdIYx7G0yHhzAQDvkG94bjuqy2YO\n a79SrF6fNxtNqrLSsqTKeqeLexCxtGrrQTGKizxv21ViMyFzImiuGDhfHodD/gV6/5wo\n 0bU22brN+NvwvO9807uCaCGVkhU94Ijh1a9vY/3K+yS8fOyZacE7J8n5eJUlGJHtdGlC\n 4YPAKGHyg6p1knmP1mGwUbKhMf4dSXgHzQcUQMue0P/3iEBBWrU6JgOf/rjolrDtNY7h jA==", "From": "Srikanth Yalavarthi <syalavarthi@marvell.com>", "To": "Srikanth Yalavarthi <syalavarthi@marvell.com>", "CC": "<dev@dpdk.org>, <sshankarnara@marvell.com>, <jerinj@marvell.com>,\n <aprabhu@marvell.com>", "Subject": "[PATCH v4 15/39] ml/cnxk: add structures for slow and fast path JDs", "Date": "Wed, 1 Feb 2023 01:22:46 -0800", "Message-ID": "<20230201092310.23252-16-syalavarthi@marvell.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": "<20230201092310.23252-1-syalavarthi@marvell.com>", "References": "<20221208200220.20267-1-syalavarthi@marvell.com>\n <20230201092310.23252-1-syalavarthi@marvell.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Proofpoint-GUID": "vkJJs7adXpb1Rnk9ccRDe9t5HQ8S9Tel", "X-Proofpoint-ORIG-GUID": "vkJJs7adXpb1Rnk9ccRDe9t5HQ8S9Tel", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.219,Aquarius:18.0.930,Hydra:6.0.562,FMLib:17.11.122.1\n definitions=2023-02-01_03,2023-01-31_01,2022-06-22_01", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Added JD structures for load, unload and run jobs. Initialize\njob command and allocate memory for request structures for slow\npath jobs.\n\nSigned-off-by: Srikanth Yalavarthi <syalavarthi@marvell.com>\n---\n drivers/ml/cnxk/cn10k_ml_dev.h | 99 ++++++++++++++++++++++++++++++++\n drivers/ml/cnxk/cn10k_ml_model.h | 4 ++\n drivers/ml/cnxk/cn10k_ml_ops.c | 19 +++++-\n drivers/ml/cnxk/cn10k_ml_ops.h | 4 ++\n 4 files changed, 125 insertions(+), 1 deletion(-)", "diff": "diff --git a/drivers/ml/cnxk/cn10k_ml_dev.h b/drivers/ml/cnxk/cn10k_ml_dev.h\nindex 02a4496c97..68fcc957fa 100644\n--- a/drivers/ml/cnxk/cn10k_ml_dev.h\n+++ b/drivers/ml/cnxk/cn10k_ml_dev.h\n@@ -188,6 +188,105 @@ struct cn10k_ml_jd {\n \n \t\t\tuint8_t rsvd[8];\n \t\t} fw_load;\n+\n+\t\tstruct cn10k_ml_jd_section_model_start {\n+\t\t\t/* Source model start address in DDR relative to ML_MLR_BASE */\n+\t\t\tuint64_t model_src_ddr_addr;\n+\n+\t\t\t/* Destination model start address in DDR relative to ML_MLR_BASE */\n+\t\t\tuint64_t model_dst_ddr_addr;\n+\n+\t\t\t/* Offset to model init section in the model */\n+\t\t\tuint64_t model_init_offset : 32;\n+\n+\t\t\t/* Size of init section in the model */\n+\t\t\tuint64_t model_init_size : 32;\n+\n+\t\t\t/* Offset to model main section in the model */\n+\t\t\tuint64_t model_main_offset : 32;\n+\n+\t\t\t/* Size of main section in the model */\n+\t\t\tuint64_t model_main_size : 32;\n+\n+\t\t\t/* Offset to model finish section in the model */\n+\t\t\tuint64_t model_finish_offset : 32;\n+\n+\t\t\t/* Size of finish section in the model */\n+\t\t\tuint64_t model_finish_size : 32;\n+\n+\t\t\t/* Offset to WB in model bin */\n+\t\t\tuint64_t model_wb_offset : 32;\n+\n+\t\t\t/* Number of model layers */\n+\t\t\tuint64_t num_layers : 8;\n+\n+\t\t\t/* Number of gather entries, 0 means linear input mode (= no gather) */\n+\t\t\tuint64_t num_gather_entries : 8;\n+\n+\t\t\t/* Number of scatter entries 0 means linear input mode (= no scatter) */\n+\t\t\tuint64_t num_scatter_entries : 8;\n+\n+\t\t\t/* Tile mask to load model */\n+\t\t\tuint64_t tilemask : 8;\n+\n+\t\t\t/* Batch size of model */\n+\t\t\tuint64_t batch_size : 32;\n+\n+\t\t\t/* OCM WB base address */\n+\t\t\tuint64_t ocm_wb_base_address : 32;\n+\n+\t\t\t/* OCM WB range start */\n+\t\t\tuint64_t ocm_wb_range_start : 32;\n+\n+\t\t\t/* OCM WB range End */\n+\t\t\tuint64_t ocm_wb_range_end : 32;\n+\n+\t\t\t/* DDR WB address */\n+\t\t\tuint64_t ddr_wb_base_address;\n+\n+\t\t\t/* DDR WB range start */\n+\t\t\tuint64_t ddr_wb_range_start : 32;\n+\n+\t\t\t/* DDR WB range end */\n+\t\t\tuint64_t ddr_wb_range_end : 32;\n+\n+\t\t\tunion {\n+\t\t\t\t/* Points to gather list if num_gather_entries > 0 */\n+\t\t\t\tvoid *gather_list;\n+\t\t\t\tstruct {\n+\t\t\t\t\t/* Linear input mode */\n+\t\t\t\t\tuint64_t ddr_range_start : 32;\n+\t\t\t\t\tuint64_t ddr_range_end : 32;\n+\t\t\t\t} s;\n+\t\t\t} input;\n+\n+\t\t\tunion {\n+\t\t\t\t/* Points to scatter list if num_scatter_entries > 0 */\n+\t\t\t\tvoid *scatter_list;\n+\t\t\t\tstruct {\n+\t\t\t\t\t/* Linear output mode */\n+\t\t\t\t\tuint64_t ddr_range_start : 32;\n+\t\t\t\t\tuint64_t ddr_range_end : 32;\n+\t\t\t\t} s;\n+\t\t\t} output;\n+\t\t} model_start;\n+\n+\t\tstruct cn10k_ml_jd_section_model_stop {\n+\t\t\tuint8_t rsvd[96];\n+\t\t} model_stop;\n+\n+\t\tstruct cn10k_ml_jd_section_model_run {\n+\t\t\t/* Address of the input for the run relative to ML_MLR_BASE */\n+\t\t\tuint64_t input_ddr_addr;\n+\n+\t\t\t/* Address of the output for the run relative to ML_MLR_BASE */\n+\t\t\tuint64_t output_ddr_addr;\n+\n+\t\t\t/* Number of batches to run in variable batch processing */\n+\t\t\tuint16_t num_batches;\n+\n+\t\t\tuint8_t rsvd[78];\n+\t\t} model_run;\n \t};\n };\n \ndiff --git a/drivers/ml/cnxk/cn10k_ml_model.h b/drivers/ml/cnxk/cn10k_ml_model.h\nindex ebd296c609..003f5aba36 100644\n--- a/drivers/ml/cnxk/cn10k_ml_model.h\n+++ b/drivers/ml/cnxk/cn10k_ml_model.h\n@@ -11,6 +11,7 @@\n \n #include \"cn10k_ml_dev.h\"\n #include \"cn10k_ml_ocm.h\"\n+#include \"cn10k_ml_ops.h\"\n \n /* Model state */\n enum cn10k_ml_model_state {\n@@ -426,6 +427,9 @@ struct cn10k_ml_model {\n \n \t/* State */\n \tenum cn10k_ml_model_state state;\n+\n+\t/* Slow-path operations request pointer */\n+\tstruct cn10k_ml_req *req;\n };\n \n int cn10k_ml_model_metadata_check(uint8_t *buffer, uint64_t size);\ndiff --git a/drivers/ml/cnxk/cn10k_ml_ops.c b/drivers/ml/cnxk/cn10k_ml_ops.c\nindex 9ccf52332f..8603cba20e 100644\n--- a/drivers/ml/cnxk/cn10k_ml_ops.c\n+++ b/drivers/ml/cnxk/cn10k_ml_ops.c\n@@ -12,6 +12,10 @@\n /* ML model macros */\n #define CN10K_ML_MODEL_MEMZONE_NAME \"ml_cn10k_model_mz\"\n \n+/* ML Job descriptor flags */\n+#define ML_FLAGS_POLL_COMPL BIT(0)\n+#define ML_FLAGS_SSO_COMPL BIT(1)\n+\n static void\n qp_memzone_name_get(char *name, int size, int dev_id, int qp_id)\n {\n@@ -65,6 +69,7 @@ cn10k_ml_qp_create(const struct rte_ml_dev *dev, uint16_t qp_id, uint32_t nb_des\n \tstruct cn10k_ml_qp *qp;\n \tuint32_t len;\n \tuint8_t *va;\n+\tuint64_t i;\n \n \t/* Allocate queue pair */\n \tqp = rte_zmalloc_socket(\"cn10k_ml_pmd_queue_pair\", sizeof(struct cn10k_ml_qp), ROC_ALIGN,\n@@ -95,6 +100,12 @@ cn10k_ml_qp_create(const struct rte_ml_dev *dev, uint16_t qp_id, uint32_t nb_des\n \tqp->queue.wait_cycles = ML_CN10K_CMD_TIMEOUT * plt_tsc_hz();\n \tqp->nb_desc = nb_desc;\n \n+\t/* Initialize job command */\n+\tfor (i = 0; i < qp->nb_desc; i++) {\n+\t\tmemset(&qp->queue.reqs[i].jd, 0, sizeof(struct cn10k_ml_jd));\n+\t\tqp->queue.reqs[i].jcmd.w1.s.jobptr = PLT_U64_CAST(&qp->queue.reqs[i].jd);\n+\t}\n+\n \treturn qp;\n \n qp_free:\n@@ -468,7 +479,8 @@ cn10k_ml_model_load(struct rte_ml_dev *dev, struct rte_ml_model_params *params,\n \t\t\t metadata->finish_model.file_size + metadata->weights_bias.file_size;\n \tmodel_data_size = PLT_ALIGN_CEIL(model_data_size, ML_CN10K_ALIGN_SIZE);\n \tmz_size = PLT_ALIGN_CEIL(sizeof(struct cn10k_ml_model), ML_CN10K_ALIGN_SIZE) +\n-\t\t 2 * model_data_size;\n+\t\t 2 * model_data_size +\n+\t\t PLT_ALIGN_CEIL(sizeof(struct cn10k_ml_req), ML_CN10K_ALIGN_SIZE);\n \n \t/* Allocate memzone for model object and model data */\n \tsnprintf(str, RTE_MEMZONE_NAMESIZE, \"%s_%u\", CN10K_ML_MODEL_MEMZONE_NAME, idx);\n@@ -507,6 +519,11 @@ cn10k_ml_model_load(struct rte_ml_dev *dev, struct rte_ml_model_params *params,\n \tmodel->model_mem_map.wb_pages = wb_pages;\n \tmodel->model_mem_map.scratch_pages = scratch_pages;\n \n+\t/* Set slow-path request address and state */\n+\tmodel->req = PLT_PTR_ADD(\n+\t\tmz->addr, PLT_ALIGN_CEIL(sizeof(struct cn10k_ml_model), ML_CN10K_ALIGN_SIZE) +\n+\t\t\t\t 2 * model_data_size);\n+\n \tplt_spinlock_init(&model->lock);\n \tmodel->state = ML_CN10K_MODEL_STATE_LOADED;\n \tdev->data->models[idx] = model;\ndiff --git a/drivers/ml/cnxk/cn10k_ml_ops.h b/drivers/ml/cnxk/cn10k_ml_ops.h\nindex 8a939cabc7..981aa52655 100644\n--- a/drivers/ml/cnxk/cn10k_ml_ops.h\n+++ b/drivers/ml/cnxk/cn10k_ml_ops.h\n@@ -6,6 +6,7 @@\n #define _CN10K_ML_OPS_H_\n \n #include <rte_mldev.h>\n+#include <rte_mldev_pmd.h>\n \n #include <roc_api.h>\n \n@@ -21,6 +22,9 @@ struct cn10k_ml_req {\n \n \t/* Status field for poll mode requests */\n \tvolatile uint64_t status;\n+\n+\t/* Job command */\n+\tstruct ml_job_cmd_s jcmd;\n } __rte_aligned(ROC_ALIGN);\n \n /* Request queue */\n", "prefixes": [ "v4", "15/39" ] }