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GET /api/patches/122819/?format=api
{ "id": 122819, "url": "http://patches.dpdk.org/api/patches/122819/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20230201092310.23252-9-syalavarthi@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20230201092310.23252-9-syalavarthi@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20230201092310.23252-9-syalavarthi@marvell.com", "date": "2023-02-01T09:22:39", "name": "[v4,08/39] ml/cnxk: enable support for simulator environment", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "3c48e49bec147115696b0addc74816457fce8905", "submitter": { "id": 2480, "url": "http://patches.dpdk.org/api/people/2480/?format=api", "name": "Srikanth Yalavarthi", "email": "syalavarthi@marvell.com" }, "delegate": { "id": 1, "url": "http://patches.dpdk.org/api/users/1/?format=api", "username": "tmonjalo", "first_name": "Thomas", "last_name": "Monjalon", "email": "thomas@monjalon.net" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20230201092310.23252-9-syalavarthi@marvell.com/mbox/", "series": [ { "id": 26732, "url": "http://patches.dpdk.org/api/series/26732/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=26732", "date": "2023-02-01T09:22:31", "name": "Implementation of ML CNXK driver", "version": 4, "mbox": "http://patches.dpdk.org/series/26732/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/122819/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/122819/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 3B90141B9D;\n\tWed, 1 Feb 2023 10:24:27 +0100 (CET)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 2686D42D88;\n\tWed, 1 Feb 2023 10:23:29 +0100 (CET)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n [67.231.156.173])\n by mails.dpdk.org (Postfix) with ESMTP id 3195142D29\n for <dev@dpdk.org>; Wed, 1 Feb 2023 10:23:19 +0100 (CET)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n by mx0b-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id\n 3116M428010261 for <dev@dpdk.org>; Wed, 1 Feb 2023 01:23:18 -0800", "from dc5-exch02.marvell.com ([199.233.59.182])\n by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3nfjrj0s0f-5\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Wed, 01 Feb 2023 01:23:18 -0800", "from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.42;\n Wed, 1 Feb 2023 01:23:16 -0800", "from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.42 via Frontend\n Transport; Wed, 1 Feb 2023 01:23:15 -0800", "from ml-host-33.caveonetworks.com (unknown [10.110.143.233])\n by maili.marvell.com (Postfix) with ESMTP id 5EFA63F70E7;\n Wed, 1 Feb 2023 01:23:15 -0800 (PST)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-type; s=pfpt0220; bh=UxghtxWNIoa/urab9LWIQBwNFxc60gxPtTINtsrmkoM=;\n b=QwtlM92gKF9V1iOuBKRP6XWHtC1f/fC70/gHiMFaR6C/Enm13KdmmfMaprGFGwMyWUB3\n FXyw2bz6eVWI1I3vdUXFe5BKhgcHJqbuE6mdCd0MAciuVq42qcvFwspMjjg8MhjO2fl7\n 4dseissM85ruUZlgmFYuXUBdxsKzWxO05FxJjjKcQbNvQkc3DoU2boL65y//meh4SwGC\n 0jPdQIFIAA69lfsGDh35QlqmkI3AWhFHKP3vvHgf7XcG01ugiPs4AvxKF6MBogX6TyLU\n eI619y4Eh3dgydxvyHpHIOJDrgovqZg4xSkvk3bOTeWOdRV5q43HrpdKYxreBHzhf++W yw==", "From": "Srikanth Yalavarthi <syalavarthi@marvell.com>", "To": "Srikanth Yalavarthi <syalavarthi@marvell.com>", "CC": "<dev@dpdk.org>, <sshankarnara@marvell.com>, <jerinj@marvell.com>,\n <aprabhu@marvell.com>", "Subject": "[PATCH v4 08/39] ml/cnxk: enable support for simulator environment", "Date": "Wed, 1 Feb 2023 01:22:39 -0800", "Message-ID": "<20230201092310.23252-9-syalavarthi@marvell.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": "<20230201092310.23252-1-syalavarthi@marvell.com>", "References": "<20221208200220.20267-1-syalavarthi@marvell.com>\n <20230201092310.23252-1-syalavarthi@marvell.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Proofpoint-ORIG-GUID": "-anLdFDDd00uv6LSPKPW8E66Sv2BujMg", "X-Proofpoint-GUID": "-anLdFDDd00uv6LSPKPW8E66Sv2BujMg", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.219,Aquarius:18.0.930,Hydra:6.0.562,FMLib:17.11.122.1\n definitions=2023-02-01_03,2023-01-31_01,2022-06-22_01", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Enabled device initialization and firmware load on simulator\nplatform. Firmware load stage on simulator would involve\nlaunching a firmware handshake request only.\n\nSigned-off-by: Srikanth Yalavarthi <syalavarthi@marvell.com>\n---\n drivers/ml/cnxk/cn10k_ml_dev.c | 119 +++++++++++++++++++++++++++++----\n 1 file changed, 107 insertions(+), 12 deletions(-)", "diff": "diff --git a/drivers/ml/cnxk/cn10k_ml_dev.c b/drivers/ml/cnxk/cn10k_ml_dev.c\nindex 90fca45ddd..837f006bf0 100644\n--- a/drivers/ml/cnxk/cn10k_ml_dev.c\n+++ b/drivers/ml/cnxk/cn10k_ml_dev.c\n@@ -213,6 +213,89 @@ cn10k_ml_fw_flags_get(struct cn10k_ml_fw *fw)\n \treturn FW_LOAD_FLAGS;\n }\n \n+static int\n+cn10k_ml_fw_load_asim(struct cn10k_ml_fw *fw)\n+{\n+\tstruct cn10k_ml_dev *mldev;\n+\tuint64_t timeout_cycle;\n+\tuint64_t reg_val64;\n+\tbool timeout;\n+\tint ret = 0;\n+\n+\tmldev = fw->mldev;\n+\n+\t/* Reset HEAD and TAIL debug pointer registers */\n+\troc_ml_reg_write64(&mldev->roc, 0, ML_SCRATCH_DBG_BUFFER_HEAD_C0);\n+\troc_ml_reg_write64(&mldev->roc, 0, ML_SCRATCH_DBG_BUFFER_TAIL_C0);\n+\troc_ml_reg_write64(&mldev->roc, 0, ML_SCRATCH_DBG_BUFFER_HEAD_C1);\n+\troc_ml_reg_write64(&mldev->roc, 0, ML_SCRATCH_DBG_BUFFER_TAIL_C1);\n+\troc_ml_reg_write64(&mldev->roc, 0, ML_SCRATCH_EXCEPTION_SP_C0);\n+\troc_ml_reg_write64(&mldev->roc, 0, ML_SCRATCH_EXCEPTION_SP_C1);\n+\n+\t/* Set ML_MLR_BASE to base IOVA of the ML region in LLC/DRAM. */\n+\treg_val64 = rte_eal_get_baseaddr();\n+\troc_ml_reg_write64(&mldev->roc, reg_val64, ML_MLR_BASE);\n+\tplt_ml_dbg(\"ML_MLR_BASE = 0x%016lx\", roc_ml_reg_read64(&mldev->roc, ML_MLR_BASE));\n+\troc_ml_reg_save(&mldev->roc, ML_MLR_BASE);\n+\n+\t/* Update FW load completion structure */\n+\tfw->req->jd.hdr.jce.w1.u64 = PLT_U64_CAST(&fw->req->status);\n+\tfw->req->jd.hdr.job_type = ML_CN10K_JOB_TYPE_FIRMWARE_LOAD;\n+\tfw->req->jd.hdr.result = roc_ml_addr_ap2mlip(&mldev->roc, &fw->req->result);\n+\tfw->req->jd.fw_load.flags = cn10k_ml_fw_flags_get(fw);\n+\tplt_write64(ML_CN10K_POLL_JOB_START, &fw->req->status);\n+\tplt_wmb();\n+\n+\t/* Enqueue FW load through scratch registers */\n+\ttimeout = true;\n+\ttimeout_cycle = plt_tsc_cycles() + ML_CN10K_CMD_TIMEOUT * plt_tsc_hz();\n+\troc_ml_scratch_enqueue(&mldev->roc, &fw->req->jd);\n+\n+\tplt_rmb();\n+\tdo {\n+\t\tif (roc_ml_scratch_is_done_bit_set(&mldev->roc) &&\n+\t\t (plt_read64(&fw->req->status) == ML_CN10K_POLL_JOB_FINISH)) {\n+\t\t\ttimeout = false;\n+\t\t\tbreak;\n+\t\t}\n+\t} while (plt_tsc_cycles() < timeout_cycle);\n+\n+\t/* Check firmware load status, clean-up and exit on failure. */\n+\tif ((!timeout) && (fw->req->result.error_code == 0)) {\n+\t\tcn10k_ml_fw_print_info(fw);\n+\t} else {\n+\t\t/* Set ML to disable new jobs */\n+\t\treg_val64 = (ROC_ML_CFG_JD_SIZE | ROC_ML_CFG_MLIP_ENA);\n+\t\troc_ml_reg_write64(&mldev->roc, reg_val64, ML_CFG);\n+\n+\t\t/* Clear scratch registers */\n+\t\troc_ml_reg_write64(&mldev->roc, 0, ML_SCRATCH_WORK_PTR);\n+\t\troc_ml_reg_write64(&mldev->roc, 0, ML_SCRATCH_FW_CTRL);\n+\n+\t\tif (timeout) {\n+\t\t\tplt_err(\"Firmware load timeout\");\n+\t\t\tret = -ETIME;\n+\t\t} else {\n+\t\t\tplt_err(\"Firmware load failed\");\n+\t\t\tret = -1;\n+\t\t}\n+\n+\t\treturn ret;\n+\t}\n+\n+\t/* Reset scratch registers */\n+\troc_ml_reg_write64(&mldev->roc, 0, ML_SCRATCH_FW_CTRL);\n+\troc_ml_reg_write64(&mldev->roc, 0, ML_SCRATCH_WORK_PTR);\n+\n+\t/* Disable job execution, to be enabled in start */\n+\treg_val64 = roc_ml_reg_read64(&mldev->roc, ML_CFG);\n+\treg_val64 &= ~ROC_ML_CFG_ENA;\n+\troc_ml_reg_write64(&mldev->roc, reg_val64, ML_CFG);\n+\tplt_ml_dbg(\"ML_CFG => 0x%016lx\", roc_ml_reg_read64(&mldev->roc, ML_CFG));\n+\n+\treturn ret;\n+}\n+\n static int\n cn10k_ml_fw_load_cn10ka(struct cn10k_ml_fw *fw, void *buffer, uint64_t size)\n {\n@@ -447,16 +530,22 @@ cn10k_ml_fw_load(struct cn10k_ml_dev *mldev)\n \tfw = &mldev->fw;\n \tfw->mldev = mldev;\n \n-\t/* Read firmware image to a buffer */\n-\tret = rte_firmware_read(fw->path, &fw_buffer, &fw_size);\n-\tif (ret < 0) {\n-\t\tplt_err(\"Can't read firmware data: %s\\n\", fw->path);\n-\t\treturn ret;\n+\tif (roc_env_is_emulator() || roc_env_is_hw()) {\n+\t\t/* Read firmware image to a buffer */\n+\t\tret = rte_firmware_read(fw->path, &fw_buffer, &fw_size);\n+\t\tif (ret < 0) {\n+\t\t\tplt_err(\"Can't read firmware data: %s\\n\", fw->path);\n+\t\t\treturn ret;\n+\t\t}\n+\n+\t\t/* Reserve memzone for firmware load completion and data */\n+\t\tmz_size = sizeof(struct cn10k_ml_req) + fw_size + FW_STACK_BUFFER_SIZE +\n+\t\t\t FW_DEBUG_BUFFER_SIZE + FW_EXCEPTION_BUFFER_SIZE;\n+\t} else if (roc_env_is_asim()) {\n+\t\t/* Reserve memzone for firmware load completion */\n+\t\tmz_size = sizeof(struct cn10k_ml_req);\n \t}\n \n-\t/* Reserve memzone for firmware load completion and data */\n-\tmz_size = sizeof(struct cn10k_ml_req) + fw_size + FW_STACK_BUFFER_SIZE +\n-\t\t FW_DEBUG_BUFFER_SIZE + FW_EXCEPTION_BUFFER_SIZE;\n \tmz = plt_memzone_reserve_aligned(FW_MEMZONE_NAME, mz_size, 0, ML_CN10K_ALIGN_SIZE);\n \tif (mz == NULL) {\n \t\tplt_err(\"plt_memzone_reserve failed : %s\", FW_MEMZONE_NAME);\n@@ -475,10 +564,16 @@ cn10k_ml_fw_load(struct cn10k_ml_dev *mldev)\n \t\troc_ml_mlip_reset(&mldev->roc, true);\n \n \t/* Load firmware */\n-\tfw->data = PLT_PTR_ADD(mz->addr, sizeof(struct cn10k_ml_req));\n-\tret = cn10k_ml_fw_load_cn10ka(fw, fw_buffer, fw_size);\n-\tif (fw_buffer != NULL)\n-\t\tfree(fw_buffer);\n+\tif (roc_env_is_emulator() || roc_env_is_hw()) {\n+\t\tfw->data = PLT_PTR_ADD(mz->addr, sizeof(struct cn10k_ml_req));\n+\t\tret = cn10k_ml_fw_load_cn10ka(fw, fw_buffer, fw_size);\n+\t\tif (fw_buffer != NULL)\n+\t\t\tfree(fw_buffer);\n+\t} else if (roc_env_is_asim()) {\n+\t\tfw->data = NULL;\n+\t\tret = cn10k_ml_fw_load_asim(fw);\n+\t}\n+\n \tif (ret < 0)\n \t\tcn10k_ml_fw_unload(mldev);\n \n", "prefixes": [ "v4", "08/39" ] }