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GET /api/patches/122813/?format=api
{ "id": 122813, "url": "http://patches.dpdk.org/api/patches/122813/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20230201092310.23252-2-syalavarthi@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20230201092310.23252-2-syalavarthi@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20230201092310.23252-2-syalavarthi@marvell.com", "date": "2023-02-01T09:22:32", "name": "[v4,01/39] common/cnxk: add ML headers and ROC code for cnxk", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "4c78124dd7d62ccb88de7147f3b1e31e50dea23b", "submitter": { "id": 2480, "url": "http://patches.dpdk.org/api/people/2480/?format=api", "name": "Srikanth Yalavarthi", "email": "syalavarthi@marvell.com" }, "delegate": { "id": 1, "url": "http://patches.dpdk.org/api/users/1/?format=api", "username": "tmonjalo", "first_name": "Thomas", "last_name": "Monjalon", "email": "thomas@monjalon.net" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20230201092310.23252-2-syalavarthi@marvell.com/mbox/", "series": [ { "id": 26732, "url": "http://patches.dpdk.org/api/series/26732/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=26732", "date": "2023-02-01T09:22:31", "name": "Implementation of ML CNXK driver", "version": 4, "mbox": "http://patches.dpdk.org/series/26732/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/122813/comments/", "check": "warning", "checks": "http://patches.dpdk.org/api/patches/122813/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 6F44B41B9D;\n\tWed, 1 Feb 2023 10:23:38 +0100 (CET)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 3EC4E42D0B;\n\tWed, 1 Feb 2023 10:23:21 +0100 (CET)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n [67.231.156.173])\n by mails.dpdk.org (Postfix) with ESMTP id 45D75406A2\n for <dev@dpdk.org>; Wed, 1 Feb 2023 10:23:17 +0100 (CET)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n by mx0b-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id\n 3116M423010261; Wed, 1 Feb 2023 01:23:16 -0800", "from dc5-exch02.marvell.com ([199.233.59.182])\n by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3nfjrj0s0f-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT);\n Wed, 01 Feb 2023 01:23:16 -0800", "from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.42;\n Wed, 1 Feb 2023 01:23:13 -0800", "from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.42 via Frontend\n Transport; Wed, 1 Feb 2023 01:23:13 -0800", "from ml-host-33.caveonetworks.com (unknown [10.110.143.233])\n by maili.marvell.com (Postfix) with ESMTP id 0380D5B6924;\n Wed, 1 Feb 2023 01:23:12 -0800 (PST)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-type; s=pfpt0220; bh=CsegH4KOsfkq2a9AKXUVYwQAruPMHJKBPSmAvBa8RXA=;\n b=KU36CDfO9SaWG20sboMOK/ZU3G78bG62OyPUl+zJlpHsMRarpMSKGI/YOIv0brMxBNWI\n s/lLeqBO5mvqgA92oQdlo/W3t/xhDT9l2FmvmngojqeigM/RZV+6oDaHc/lWI4RDbOtl\n Tt2VlYUOJmjChrp6QSo7xcwVCOWjTIlvfqOEgZMb2e9KcvuWl4s18alxyf1ayi4TQPKp\n istc392icPZUwalABf06ihiRy8xWoQoA5wPcGvCzNe46GC2p3EBpT93VQccCpJ43d7oL\n hP2BkKhN88hUiZGliAQWhghW24KSwqW5u+gBjU9naLZMzRtbw96YIMjgfun9FWuvNhhS sQ==", "From": "Srikanth Yalavarthi <syalavarthi@marvell.com>", "To": "Thomas Monjalon <thomas@monjalon.net>, Srikanth Yalavarthi\n <syalavarthi@marvell.com>, Nithin Dabilpuram <ndabilpuram@marvell.com>,\n \"Kiran Kumar K\" <kirankumark@marvell.com>, Sunil Kumar Kori\n <skori@marvell.com>, Satha Rao <skoteshwar@marvell.com>", "CC": "<dev@dpdk.org>, <sshankarnara@marvell.com>, <jerinj@marvell.com>,\n <aprabhu@marvell.com>", "Subject": "[PATCH v4 01/39] common/cnxk: add ML headers and ROC code for cnxk", "Date": "Wed, 1 Feb 2023 01:22:32 -0800", "Message-ID": "<20230201092310.23252-2-syalavarthi@marvell.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": "<20230201092310.23252-1-syalavarthi@marvell.com>", "References": "<20221208200220.20267-1-syalavarthi@marvell.com>\n <20230201092310.23252-1-syalavarthi@marvell.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Proofpoint-ORIG-GUID": "kIBn4PLL-WalUiPHjzAllJnbXg1Xahk2", "X-Proofpoint-GUID": "kIBn4PLL-WalUiPHjzAllJnbXg1Xahk2", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.219,Aquarius:18.0.930,Hydra:6.0.562,FMLib:17.11.122.1\n definitions=2023-02-01_03,2023-01-31_01,2022-06-22_01", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Added ML cnxk headers for register, structure definitions and\nROC layer. Implemented ROC functions, registered logtype for\nML module with the name pmd.ml.cnxk and defined ML hardware ID.\n\nSigned-off-by: Srikanth Yalavarthi <syalavarthi@marvell.com>\n---\nDepends-on: series-26731 (\"Implementation of ML common code\")\n\n MAINTAINERS | 9 +\n drivers/common/cnxk/hw/ml.h | 170 ++++++++\n drivers/common/cnxk/meson.build | 1 +\n drivers/common/cnxk/roc_api.h | 4 +\n drivers/common/cnxk/roc_constants.h | 2 +\n drivers/common/cnxk/roc_dev_priv.h | 1 +\n drivers/common/cnxk/roc_ml.c | 626 ++++++++++++++++++++++++++++\n drivers/common/cnxk/roc_ml.h | 152 +++++++\n drivers/common/cnxk/roc_ml_priv.h | 24 ++\n drivers/common/cnxk/roc_platform.c | 1 +\n drivers/common/cnxk/roc_platform.h | 2 +\n drivers/common/cnxk/roc_priv.h | 3 +\n drivers/common/cnxk/version.map | 29 ++\n 13 files changed, 1024 insertions(+)\n create mode 100644 drivers/common/cnxk/hw/ml.h\n create mode 100644 drivers/common/cnxk/roc_ml.c\n create mode 100644 drivers/common/cnxk/roc_ml.h\n create mode 100644 drivers/common/cnxk/roc_ml_priv.h\n\n--\n2.17.1", "diff": "diff --git a/MAINTAINERS b/MAINTAINERS\nindex 36f6e43470..265f5b9a3d 100644\n--- a/MAINTAINERS\n+++ b/MAINTAINERS\n@@ -1434,6 +1434,15 @@ F: drivers/raw/dpaa2_cmdif/\n F: doc/guides/rawdevs/dpaa2_cmdif.rst\n\n\n+ML Device Drivers\n+------------------------\n+\n+Marvell ML CNXK\n+M: Srikanth Yalavarthi <syalavarthi@marvell.com>\n+F: drivers/common/cnxk/hw/ml.h\n+F: drivers/common/cnxk/roc_ml*\n+\n+\n Packet processing\n -----------------\n\ndiff --git a/drivers/common/cnxk/hw/ml.h b/drivers/common/cnxk/hw/ml.h\nnew file mode 100644\nindex 0000000000..3ead42b807\n--- /dev/null\n+++ b/drivers/common/cnxk/hw/ml.h\n@@ -0,0 +1,170 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright (c) 2022 Marvell.\n+ */\n+\n+#ifndef __ML_HW_H__\n+#define __ML_HW_H__\n+\n+#include <stdint.h>\n+\n+/* Constants */\n+#define ML_ANBX_NR 0x3\n+\n+/* Base offsets */\n+#define ML_MLAB_BLK_OFFSET 0x20000000 /* CNF10KB */\n+#define ML_AXI_START_ADDR 0x800000000\n+\n+/* MLW register offsets / ML_PF_BAR0 */\n+#define ML_CFG\t\t\t 0x10000\n+#define ML_MLR_BASE\t\t 0x10008\n+#define ML_AXI_BRIDGE_CTRL(a)\t (0x10020 | (uint64_t)(a) << 3)\n+#define ML_JOB_MGR_CTRL\t\t 0x10060\n+#define ML_CORE_INT_LO\t\t 0x10140\n+#define ML_CORE_INT_HI\t\t 0x10160\n+#define ML_JCMDQ_IN(a)\t\t (0x11000 | (uint64_t)(a) << 3) /* CN10KA */\n+#define ML_JCMDQ_STATUS\t\t 0x11010\t\t\t/* CN10KA */\n+#define ML_STGX_STATUS(a)\t (0x11020 | (uint64_t)(a) << 3) /* CNF10KB */\n+#define ML_STG_CONTROL\t\t 0x11100\t\t\t/* CNF10KB */\n+#define ML_PNB_CMD_TYPE\t\t 0x113a0\t\t\t/* CNF10KB */\n+#define ML_SCRATCH(a)\t\t (0x14000 | (uint64_t)(a) << 3)\n+#define ML_ANBX_BACKP_DISABLE(a) (0x18000 | (uint64_t)(a) << 12) /* CN10KA */\n+#define ML_ANBX_NCBI_P_OVR(a)\t (0x18010 | (uint64_t)(a) << 12) /* CN10KA */\n+#define ML_ANBX_NCBI_NP_OVR(a)\t (0x18020 | (uint64_t)(a) << 12) /* CN10KA */\n+\n+/* MLIP configuration register offsets / ML_PF_BAR0 */\n+#define ML_SW_RST_CTRL\t\t 0x12084000\n+#define ML_A35_0_RST_VECTOR_BASE_W(a) (0x12084014 + (a) * (0x04))\n+#define ML_A35_1_RST_VECTOR_BASE_W(a) (0x1208401c + (a) * (0x04))\n+\n+/* MLW scratch register offsets */\n+#define ML_SCRATCH_WORK_PTR\t (ML_SCRATCH(0))\n+#define ML_SCRATCH_FW_CTRL\t (ML_SCRATCH(1))\n+#define ML_SCRATCH_DBG_BUFFER_HEAD_C0 (ML_SCRATCH(2))\n+#define ML_SCRATCH_DBG_BUFFER_TAIL_C0 (ML_SCRATCH(3))\n+#define ML_SCRATCH_DBG_BUFFER_HEAD_C1 (ML_SCRATCH(4))\n+#define ML_SCRATCH_DBG_BUFFER_TAIL_C1 (ML_SCRATCH(5))\n+#define ML_SCRATCH_EXCEPTION_SP_C0 (ML_SCRATCH(6))\n+#define ML_SCRATCH_EXCEPTION_SP_C1 (ML_SCRATCH(7))\n+\n+/* ML job completion structure */\n+struct ml_jce_s {\n+\t/* WORD 0 */\n+\tunion ml_jce_w0 {\n+\t\tstruct {\n+\t\t\tuint64_t rsvd_0_3 : 4;\n+\n+\t\t\t/* Reserved for future architecture */\n+\t\t\tuint64_t ggrp_h : 2;\n+\n+\t\t\t/* Tag type */\n+\t\t\tuint64_t ttype : 2;\n+\n+\t\t\t/* Physical function number */\n+\t\t\tuint64_t pf_func : 16;\n+\n+\t\t\t/* Unused [7] + Guest Group [6:0] */\n+\t\t\tuint64_t ggrp : 8;\n+\n+\t\t\t/* Tag */\n+\t\t\tuint64_t tag : 32;\n+\t\t} s;\n+\t\tuint64_t u64;\n+\t} w0;\n+\n+\t/* WORD 1 */\n+\tunion ml_jce_w1 {\n+\t\tstruct {\n+\t\t\t/* Work queue pointer */\n+\t\t\tuint64_t wqp : 53;\n+\t\t\tuint64_t rsvd_53_63 : 11;\n+\n+\t\t} s;\n+\t\tuint64_t u64;\n+\t} w1;\n+};\n+\n+/* ML job command structure */\n+struct ml_job_cmd_s {\n+\t/* WORD 0 */\n+\tunion ml_job_cmd_w0 {\n+\t\tstruct {\n+\t\t\tuint64_t rsvd_0_63;\n+\t\t} s;\n+\t\tuint64_t u64;\n+\t} w0;\n+\n+\t/* WORD 1 */\n+\tunion ml_job_cmd_w1 {\n+\t\tstruct {\n+\t\t\t/* Job pointer */\n+\t\t\tuint64_t jobptr : 53;\n+\t\t\tuint64_t rsvd_53_63 : 11;\n+\t\t} s;\n+\t\tuint64_t u64;\n+\t} w1;\n+};\n+\n+/* ML A35 0 RST vector base structure */\n+union ml_a35_0_rst_vector_base_s {\n+\tstruct {\n+\t\t/* Base address */\n+\t\tuint64_t addr : 37;\n+\t\tuint64_t rsvd_37_63 : 27;\n+\t} s;\n+\n+\tstruct {\n+\t\t/* WORD 0 */\n+\t\tuint32_t w0;\n+\n+\t\t/* WORD 1 */\n+\t\tuint32_t w1;\n+\t} w;\n+\n+\tuint64_t u64;\n+};\n+\n+/* ML A35 1 RST vector base structure */\n+union ml_a35_1_rst_vector_base_s {\n+\tstruct {\n+\t\t/* Base address */\n+\t\tuint64_t addr : 37;\n+\t\tuint64_t rsvd_37_63 : 27;\n+\t} s;\n+\n+\tstruct {\n+\t\t/* WORD 0 */\n+\t\tuint32_t w0;\n+\n+\t\t/* WORD 1 */\n+\t\tuint32_t w1;\n+\t} w;\n+\n+\tuint64_t u64;\n+};\n+\n+/* Work pointer scratch register */\n+union ml_scratch_work_ptr_s {\n+\tstruct {\n+\t\t/* Work pointer */\n+\t\tuint64_t work_ptr : 37;\n+\t\tuint64_t rsvd_37_63 : 27;\n+\t} s;\n+\tuint64_t u64;\n+};\n+\n+/* Firmware control scratch register */\n+union ml_scratch_fw_ctrl_s {\n+\tstruct {\n+\t\tuint64_t rsvd_0_15 : 16;\n+\n+\t\t/* Valid job bit */\n+\t\tuint64_t valid : 1;\n+\n+\t\t/* Done status bit */\n+\t\tuint64_t done : 1;\n+\t\tuint64_t rsvd_18_63 : 46;\n+\t} s;\n+\tuint64_t u64;\n+};\n+\n+#endif /* __ML_HW_H__ */\ndiff --git a/drivers/common/cnxk/meson.build b/drivers/common/cnxk/meson.build\nindex 849735921c..b4aa0a050c 100644\n--- a/drivers/common/cnxk/meson.build\n+++ b/drivers/common/cnxk/meson.build\n@@ -26,6 +26,7 @@ sources = files(\n 'roc_irq.c',\n 'roc_ie_ot.c',\n 'roc_mbox.c',\n+ 'roc_ml.c',\n 'roc_model.c',\n 'roc_nix.c',\n 'roc_nix_bpf.c',\ndiff --git a/drivers/common/cnxk/roc_api.h b/drivers/common/cnxk/roc_api.h\nindex 14a11321e0..06accf247d 100644\n--- a/drivers/common/cnxk/roc_api.h\n+++ b/drivers/common/cnxk/roc_api.h\n@@ -34,6 +34,7 @@\n /* HW structure definition */\n #include \"hw/cpt.h\"\n #include \"hw/dpi.h\"\n+#include \"hw/ml.h\"\n #include \"hw/nix.h\"\n #include \"hw/npa.h\"\n #include \"hw/npc.h\"\n@@ -107,4 +108,7 @@\n /* NIX Inline dev */\n #include \"roc_nix_inl.h\"\n\n+/* ML */\n+#include \"roc_ml.h\"\n+\n #endif /* _ROC_API_H_ */\ndiff --git a/drivers/common/cnxk/roc_constants.h b/drivers/common/cnxk/roc_constants.h\nindex 0495965daa..ddaef133b8 100644\n--- a/drivers/common/cnxk/roc_constants.h\n+++ b/drivers/common/cnxk/roc_constants.h\n@@ -50,6 +50,8 @@\n #define PCI_DEVID_CN10K_RVU_CPT_PF 0xA0F2\n #define PCI_DEVID_CN10K_RVU_CPT_VF 0xA0F3\n\n+#define PCI_DEVID_CN10K_ML_PF 0xA092\n+\n #define PCI_SUBSYSTEM_DEVID_CN10KA 0xB900\n #define PCI_SUBSYSTEM_DEVID_CN10KAS 0xB900\n #define PCI_SUBSYSTEM_DEVID_CNF10KA 0xBA00\ndiff --git a/drivers/common/cnxk/roc_dev_priv.h b/drivers/common/cnxk/roc_dev_priv.h\nindex 4217ec4af8..40af5e0f0b 100644\n--- a/drivers/common/cnxk/roc_dev_priv.h\n+++ b/drivers/common/cnxk/roc_dev_priv.h\n@@ -90,6 +90,7 @@ struct dev {\n \tvoid *roc_nix;\n \tvoid *roc_cpt;\n \tvoid *roc_tim;\n+\tvoid *roc_ml;\n \tbool disable_shared_lmt; /* false(default): shared lmt mode enabled */\n \tconst struct plt_memzone *lmt_mz;\n } __plt_cache_aligned;\ndiff --git a/drivers/common/cnxk/roc_ml.c b/drivers/common/cnxk/roc_ml.c\nnew file mode 100644\nindex 0000000000..7390697b1d\n--- /dev/null\n+++ b/drivers/common/cnxk/roc_ml.c\n@@ -0,0 +1,626 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright (c) 2022 Marvell.\n+ */\n+\n+#include \"roc_api.h\"\n+#include \"roc_priv.h\"\n+\n+#define TIME_SEC_IN_MS 1000\n+\n+static int\n+roc_ml_reg_wait_to_clear(struct roc_ml *roc_ml, uint64_t offset, uint64_t mask)\n+{\n+\tuint64_t start_cycle;\n+\tuint64_t wait_cycles;\n+\tuint64_t reg_val;\n+\n+\twait_cycles = (ROC_ML_TIMEOUT_MS * plt_tsc_hz()) / TIME_SEC_IN_MS;\n+\tstart_cycle = plt_tsc_cycles();\n+\tdo {\n+\t\treg_val = roc_ml_reg_read64(roc_ml, offset);\n+\n+\t\tif (!(reg_val & mask))\n+\t\t\treturn 0;\n+\t} while (plt_tsc_cycles() - start_cycle < wait_cycles);\n+\n+\treturn -ETIME;\n+}\n+\n+uint64_t\n+roc_ml_reg_read64(struct roc_ml *roc_ml, uint64_t offset)\n+{\n+\tstruct ml *ml = roc_ml_to_ml_priv(roc_ml);\n+\n+\treturn plt_read64(PLT_PTR_ADD(ml->ml_reg_addr, offset));\n+}\n+\n+void\n+roc_ml_reg_write64(struct roc_ml *roc_ml, uint64_t val, uint64_t offset)\n+{\n+\tstruct ml *ml = roc_ml_to_ml_priv(roc_ml);\n+\n+\tplt_write64(val, PLT_PTR_ADD(ml->ml_reg_addr, offset));\n+}\n+\n+uint32_t\n+roc_ml_reg_read32(struct roc_ml *roc_ml, uint64_t offset)\n+{\n+\tstruct ml *ml = roc_ml_to_ml_priv(roc_ml);\n+\n+\treturn plt_read32(PLT_PTR_ADD(ml->ml_reg_addr, offset));\n+}\n+\n+void\n+roc_ml_reg_write32(struct roc_ml *roc_ml, uint32_t val, uint64_t offset)\n+{\n+\tstruct ml *ml = roc_ml_to_ml_priv(roc_ml);\n+\n+\tplt_write32(val, PLT_PTR_ADD(ml->ml_reg_addr, offset));\n+}\n+\n+void\n+roc_ml_reg_save(struct roc_ml *roc_ml, uint64_t offset)\n+{\n+\tstruct ml *ml = roc_ml_to_ml_priv(roc_ml);\n+\n+\tif (offset == ML_MLR_BASE) {\n+\t\tml->ml_mlr_base =\n+\t\t\tFIELD_GET(ROC_ML_MLR_BASE_BASE, roc_ml_reg_read64(roc_ml, offset));\n+\t\tml->ml_mlr_base_saved = true;\n+\t}\n+}\n+\n+void *\n+roc_ml_addr_ap2mlip(struct roc_ml *roc_ml, void *addr)\n+{\n+\tstruct ml *ml = roc_ml_to_ml_priv(roc_ml);\n+\tuint64_t ml_mlr_base;\n+\n+\tml_mlr_base = (ml->ml_mlr_base_saved) ? ml->ml_mlr_base :\n+\t\t\t\t\t\tFIELD_GET(ROC_ML_MLR_BASE_BASE,\n+\t\t\t\t\t\t\t roc_ml_reg_read64(roc_ml, ML_MLR_BASE));\n+\treturn PLT_PTR_ADD(addr, ML_AXI_START_ADDR - ml_mlr_base);\n+}\n+\n+void *\n+roc_ml_addr_mlip2ap(struct roc_ml *roc_ml, void *addr)\n+{\n+\tstruct ml *ml = roc_ml_to_ml_priv(roc_ml);\n+\tuint64_t ml_mlr_base;\n+\n+\tml_mlr_base = (ml->ml_mlr_base_saved) ? ml->ml_mlr_base :\n+\t\t\t\t\t\tFIELD_GET(ROC_ML_MLR_BASE_BASE,\n+\t\t\t\t\t\t\t roc_ml_reg_read64(roc_ml, ML_MLR_BASE));\n+\treturn PLT_PTR_ADD(addr, ml_mlr_base - ML_AXI_START_ADDR);\n+}\n+\n+uint64_t\n+roc_ml_addr_pa_to_offset(struct roc_ml *roc_ml, uint64_t phys_addr)\n+{\n+\tstruct ml *ml = roc_ml_to_ml_priv(roc_ml);\n+\n+\tif (roc_model_is_cn10ka())\n+\t\treturn phys_addr - ml->pci_dev->mem_resource[0].phys_addr;\n+\telse\n+\t\treturn phys_addr - ml->pci_dev->mem_resource[0].phys_addr - ML_MLAB_BLK_OFFSET;\n+}\n+\n+uint64_t\n+roc_ml_addr_offset_to_pa(struct roc_ml *roc_ml, uint64_t offset)\n+{\n+\tstruct ml *ml = roc_ml_to_ml_priv(roc_ml);\n+\n+\tif (roc_model_is_cn10ka())\n+\t\treturn ml->pci_dev->mem_resource[0].phys_addr + offset;\n+\telse\n+\t\treturn ml->pci_dev->mem_resource[0].phys_addr + ML_MLAB_BLK_OFFSET + offset;\n+}\n+\n+void\n+roc_ml_scratch_write_job(struct roc_ml *roc_ml, void *work_ptr)\n+{\n+\tunion ml_scratch_work_ptr_s reg_work_ptr;\n+\tunion ml_scratch_fw_ctrl_s reg_fw_ctrl;\n+\n+\treg_work_ptr.u64 = 0;\n+\treg_work_ptr.s.work_ptr = PLT_U64_CAST(roc_ml_addr_ap2mlip(roc_ml, work_ptr));\n+\n+\treg_fw_ctrl.u64 = 0;\n+\treg_fw_ctrl.s.valid = 1;\n+\n+\troc_ml_reg_write64(roc_ml, reg_work_ptr.u64, ML_SCRATCH_WORK_PTR);\n+\troc_ml_reg_write64(roc_ml, reg_fw_ctrl.u64, ML_SCRATCH_FW_CTRL);\n+}\n+\n+bool\n+roc_ml_scratch_is_valid_bit_set(struct roc_ml *roc_ml)\n+{\n+\tunion ml_scratch_fw_ctrl_s reg_fw_ctrl;\n+\n+\treg_fw_ctrl.u64 = roc_ml_reg_read64(roc_ml, ML_SCRATCH_FW_CTRL);\n+\n+\tif (reg_fw_ctrl.s.valid == 1)\n+\t\treturn true;\n+\n+\treturn false;\n+}\n+\n+bool\n+roc_ml_scratch_is_done_bit_set(struct roc_ml *roc_ml)\n+{\n+\tunion ml_scratch_fw_ctrl_s reg_fw_ctrl;\n+\n+\treg_fw_ctrl.u64 = roc_ml_reg_read64(roc_ml, ML_SCRATCH_FW_CTRL);\n+\n+\tif (reg_fw_ctrl.s.done == 1)\n+\t\treturn true;\n+\n+\treturn false;\n+}\n+\n+bool\n+roc_ml_scratch_enqueue(struct roc_ml *roc_ml, void *work_ptr)\n+{\n+\tunion ml_scratch_work_ptr_s reg_work_ptr;\n+\tunion ml_scratch_fw_ctrl_s reg_fw_ctrl;\n+\tbool ret = false;\n+\n+\treg_work_ptr.u64 = 0;\n+\treg_work_ptr.s.work_ptr = PLT_U64_CAST(roc_ml_addr_ap2mlip(roc_ml, work_ptr));\n+\n+\treg_fw_ctrl.u64 = 0;\n+\treg_fw_ctrl.s.valid = 1;\n+\n+\tif (plt_spinlock_trylock(&roc_ml->sp_spinlock) != 0) {\n+\t\tbool valid = roc_ml_scratch_is_valid_bit_set(roc_ml);\n+\t\tbool done = roc_ml_scratch_is_done_bit_set(roc_ml);\n+\n+\t\tif (valid == done) {\n+\t\t\troc_ml_clk_force_on(roc_ml);\n+\t\t\troc_ml_dma_stall_off(roc_ml);\n+\n+\t\t\troc_ml_reg_write64(roc_ml, reg_work_ptr.u64, ML_SCRATCH_WORK_PTR);\n+\t\t\troc_ml_reg_write64(roc_ml, reg_fw_ctrl.u64, ML_SCRATCH_FW_CTRL);\n+\n+\t\t\tret = true;\n+\t\t}\n+\t\tplt_spinlock_unlock(&roc_ml->sp_spinlock);\n+\t}\n+\n+\treturn ret;\n+}\n+\n+bool\n+roc_ml_scratch_dequeue(struct roc_ml *roc_ml, void *work_ptr)\n+{\n+\tunion ml_scratch_work_ptr_s reg_work_ptr;\n+\tbool ret = false;\n+\n+\tif (plt_spinlock_trylock(&roc_ml->sp_spinlock) != 0) {\n+\t\tbool valid = roc_ml_scratch_is_valid_bit_set(roc_ml);\n+\t\tbool done = roc_ml_scratch_is_done_bit_set(roc_ml);\n+\n+\t\tif (valid && done) {\n+\t\t\treg_work_ptr.u64 = roc_ml_reg_read64(roc_ml, ML_SCRATCH_WORK_PTR);\n+\t\t\tif (work_ptr ==\n+\t\t\t roc_ml_addr_mlip2ap(roc_ml, PLT_PTR_CAST(reg_work_ptr.u64))) {\n+\t\t\t\troc_ml_dma_stall_on(roc_ml);\n+\t\t\t\troc_ml_clk_force_off(roc_ml);\n+\n+\t\t\t\troc_ml_reg_write64(roc_ml, 0, ML_SCRATCH_WORK_PTR);\n+\t\t\t\troc_ml_reg_write64(roc_ml, 0, ML_SCRATCH_FW_CTRL);\n+\t\t\t\tret = true;\n+\t\t\t}\n+\t\t}\n+\t\tplt_spinlock_unlock(&roc_ml->sp_spinlock);\n+\t}\n+\n+\treturn ret;\n+}\n+\n+void\n+roc_ml_scratch_queue_reset(struct roc_ml *roc_ml)\n+{\n+\tif (plt_spinlock_trylock(&roc_ml->sp_spinlock) != 0) {\n+\t\troc_ml_dma_stall_on(roc_ml);\n+\t\troc_ml_clk_force_off(roc_ml);\n+\t\troc_ml_reg_write64(roc_ml, 0, ML_SCRATCH_WORK_PTR);\n+\t\troc_ml_reg_write64(roc_ml, 0, ML_SCRATCH_FW_CTRL);\n+\t\tplt_spinlock_unlock(&roc_ml->sp_spinlock);\n+\t}\n+}\n+\n+bool\n+roc_ml_jcmdq_enqueue_lf(struct roc_ml *roc_ml, struct ml_job_cmd_s *job_cmd)\n+{\n+\tbool ret = false;\n+\n+\tif (FIELD_GET(ROC_ML_JCMDQ_STATUS_AVAIL_COUNT,\n+\t\t roc_ml_reg_read64(roc_ml, ML_JCMDQ_STATUS)) != 0) {\n+\t\troc_ml_reg_write64(roc_ml, job_cmd->w0.u64, ML_JCMDQ_IN(0));\n+\t\troc_ml_reg_write64(roc_ml, job_cmd->w1.u64, ML_JCMDQ_IN(1));\n+\t\tret = true;\n+\t}\n+\n+\treturn ret;\n+}\n+\n+bool\n+roc_ml_jcmdq_enqueue_sl(struct roc_ml *roc_ml, struct ml_job_cmd_s *job_cmd)\n+{\n+\tbool ret = false;\n+\n+\tif (plt_spinlock_trylock(&roc_ml->fp_spinlock) != 0) {\n+\t\tif (FIELD_GET(ROC_ML_JCMDQ_STATUS_AVAIL_COUNT,\n+\t\t\t roc_ml_reg_read64(roc_ml, ML_JCMDQ_STATUS)) != 0) {\n+\t\t\troc_ml_reg_write64(roc_ml, job_cmd->w0.u64, ML_JCMDQ_IN(0));\n+\t\t\troc_ml_reg_write64(roc_ml, job_cmd->w1.u64, ML_JCMDQ_IN(1));\n+\t\t\tret = true;\n+\t\t}\n+\t\tplt_spinlock_unlock(&roc_ml->fp_spinlock);\n+\t}\n+\n+\treturn ret;\n+}\n+\n+void\n+roc_ml_clk_force_on(struct roc_ml *roc_ml)\n+{\n+\tuint64_t reg_val = 0;\n+\n+\treg_val = roc_ml_reg_read64(roc_ml, ML_CFG);\n+\treg_val |= ROC_ML_CFG_MLIP_CLK_FORCE;\n+\troc_ml_reg_write64(roc_ml, reg_val, ML_CFG);\n+}\n+\n+void\n+roc_ml_clk_force_off(struct roc_ml *roc_ml)\n+{\n+\tuint64_t reg_val = 0;\n+\n+\troc_ml_reg_write64(roc_ml, 0, ML_SCRATCH_WORK_PTR);\n+\n+\treg_val = roc_ml_reg_read64(roc_ml, ML_CFG);\n+\treg_val &= ~ROC_ML_CFG_MLIP_CLK_FORCE;\n+\troc_ml_reg_write64(roc_ml, reg_val, ML_CFG);\n+}\n+\n+void\n+roc_ml_dma_stall_on(struct roc_ml *roc_ml)\n+{\n+\tuint64_t reg_val = 0;\n+\n+\treg_val = roc_ml_reg_read64(roc_ml, ML_JOB_MGR_CTRL);\n+\treg_val |= ROC_ML_JOB_MGR_CTRL_STALL_ON_IDLE;\n+\troc_ml_reg_write64(roc_ml, reg_val, ML_JOB_MGR_CTRL);\n+}\n+\n+void\n+roc_ml_dma_stall_off(struct roc_ml *roc_ml)\n+{\n+\tuint64_t reg_val = 0;\n+\n+\treg_val = roc_ml_reg_read64(roc_ml, ML_JOB_MGR_CTRL);\n+\treg_val &= ~ROC_ML_JOB_MGR_CTRL_STALL_ON_IDLE;\n+\troc_ml_reg_write64(roc_ml, reg_val, ML_JOB_MGR_CTRL);\n+}\n+\n+bool\n+roc_ml_mlip_is_enabled(struct roc_ml *roc_ml)\n+{\n+\tuint64_t reg_val;\n+\n+\treg_val = roc_ml_reg_read64(roc_ml, ML_CFG);\n+\n+\tif ((reg_val & ROC_ML_CFG_MLIP_ENA) != 0)\n+\t\treturn true;\n+\n+\treturn false;\n+}\n+\n+int\n+roc_ml_mlip_reset(struct roc_ml *roc_ml, bool force)\n+{\n+\tuint64_t reg_val;\n+\n+\t/* Force reset */\n+\tif (force) {\n+\t\t/* Set ML(0)_CFG[ENA] = 0. */\n+\t\treg_val = roc_ml_reg_read64(roc_ml, ML_CFG);\n+\t\treg_val &= ~ROC_ML_CFG_ENA;\n+\t\troc_ml_reg_write64(roc_ml, reg_val, ML_CFG);\n+\n+\t\t/* Set ML(0)_CFG[MLIP_ENA] = 0. */\n+\t\treg_val = roc_ml_reg_read64(roc_ml, ML_CFG);\n+\t\treg_val &= ~ROC_ML_CFG_MLIP_ENA;\n+\t\troc_ml_reg_write64(roc_ml, reg_val, ML_CFG);\n+\n+\t\t/* Clear ML_MLR_BASE */\n+\t\troc_ml_reg_write64(roc_ml, 0, ML_MLR_BASE);\n+\t}\n+\n+\tif (roc_model_is_cn10ka()) {\n+\t\t/* Wait for all active jobs to finish.\n+\t\t * ML_CFG[ENA] : When set, MLW will accept job commands. This\n+\t\t * bit can be cleared at any time. If [BUSY] is set, software\n+\t\t * must wait until [BUSY] == 0 before setting this bit.\n+\t\t */\n+\t\troc_ml_reg_wait_to_clear(roc_ml, ML_CFG, ROC_ML_CFG_BUSY);\n+\n+\t\t/* (1) Set ML(0)_AXI_BRIDGE_CTRL(0..1)[FENCE] = 1 to instruct\n+\t\t * the AXI bridge not to accept any new transactions from MLIP.\n+\t\t */\n+\t\treg_val = roc_ml_reg_read64(roc_ml, ML_AXI_BRIDGE_CTRL(0));\n+\t\treg_val |= ROC_ML_AXI_BRIDGE_CTRL_FENCE;\n+\t\troc_ml_reg_write64(roc_ml, reg_val, ML_AXI_BRIDGE_CTRL(0));\n+\n+\t\treg_val = roc_ml_reg_read64(roc_ml, ML_AXI_BRIDGE_CTRL(1));\n+\t\treg_val |= ROC_ML_AXI_BRIDGE_CTRL_FENCE;\n+\t\troc_ml_reg_write64(roc_ml, reg_val, ML_AXI_BRIDGE_CTRL(1));\n+\n+\t\t/* (2) Wait until ML(0)_AXI_BRIDGE_CTRL(0..1)[BUSY] = 0 which\n+\t\t * indicates that there is no outstanding transactions on\n+\t\t * AXI-NCB paths.\n+\t\t */\n+\t\troc_ml_reg_wait_to_clear(roc_ml, ML_AXI_BRIDGE_CTRL(0),\n+\t\t\t\t\t ROC_ML_AXI_BRIDGE_CTRL_BUSY);\n+\t\troc_ml_reg_wait_to_clear(roc_ml, ML_AXI_BRIDGE_CTRL(1),\n+\t\t\t\t\t ROC_ML_AXI_BRIDGE_CTRL_BUSY);\n+\n+\t\t/* (3) Wait until ML(0)_JOB_MGR_CTRL[BUSY] = 0 which indicates\n+\t\t * that there are no pending jobs in the MLW's job manager.\n+\t\t */\n+\t\troc_ml_reg_wait_to_clear(roc_ml, ML_JOB_MGR_CTRL, ROC_ML_JOB_MGR_CTRL_BUSY);\n+\n+\t\t/* (4) Set ML(0)_CFG[ENA] = 0. */\n+\t\treg_val = roc_ml_reg_read64(roc_ml, ML_CFG);\n+\t\treg_val &= ~ROC_ML_CFG_ENA;\n+\t\troc_ml_reg_write64(roc_ml, reg_val, ML_CFG);\n+\n+\t\t/* (5) Set ML(0)_CFG[MLIP_ENA] = 0. */\n+\t\treg_val = roc_ml_reg_read64(roc_ml, ML_CFG);\n+\t\treg_val &= ~ROC_ML_CFG_MLIP_ENA;\n+\t\troc_ml_reg_write64(roc_ml, reg_val, ML_CFG);\n+\n+\t\t/* (6) Set ML(0)_AXI_BRIDGE_CTRL(0..1)[FENCE] = 0.*/\n+\t\treg_val = roc_ml_reg_read64(roc_ml, ML_AXI_BRIDGE_CTRL(0));\n+\t\treg_val &= ~ROC_ML_AXI_BRIDGE_CTRL_FENCE;\n+\t\troc_ml_reg_write64(roc_ml, reg_val, ML_AXI_BRIDGE_CTRL(0));\n+\t\troc_ml_reg_write64(roc_ml, reg_val, ML_AXI_BRIDGE_CTRL(1));\n+\t}\n+\n+\tif (roc_model_is_cnf10kb()) {\n+\t\t/* (1) Clear MLAB(0)_CFG[ENA]. Any new jobs will bypass the job\n+\t\t * execution stages and their completions will be returned to\n+\t\t * PSM.\n+\t\t */\n+\t\treg_val = roc_ml_reg_read64(roc_ml, ML_CFG);\n+\t\treg_val &= ~ROC_ML_CFG_ENA;\n+\t\troc_ml_reg_write64(roc_ml, reg_val, ML_CFG);\n+\n+\t\t/* (2) Quiesce the ACC and DMA AXI interfaces: For each of the\n+\t\t * two MLAB(0)_AXI_BRIDGE_CTRL(0..1) registers:\n+\t\t *\n+\t\t * (a) Set MLAB(0)_AXI_BRIDGE_CTRL(0..1)[FENCE] to block new AXI\n+\t\t * commands from MLIP.\n+\t\t *\n+\t\t * (b) Poll MLAB(0)_AXI_BRIDGE_CTRL(0..1)[BUSY] == 0.\n+\t\t */\n+\t\treg_val = roc_ml_reg_read64(roc_ml, ML_AXI_BRIDGE_CTRL(0));\n+\t\treg_val |= ROC_ML_AXI_BRIDGE_CTRL_FENCE;\n+\t\troc_ml_reg_write64(roc_ml, reg_val, ML_AXI_BRIDGE_CTRL(0));\n+\n+\t\troc_ml_reg_wait_to_clear(roc_ml, ML_AXI_BRIDGE_CTRL(0),\n+\t\t\t\t\t ROC_ML_AXI_BRIDGE_CTRL_BUSY);\n+\n+\t\treg_val = roc_ml_reg_read64(roc_ml, ML_AXI_BRIDGE_CTRL(1));\n+\t\treg_val |= ROC_ML_AXI_BRIDGE_CTRL_FENCE;\n+\t\troc_ml_reg_write64(roc_ml, reg_val, ML_AXI_BRIDGE_CTRL(1));\n+\n+\t\troc_ml_reg_wait_to_clear(roc_ml, ML_AXI_BRIDGE_CTRL(1),\n+\t\t\t\t\t ROC_ML_AXI_BRIDGE_CTRL_BUSY);\n+\n+\t\t/* (3) Clear MLAB(0)_CFG[MLIP_ENA] to reset MLIP.\n+\t\t */\n+\t\treg_val = roc_ml_reg_read64(roc_ml, ML_CFG);\n+\t\treg_val &= ~ROC_ML_CFG_MLIP_ENA;\n+\t\troc_ml_reg_write64(roc_ml, reg_val, ML_CFG);\n+\n+cnf10kb_mlip_reset_stage_4a:\n+\t\t/* (4) Flush any outstanding jobs in MLAB's job execution\n+\t\t * stages:\n+\t\t *\n+\t\t * (a) Wait for completion stage to clear:\n+\t\t * - Poll MLAB(0)_STG(0..2)_STATUS[VALID] == 0.\n+\t\t */\n+\t\troc_ml_reg_wait_to_clear(roc_ml, ML_STGX_STATUS(0), ROC_ML_STG_STATUS_VALID);\n+\t\troc_ml_reg_wait_to_clear(roc_ml, ML_STGX_STATUS(1), ROC_ML_STG_STATUS_VALID);\n+\t\troc_ml_reg_wait_to_clear(roc_ml, ML_STGX_STATUS(2), ROC_ML_STG_STATUS_VALID);\n+\n+cnf10kb_mlip_reset_stage_4b:\n+\t\t/* (4b) Clear job run stage: Poll\n+\t\t * MLAB(0)_STG_CONTROL[RUN_TO_COMP] == 0.\n+\t\t */\n+\t\troc_ml_reg_wait_to_clear(roc_ml, ML_STG_CONTROL, ROC_ML_STG_CONTROL_RUN_TO_COMP);\n+\n+\t\t/* (4b) Clear job run stage: If MLAB(0)_STG(1)_STATUS[VALID] ==\n+\t\t * 1:\n+\t\t * - Set MLAB(0)_STG_CONTROL[RUN_TO_COMP].\n+\t\t * - Poll MLAB(0)_STG_CONTROL[RUN_TO_COMP] == 0.\n+\t\t * - Repeat step (a) to clear job completion stage.\n+\t\t */\n+\t\treg_val = roc_ml_reg_read64(roc_ml, ML_STGX_STATUS(1));\n+\t\tif (reg_val & ROC_ML_STG_STATUS_VALID) {\n+\t\t\treg_val = roc_ml_reg_read64(roc_ml, ML_STG_CONTROL);\n+\t\t\treg_val |= ROC_ML_STG_CONTROL_RUN_TO_COMP;\n+\t\t\troc_ml_reg_write64(roc_ml, reg_val, ML_STG_CONTROL);\n+\n+\t\t\troc_ml_reg_wait_to_clear(roc_ml, ML_STG_CONTROL,\n+\t\t\t\t\t\t ROC_ML_STG_CONTROL_RUN_TO_COMP);\n+\n+\t\t\tgoto cnf10kb_mlip_reset_stage_4a;\n+\t\t}\n+\n+\t\t/* (4c) Clear job fetch stage: Poll\n+\t\t * MLAB(0)_STG_CONTROL[FETCH_TO_RUN] == 0.\n+\t\t */\n+\t\troc_ml_reg_wait_to_clear(roc_ml, ML_STG_CONTROL, ROC_ML_STG_CONTROL_FETCH_TO_RUN);\n+\n+\t\t/* (4c) Clear job fetch stage: If\n+\t\t * MLAB(0)_STG(0..2)_STATUS[VALID] == 1:\n+\t\t * - Set MLAB(0)_STG_CONTROL[FETCH_TO_RUN].\n+\t\t * - Poll MLAB(0)_STG_CONTROL[FETCH_TO_RUN] == 0.\n+\t\t * - Repeat step (b) to clear job run and completion stages.\n+\t\t */\n+\t\treg_val = (roc_ml_reg_read64(roc_ml, ML_STGX_STATUS(0)) |\n+\t\t\t roc_ml_reg_read64(roc_ml, ML_STGX_STATUS(1)) |\n+\t\t\t roc_ml_reg_read64(roc_ml, ML_STGX_STATUS(2)));\n+\n+\t\tif (reg_val & ROC_ML_STG_STATUS_VALID) {\n+\t\t\treg_val = roc_ml_reg_read64(roc_ml, ML_STG_CONTROL);\n+\t\t\treg_val |= ROC_ML_STG_CONTROL_RUN_TO_COMP;\n+\t\t\troc_ml_reg_write64(roc_ml, reg_val, ML_STG_CONTROL);\n+\n+\t\t\troc_ml_reg_wait_to_clear(roc_ml, ML_STG_CONTROL,\n+\t\t\t\t\t\t ROC_ML_STG_CONTROL_RUN_TO_COMP);\n+\n+\t\t\tgoto cnf10kb_mlip_reset_stage_4b;\n+\t\t}\n+\n+\t\t/* (5) Reset the ACC and DMA AXI interfaces: For each of the two\n+\t\t * MLAB(0)_AXI_BRIDGE_CTRL(0..1) registers:\n+\t\t *\n+\t\t * (5a) Set and then clear\n+\t\t * MLAB(0)_AXI_BRIDGE_CTRL(0..1)[FLUSH_WRITE_DATA].\n+\t\t *\n+\t\t * (5b) Clear MLAB(0)_AXI_BRIDGE_CTRL(0..1)[FENCE].\n+\t\t */\n+\t\treg_val = roc_ml_reg_read64(roc_ml, ML_AXI_BRIDGE_CTRL(0));\n+\t\treg_val |= ROC_ML_AXI_BRIDGE_CTRL_FLUSH_WRITE_DATA;\n+\t\troc_ml_reg_write64(roc_ml, reg_val, ML_AXI_BRIDGE_CTRL(0));\n+\n+\t\treg_val = roc_ml_reg_read64(roc_ml, ML_AXI_BRIDGE_CTRL(0));\n+\t\treg_val &= ~ROC_ML_AXI_BRIDGE_CTRL_FLUSH_WRITE_DATA;\n+\t\troc_ml_reg_write64(roc_ml, reg_val, ML_AXI_BRIDGE_CTRL(0));\n+\n+\t\treg_val = roc_ml_reg_read64(roc_ml, ML_AXI_BRIDGE_CTRL(0));\n+\t\treg_val &= ~ROC_ML_AXI_BRIDGE_CTRL_FENCE;\n+\t\troc_ml_reg_write64(roc_ml, reg_val, ML_AXI_BRIDGE_CTRL(0));\n+\n+\t\treg_val = roc_ml_reg_read64(roc_ml, ML_AXI_BRIDGE_CTRL(1));\n+\t\treg_val |= ROC_ML_AXI_BRIDGE_CTRL_FLUSH_WRITE_DATA;\n+\t\troc_ml_reg_write64(roc_ml, reg_val, ML_AXI_BRIDGE_CTRL(1));\n+\n+\t\treg_val = roc_ml_reg_read64(roc_ml, ML_AXI_BRIDGE_CTRL(1));\n+\t\treg_val &= ~ROC_ML_AXI_BRIDGE_CTRL_FLUSH_WRITE_DATA;\n+\t\troc_ml_reg_write64(roc_ml, reg_val, ML_AXI_BRIDGE_CTRL(1));\n+\n+\t\treg_val = roc_ml_reg_read64(roc_ml, ML_AXI_BRIDGE_CTRL(1));\n+\t\treg_val &= ~ROC_ML_AXI_BRIDGE_CTRL_FENCE;\n+\t\troc_ml_reg_write64(roc_ml, reg_val, ML_AXI_BRIDGE_CTRL(1));\n+\t}\n+\n+\treturn 0;\n+}\n+\n+int\n+roc_ml_dev_init(struct roc_ml *roc_ml)\n+{\n+\tstruct plt_pci_device *pci_dev;\n+\tstruct dev *dev;\n+\tstruct ml *ml;\n+\n+\tif (roc_ml == NULL || roc_ml->pci_dev == NULL)\n+\t\treturn -EINVAL;\n+\n+\tPLT_STATIC_ASSERT(sizeof(struct ml) <= ROC_ML_MEM_SZ);\n+\n+\tml = roc_ml_to_ml_priv(roc_ml);\n+\tmemset(ml, 0, sizeof(*ml));\n+\tpci_dev = roc_ml->pci_dev;\n+\tdev = &ml->dev;\n+\n+\tml->pci_dev = pci_dev;\n+\tdev->roc_ml = roc_ml;\n+\n+\tml->ml_reg_addr = ml->pci_dev->mem_resource[0].addr;\n+\tml->ml_mlr_base = 0;\n+\tml->ml_mlr_base_saved = false;\n+\n+\tplt_ml_dbg(\"ML: PCI Physical Address : 0x%016lx\", ml->pci_dev->mem_resource[0].phys_addr);\n+\tplt_ml_dbg(\"ML: PCI Virtual Address : 0x%016lx\",\n+\t\t PLT_U64_CAST(ml->pci_dev->mem_resource[0].addr));\n+\n+\tplt_spinlock_init(&roc_ml->sp_spinlock);\n+\tplt_spinlock_init(&roc_ml->fp_spinlock);\n+\n+\treturn 0;\n+}\n+\n+int\n+roc_ml_dev_fini(struct roc_ml *roc_ml)\n+{\n+\tstruct ml *ml = roc_ml_to_ml_priv(roc_ml);\n+\n+\tif (ml == NULL)\n+\t\treturn -EINVAL;\n+\n+\treturn 0;\n+}\n+\n+int\n+roc_ml_blk_init(struct roc_bphy *roc_bphy, struct roc_ml *roc_ml)\n+{\n+\tstruct dev *dev;\n+\tstruct ml *ml;\n+\n+\tif ((roc_ml == NULL) || (roc_bphy == NULL))\n+\t\treturn -EINVAL;\n+\n+\tPLT_STATIC_ASSERT(sizeof(struct ml) <= ROC_ML_MEM_SZ);\n+\n+\tml = roc_ml_to_ml_priv(roc_ml);\n+\tmemset(ml, 0, sizeof(*ml));\n+\n+\tdev = &ml->dev;\n+\n+\tml->pci_dev = roc_bphy->pci_dev;\n+\tdev->roc_ml = roc_ml;\n+\n+\tplt_ml_dbg(\n+\t\t\"MLAB: Physical Address : 0x%016lx\",\n+\t\tPLT_PTR_ADD_U64_CAST(ml->pci_dev->mem_resource[0].phys_addr, ML_MLAB_BLK_OFFSET));\n+\tplt_ml_dbg(\"MLAB: Virtual Address : 0x%016lx\",\n+\t\t PLT_PTR_ADD_U64_CAST(ml->pci_dev->mem_resource[0].addr, ML_MLAB_BLK_OFFSET));\n+\n+\tml->ml_reg_addr = PLT_PTR_ADD(ml->pci_dev->mem_resource[0].addr, ML_MLAB_BLK_OFFSET);\n+\tml->ml_mlr_base = 0;\n+\tml->ml_mlr_base_saved = false;\n+\n+\tplt_spinlock_init(&roc_ml->sp_spinlock);\n+\tplt_spinlock_init(&roc_ml->fp_spinlock);\n+\n+\treturn 0;\n+}\n+\n+int\n+roc_ml_blk_fini(struct roc_bphy *roc_bphy, struct roc_ml *roc_ml)\n+{\n+\tstruct ml *ml;\n+\n+\tif ((roc_ml == NULL) || (roc_bphy == NULL))\n+\t\treturn -EINVAL;\n+\n+\tml = roc_ml_to_ml_priv(roc_ml);\n+\n+\tif (ml == NULL)\n+\t\treturn -EINVAL;\n+\n+\treturn 0;\n+}\n+\n+uint16_t\n+roc_ml_sso_pf_func_get(void)\n+{\n+\treturn idev_sso_pffunc_get();\n+}\ndiff --git a/drivers/common/cnxk/roc_ml.h b/drivers/common/cnxk/roc_ml.h\nnew file mode 100644\nindex 0000000000..3cd82be6a6\n--- /dev/null\n+++ b/drivers/common/cnxk/roc_ml.h\n@@ -0,0 +1,152 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright (c) 2022 Marvell.\n+ */\n+\n+#ifndef _ROC_ML_H_\n+#define _ROC_ML_H_\n+\n+#include \"roc_api.h\"\n+\n+#define ROC_ML_MEM_SZ\t (6 * 1024)\n+#define ROC_ML_TIMEOUT_MS 10000\n+\n+/* ML_CFG */\n+#define ROC_ML_CFG_JD_SIZE\t GENMASK_ULL(1, 0)\n+#define ROC_ML_CFG_MLIP_ENA\t BIT_ULL(2)\n+#define ROC_ML_CFG_BUSY\t\t BIT_ULL(3)\n+#define ROC_ML_CFG_WRAP_CLK_FORCE BIT_ULL(4)\n+#define ROC_ML_CFG_MLIP_CLK_FORCE BIT_ULL(5)\n+#define ROC_ML_CFG_ENA\t\t BIT_ULL(6)\n+\n+/* ML_MLR_BASE */\n+#define ROC_ML_MLR_BASE_BASE GENMASK_ULL(51, 0)\n+\n+/* ML_STG_STATUS */\n+#define ROC_ML_STG_STATUS_VALID\t\tBIT_ULL(0)\n+#define ROC_ML_STG_STATUS_ADDR_ERR\tBIT_ULL(1)\n+#define ROC_ML_STG_STATUS_DMA_ERR\tBIT_ULL(2)\n+#define ROC_ML_STG_STATUS_TIMEOUT\tBIT_ULL(3)\n+#define ROC_ML_STG_STATUS_NFAT_ERR\tBIT_ULL(4)\n+#define ROC_ML_STG_STATUS_JOB_ERR\tBIT_ULL(5)\n+#define ROC_ML_STG_STATUS_ELAPSED_TICKS GENMASK_ULL(47, 6)\n+\n+/* ML_STG_CONTROL */\n+#define ROC_ML_STG_CONTROL_FETCH_TO_RUN BIT_ULL(0)\n+#define ROC_ML_STG_CONTROL_RUN_TO_COMP\tBIT_ULL(1)\n+\n+/* ML_AXI_BRIDGE */\n+#define ROC_ML_AXI_BRIDGE_CTRL_AXI_RESP_CTRL\t BIT_ULL(0)\n+#define ROC_ML_AXI_BRIDGE_CTRL_BRIDGE_CTRL_MODE\t BIT_ULL(1)\n+#define ROC_ML_AXI_BRIDGE_CTRL_FORCE_AXI_ID\t GENMASK_ULL(11, 2)\n+#define ROC_ML_AXI_BRIDGE_CTRL_CSR_WR_BLK\t BIT_ULL(13)\n+#define ROC_ML_AXI_BRIDGE_CTRL_NCB_WR_BLK\t BIT_ULL(14)\n+#define ROC_ML_AXI_BRIDGE_CTRL_CSR_RD_BLK\t BIT_ULL(15)\n+#define ROC_ML_AXI_BRIDGE_CTRL_NCB_RD_BLK\t BIT_ULL(16)\n+#define ROC_ML_AXI_BRIDGE_CTRL_FENCE\t\t BIT_ULL(17)\n+#define ROC_ML_AXI_BRIDGE_CTRL_BUSY\t\t BIT_ULL(18)\n+#define ROC_ML_AXI_BRIDGE_CTRL_FORCE_WRESP_OK\t BIT_ULL(19)\n+#define ROC_ML_AXI_BRIDGE_CTRL_FORCE_RRESP_OK\t BIT_ULL(20)\n+#define ROC_ML_AXI_BRIDGE_CTRL_CSR_FORCE_CMPLT\t BIT_ULL(21)\n+#define ROC_ML_AXI_BRIDGE_CTRL_WR_CNT_GEAR\t GENMASK_ULL(25, 22)\n+#define ROC_ML_AXI_BRIDGE_CTRL_RD_GEAR\t\t GENMASK_ULL(28, 26)\n+#define ROC_ML_AXI_BRIDGE_CTRL_CSR_CUTTHROUGH_MODE BIT_ULL(29)\n+#define ROC_ML_AXI_BRIDGE_CTRL_GAA_WRITE_CREDITS GENMASK_ULL(33, 30)\n+#define ROC_ML_AXI_BRIDGE_CTRL_GAA_READ_CREDITS\t GENMASK_ULL(37, 34)\n+#define ROC_ML_AXI_BRIDGE_CTRL_GAA_LOAD_WRITE_CREDITS BIT_ULL(38)\n+#define ROC_ML_AXI_BRIDGE_CTRL_GAA_LOAD_READ_CREDITS BIT_ULL(39)\n+#define ROC_ML_AXI_BRIDGE_CTRL_FLUSH_WRITE_DATA\t BIT_ULL(40)\n+\n+/* ML_JOB_MGR_CTRL */\n+#define ROC_ML_JOB_MGR_CTRL_STALL_ON_ERR BIT_ULL(0)\n+#define ROC_ML_JOB_MGR_CTRL_PF_OVERRIDE\t BIT_ULL(1)\n+#define ROC_ML_JOB_MGR_CTRL_PF_FUNC_OVERRIDE GENMASK_ULL(19, 4)\n+#define ROC_ML_JOB_MGR_CTRL_BUSY\t BIT_ULL(20)\n+#define ROC_ML_JOB_MGR_CTRL_STALL_ON_IDLE BIT_ULL(21)\n+\n+/* ML_JCMDQ_STATUS */\n+#define ROC_ML_JCMDQ_STATUS_AVAIL_COUNT GENMASK_ULL(4, 0)\n+\n+/* ML_ANBX_BACKP_DISABLE */\n+#define ROC_ML_ANBX_BACKP_DISABLE_EXTMSTR_B_BACKP_DISABLE BIT_ULL(0)\n+#define ROC_ML_ANBX_BACKP_DISABLE_EXTMSTR_R_BACKP_DISABLE BIT_ULL(1)\n+\n+/* ML_ANBX_NCBI_P_OVR */\n+#define ML_ANBX_NCBI_P_OVR_ANB_NCBI_P_MSH_DST_OVR_VLD\t BIT_ULL(0)\n+#define ML_ANBX_NCBI_P_OVR_ANB_NCBI_P_MSH_DST_OVR\t GENMASK_ULL(11, 1)\n+#define ML_ANBX_NCBI_P_OVR_ANB_NCBI_P_NS_OVR_VLD\t BIT_ULL(12)\n+#define ML_ANBX_NCBI_P_OVR_ANB_NCBI_P_NS_OVR\t\t BIT_ULL(13)\n+#define ML_ANBX_NCBI_P_OVR_ANB_NCBI_P_PADDR_OVR_VLD\t BIT_ULL(14)\n+#define ML_ANBX_NCBI_P_OVR_ANB_NCBI_P_PADDR_OVR\t\t BIT_ULL(15)\n+#define ML_ANBX_NCBI_P_OVR_ANB_NCBI_P_RO_OVR_VLD\t BIT_ULL(16)\n+#define ML_ANBX_NCBI_P_OVR_ANB_NCBI_P_RO_OVR\t\t BIT_ULL(17)\n+#define ML_ANBX_NCBI_P_OVR_ANB_NCBI_P_MPADID_VAL_OVR_VLD BIT_ULL(18)\n+#define ML_ANBX_NCBI_P_OVR_ANB_NCBI_P_MPADID_VAL_OVR\t BIT_ULL(19)\n+#define ML_ANBX_NCBI_P_OVR_ANB_NCBI_P_MPAMDID_OVR_VLD\t BIT_ULL(20)\n+#define ML_ANBX_NCBI_P_OVR_ANB_NCBI_P_MPAMDID_OVR\t BIT_ULL(21)\n+\n+/* ML_ANBX_NCBI_NP_OVR */\n+#define ML_ANBX_NCBI_NP_OVR_ANB_NCBI_NP_MSH_DST_OVR_VLD\t BIT_ULL(0)\n+#define ML_ANBX_NCBI_NP_OVR_ANB_NCBI_NP_MSH_DST_OVR\t GENMASK_ULL(11, 1)\n+#define ML_ANBX_NCBI_NP_OVR_ANB_NCBI_NP_NS_OVR_VLD\t BIT_ULL(12)\n+#define ML_ANBX_NCBI_NP_OVR_ANB_NCBI_NP_NS_OVR\t\t BIT_ULL(13)\n+#define ML_ANBX_NCBI_NP_OVR_ANB_NCBI_NP_PADDR_OVR_VLD\t BIT_ULL(14)\n+#define ML_ANBX_NCBI_NP_OVR_ANB_NCBI_NP_PADDR_OVR\t BIT_ULL(15)\n+#define ML_ANBX_NCBI_NP_OVR_ANB_NCBI_NP_RO_OVR_VLD\t BIT_ULL(16)\n+#define ML_ANBX_NCBI_NP_OVR_ANB_NCBI_NP_RO_OVR\t\t BIT_ULL(17)\n+#define ML_ANBX_NCBI_NP_OVR_ANB_NCBI_NP_MPADID_VAL_OVR_VLD BIT_ULL(18)\n+#define ML_ANBX_NCBI_NP_OVR_ANB_NCBI_NP_MPADID_VAL_OVR\t BIT_ULL(19)\n+#define ML_ANBX_NCBI_NP_OVR_ANB_NCBI_NP_MPAMDID_OVR_VLD\t BIT_ULL(20)\n+#define ML_ANBX_NCBI_NP_OVR_ANB_NCBI_NP_MPAMDID_OVR\t BIT_ULL(21)\n+\n+/* ML_SW_RST_CTRL */\n+#define ROC_ML_SW_RST_CTRL_ACC_RST BIT_ULL(0)\n+#define ROC_ML_SW_RST_CTRL_CMPC_RST BIT_ULL(1)\n+\n+struct roc_ml {\n+\tstruct plt_pci_device *pci_dev;\n+\tplt_spinlock_t sp_spinlock;\n+\tplt_spinlock_t fp_spinlock;\n+\tuint8_t reserved[ROC_ML_MEM_SZ] __plt_cache_aligned;\n+} __plt_cache_aligned;\n+\n+/* Register read and write functions */\n+uint64_t __roc_api roc_ml_reg_read64(struct roc_ml *roc_ml, uint64_t offset);\n+void __roc_api roc_ml_reg_write64(struct roc_ml *roc_ml, uint64_t val, uint64_t offset);\n+uint32_t __roc_api roc_ml_reg_read32(struct roc_ml *roc_ml, uint64_t offset);\n+void __roc_api roc_ml_reg_write32(struct roc_ml *roc_ml, uint32_t val, uint64_t offset);\n+void __roc_api roc_ml_reg_save(struct roc_ml *roc_ml, uint64_t offset);\n+\n+/* Address translation functions */\n+uint64_t __roc_api roc_ml_addr_pa_to_offset(struct roc_ml *roc_ml, uint64_t phys_addr);\n+uint64_t __roc_api roc_ml_addr_offset_to_pa(struct roc_ml *roc_ml, uint64_t offset);\n+void *__roc_api roc_ml_addr_ap2mlip(struct roc_ml *roc_ml, void *addr);\n+void *__roc_api roc_ml_addr_mlip2ap(struct roc_ml *roc_ml, void *addr);\n+\n+/* Scratch and JCMDQ functions */\n+void __roc_api roc_ml_scratch_write_job(struct roc_ml *roc_ml, void *jd);\n+bool __roc_api roc_ml_scratch_is_valid_bit_set(struct roc_ml *roc_ml);\n+bool __roc_api roc_ml_scratch_is_done_bit_set(struct roc_ml *roc_ml);\n+bool __roc_api roc_ml_scratch_enqueue(struct roc_ml *roc_ml, void *work_ptr);\n+bool __roc_api roc_ml_scratch_dequeue(struct roc_ml *roc_ml, void *work_ptr);\n+void __roc_api roc_ml_scratch_queue_reset(struct roc_ml *roc_ml);\n+bool __roc_api roc_ml_jcmdq_enqueue_lf(struct roc_ml *roc_ml, struct ml_job_cmd_s *job_cmd);\n+bool __roc_api roc_ml_jcmdq_enqueue_sl(struct roc_ml *roc_ml, struct ml_job_cmd_s *job_cmd);\n+\n+/* Device management functions */\n+void __roc_api roc_ml_clk_force_on(struct roc_ml *roc_ml);\n+void __roc_api roc_ml_clk_force_off(struct roc_ml *roc_ml);\n+void __roc_api roc_ml_dma_stall_on(struct roc_ml *roc_ml);\n+void __roc_api roc_ml_dma_stall_off(struct roc_ml *roc_ml);\n+bool __roc_api roc_ml_mlip_is_enabled(struct roc_ml *roc_ml);\n+int __roc_api roc_ml_mlip_reset(struct roc_ml *roc_ml, bool force);\n+\n+/* Device / block functions */\n+int __roc_api roc_ml_dev_init(struct roc_ml *roc_ml);\n+int __roc_api roc_ml_dev_fini(struct roc_ml *roc_ml);\n+int __roc_api roc_ml_blk_init(struct roc_bphy *roc_bphy, struct roc_ml *roc_ml);\n+int __roc_api roc_ml_blk_fini(struct roc_bphy *roc_bphy, struct roc_ml *roc_ml);\n+\n+/* Utility functions */\n+uint16_t __roc_api roc_ml_sso_pf_func_get(void);\n+\n+#endif /*_ROC_ML_H_*/\ndiff --git a/drivers/common/cnxk/roc_ml_priv.h b/drivers/common/cnxk/roc_ml_priv.h\nnew file mode 100644\nindex 0000000000..ad5fe90bab\n--- /dev/null\n+++ b/drivers/common/cnxk/roc_ml_priv.h\n@@ -0,0 +1,24 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright (c) 2022 Marvell.\n+ */\n+\n+#ifndef _ROC_ML_PRIV_H_\n+#define _ROC_ML_PRIV_H_\n+\n+#include \"roc_api.h\"\n+\n+struct ml {\n+\tstruct plt_pci_device *pci_dev;\n+\tstruct dev dev;\n+\tuint8_t *ml_reg_addr;\n+\tuint64_t ml_mlr_base;\n+\tbool ml_mlr_base_saved;\n+} __plt_cache_aligned;\n+\n+static inline struct ml *\n+roc_ml_to_ml_priv(struct roc_ml *roc_ml)\n+{\n+\treturn (struct ml *)&roc_ml->reserved[0];\n+}\n+\n+#endif /* _ROC_ML_PRIV_H_ */\ndiff --git a/drivers/common/cnxk/roc_platform.c b/drivers/common/cnxk/roc_platform.c\nindex ce0f9b870c..f91b95ceab 100644\n--- a/drivers/common/cnxk/roc_platform.c\n+++ b/drivers/common/cnxk/roc_platform.c\n@@ -63,6 +63,7 @@ roc_plt_init(void)\n RTE_LOG_REGISTER(cnxk_logtype_base, pmd.cnxk.base, NOTICE);\n RTE_LOG_REGISTER(cnxk_logtype_mbox, pmd.cnxk.mbox, NOTICE);\n RTE_LOG_REGISTER(cnxk_logtype_cpt, pmd.crypto.cnxk, NOTICE);\n+RTE_LOG_REGISTER(cnxk_logtype_ml, pmd.ml.cnxk, NOTICE);\n RTE_LOG_REGISTER(cnxk_logtype_npa, pmd.mempool.cnxk, NOTICE);\n RTE_LOG_REGISTER(cnxk_logtype_nix, pmd.net.cnxk, NOTICE);\n RTE_LOG_REGISTER(cnxk_logtype_npc, pmd.net.cnxk.flow, NOTICE);\ndiff --git a/drivers/common/cnxk/roc_platform.h b/drivers/common/cnxk/roc_platform.h\nindex 8ba28e69fa..59a422eb9d 100644\n--- a/drivers/common/cnxk/roc_platform.h\n+++ b/drivers/common/cnxk/roc_platform.h\n@@ -234,6 +234,7 @@\n extern int cnxk_logtype_base;\n extern int cnxk_logtype_mbox;\n extern int cnxk_logtype_cpt;\n+extern int cnxk_logtype_ml;\n extern int cnxk_logtype_npa;\n extern int cnxk_logtype_nix;\n extern int cnxk_logtype_npc;\n@@ -261,6 +262,7 @@ extern int cnxk_logtype_ree;\n #define plt_base_dbg(fmt, ...)\tplt_dbg(base, fmt, ##__VA_ARGS__)\n #define plt_cpt_dbg(fmt, ...)\tplt_dbg(cpt, fmt, ##__VA_ARGS__)\n #define plt_mbox_dbg(fmt, ...)\tplt_dbg(mbox, fmt, ##__VA_ARGS__)\n+#define plt_ml_dbg(fmt, ...)\tplt_dbg(ml, fmt, ##__VA_ARGS__)\n #define plt_npa_dbg(fmt, ...)\tplt_dbg(npa, fmt, ##__VA_ARGS__)\n #define plt_nix_dbg(fmt, ...)\tplt_dbg(nix, fmt, ##__VA_ARGS__)\n #define plt_npc_dbg(fmt, ...)\tplt_dbg(npc, fmt, ##__VA_ARGS__)\ndiff --git a/drivers/common/cnxk/roc_priv.h b/drivers/common/cnxk/roc_priv.h\nindex 122d411fe7..14fe2e452a 100644\n--- a/drivers/common/cnxk/roc_priv.h\n+++ b/drivers/common/cnxk/roc_priv.h\n@@ -47,4 +47,7 @@\n /* REE */\n #include \"roc_ree_priv.h\"\n\n+/* ML */\n+#include \"roc_ml_priv.h\"\n+\n #endif /* _ROC_PRIV_H_ */\ndiff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map\nindex ee283d2392..c1c8542b1a 100644\n--- a/drivers/common/cnxk/version.map\n+++ b/drivers/common/cnxk/version.map\n@@ -8,6 +8,7 @@ INTERNAL {\n \tcnxk_logtype_base;\n \tcnxk_logtype_cpt;\n \tcnxk_logtype_mbox;\n+\tcnxk_logtype_ml;\n \tcnxk_logtype_nix;\n \tcnxk_logtype_npa;\n \tcnxk_logtype_npc;\n@@ -96,6 +97,34 @@ INTERNAL {\n \troc_idev_npa_nix_get;\n \troc_idev_num_lmtlines_get;\n \troc_idev_nix_inl_meta_aura_get;\n+\troc_ml_reg_read64;\n+\troc_ml_reg_write64;\n+\troc_ml_reg_read32;\n+\troc_ml_reg_write32;\n+\troc_ml_reg_save;\n+\troc_ml_addr_ap2mlip;\n+\troc_ml_addr_mlip2ap;\n+\troc_ml_addr_pa_to_offset;\n+\troc_ml_addr_offset_to_pa;\n+\troc_ml_scratch_write_job;\n+\troc_ml_scratch_is_valid_bit_set;\n+\troc_ml_scratch_is_done_bit_set;\n+\troc_ml_scratch_enqueue;\n+\troc_ml_scratch_dequeue;\n+\troc_ml_scratch_queue_reset;\n+\troc_ml_jcmdq_enqueue_lf;\n+\troc_ml_jcmdq_enqueue_sl;\n+\troc_ml_clk_force_on;\n+\troc_ml_clk_force_off;\n+\troc_ml_dma_stall_on;\n+\troc_ml_dma_stall_off;\n+\troc_ml_mlip_is_enabled;\n+\troc_ml_mlip_reset;\n+\troc_ml_dev_init;\n+\troc_ml_dev_fini;\n+\troc_ml_blk_init;\n+\troc_ml_blk_fini;\n+\troc_ml_sso_pf_func_get;\n \troc_model;\n \troc_se_auth_key_set;\n \troc_se_ciph_key_set;\n", "prefixes": [ "v4", "01/39" ] }