Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/122686/?format=api
{ "id": 122686, "url": "http://patches.dpdk.org/api/patches/122686/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20230130132000.1715473-6-rongweil@nvidia.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20230130132000.1715473-6-rongweil@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20230130132000.1715473-6-rongweil@nvidia.com", "date": "2023-01-30T13:19:54", "name": "[v3,05/11] net/mlx5: adopt new flex item prm definition", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "2d8a2491ee5cb6a643b39ae9002d035aefec37ce", "submitter": { "id": 2223, "url": "http://patches.dpdk.org/api/people/2223/?format=api", "name": "Rongwei Liu", "email": "rongweil@nvidia.com" }, "delegate": { "id": 319, "url": "http://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20230130132000.1715473-6-rongweil@nvidia.com/mbox/", "series": [ { "id": 26693, "url": "http://patches.dpdk.org/api/series/26693/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=26693", "date": "2023-01-30T13:19:50", "name": "[v3,01/11] ethdev: add flex item modify field support", "version": 3, "mbox": "http://patches.dpdk.org/series/26693/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/122686/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/122686/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 9BDA341B81;\n\tMon, 30 Jan 2023 14:21:00 +0100 (CET)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id D47CC42D0D;\n\tMon, 30 Jan 2023 14:20:44 +0100 (CET)", "from NAM10-MW2-obe.outbound.protection.outlook.com\n (mail-mw2nam10on2049.outbound.protection.outlook.com [40.107.94.49])\n by mails.dpdk.org (Postfix) with ESMTP id 203CD42D0D\n for <dev@dpdk.org>; Mon, 30 Jan 2023 14:20:44 +0100 (CET)", "from BN8PR04CA0047.namprd04.prod.outlook.com (2603:10b6:408:d4::21)\n by MN2PR12MB4520.namprd12.prod.outlook.com (2603:10b6:208:26f::15)\n with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6043.36; Mon, 30 Jan\n 2023 13:20:41 +0000", "from BN8NAM11FT031.eop-nam11.prod.protection.outlook.com\n (2603:10b6:408:d4:cafe::af) by BN8PR04CA0047.outlook.office365.com\n (2603:10b6:408:d4::21) with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6043.36 via Frontend\n Transport; Mon, 30 Jan 2023 13:20:40 +0000", "from mail.nvidia.com (216.228.117.160) by\n BN8NAM11FT031.mail.protection.outlook.com (10.13.177.25) with Microsoft SMTP\n Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id\n 15.20.6043.36 via Frontend Transport; Mon, 30 Jan 2023 13:20:39 +0000", "from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com\n (10.129.200.66) with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.36; Mon, 30 Jan\n 2023 05:20:28 -0800", "from nvidia.com (10.126.231.37) by rnnvmail201.nvidia.com\n (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.36; Mon, 30 Jan\n 2023 05:20:26 -0800" ], "ARC-Seal": "i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none;\n b=IDG8fDllsqJmRsNyOxb2/Emdp86I2FW/marAyPPx1LJsscSgtf+NIfY+pkykvsCNpvq+O21Rz3w6rLYjvbz18ZDynTBPEXBTgCX87wUBMwZja9SuKhKVY7uwE1N5gyF09kAKkSdu7RCR9W4Jv90qhxFIFZjhH6mDFOszhiifMPyZksr6en6Ap+am1cNbQguPwbqgEBHYKzgJo/KInzu5v54e6Ba0H6B14jno20mUP30SzOM0TGgxcLO4zQXIPV4zS1i7Sc4WTupQLbYbFXSV/yuAKcM3BZqRkVvwnk59M++y1w0KRrwO5RAEV6pZaVhBtkn7Q/Ua5sjWJMdIUuH3iQ==", "ARC-Message-Signature": "i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com;\n s=arcselector9901;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1;\n bh=ntm7F6qM4MuksLXB12yACRJYS/MoKv4IQ7qd2Kh/P5s=;\n b=UxYA489ZC4jhtmoz+V5Iw6IvcuIsnO1jz86D8t0eVmfwPKB2e5BAjN7WqIcD2J+Dbw4SekZW23tVYfpJlgbo47jKjlZ/cyxRkKGt2e/uFE8v7Zhing0dlrQ/QRyJ1RDGWWI/gAFo/JckZhPPz+gvImPtbeADRcgTEdzyI/pLKZMoxWaaRiJswk9K/4EXkc5zN3PzL/qHa5Uq3ijy2lXw7kba/5XQL0r1hI9adpp7RcEEm7hBlxqCsAha0reYP/vUFOI68nPJ9rcbl60e6DKPSiaZKG6GmoOedIkzJd0UK4iFp+YtHdXGroMUpSgzaaco4X8iTqAwCvdYKeMMdCe1rw==", "ARC-Authentication-Results": "i=1; mx.microsoft.com 1; spf=pass (sender ip is\n 216.228.117.160) smtp.rcpttodomain=monjalon.net smtp.mailfrom=nvidia.com;\n dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com;\n dkim=none (message not signed); arc=none", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com;\n s=selector2;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n bh=ntm7F6qM4MuksLXB12yACRJYS/MoKv4IQ7qd2Kh/P5s=;\n b=Wsr9nSnaUxt8D/ckGqTKWegm173tuCkPj9LFCrYNAY7ry3IXFxcw8XJ0Js99xoMdixcR2OCXeDkn1mKDYr9KR2M1L9ywc7zmlonc9iJ/CHJQeDPitoJYYPqQuZsKlELr9J70OvJfz9Hw9K/4n3VVf1w1qqZe/jv02iCGpcYttSLm28PZjdrBkfIemhBgiYF8nH4SWXmNe+YrCZyk51fdeh57VKuE0AjDkOLgTiELeb95BMjVP1ORO5oVroSjMl9SX1n08XtLo78ZDwvEAbY59jcEGEtViFxiiAGusgp6ooLqO6v7D0KyCLSK9q8rNOuOBQEK084hOp6xNuvjnSlRtA==", "X-MS-Exchange-Authentication-Results": "spf=pass (sender IP is 216.228.117.160)\n smtp.mailfrom=nvidia.com;\n dkim=none (message not signed)\n header.d=none;dmarc=pass action=none header.from=nvidia.com;", "Received-SPF": "Pass (protection.outlook.com: domain of nvidia.com designates\n 216.228.117.160 as permitted sender) receiver=protection.outlook.com;\n client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C", "From": "Rongwei Liu <rongweil@nvidia.com>", "To": "<matan@nvidia.com>, <viacheslavo@nvidia.com>, <orika@nvidia.com>,\n <thomas@monjalon.net>", "CC": "<dev@dpdk.org>, <rasland@nvidia.com>", "Subject": "[PATCH v3 05/11] net/mlx5: adopt new flex item prm definition", "Date": "Mon, 30 Jan 2023 15:19:54 +0200", "Message-ID": "<20230130132000.1715473-6-rongweil@nvidia.com>", "X-Mailer": "git-send-email 2.27.0", "In-Reply-To": "<20230130132000.1715473-1-rongweil@nvidia.com>", "References": "<3ba49f25-52d0-fe07-02e6-22a71e0fbe13@oktetlabs.ru>\n <20230130132000.1715473-1-rongweil@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[10.126.231.37]", "X-ClientProxiedBy": "rnnvmail203.nvidia.com (10.129.68.9) To\n rnnvmail201.nvidia.com (10.129.68.8)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "BN8NAM11FT031:EE_|MN2PR12MB4520:EE_", "X-MS-Office365-Filtering-Correlation-Id": "c1cef3da-8dc4-4e60-6d1c-08db02c4c858", "X-LD-Processed": "43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n Ds+8G6MQraWppCMHMLqcpZPXCovhb20FUm/ZwAYzMlQrkbz0MTyQCDtmgyX5d3b1dx/uBTkm4CzDApfWxdqjfkoDgcQd6ds7jVEHxfO9Px1CGFlOCc/9ypotRI+gcUR1AZ2B8YJXQl9gpcQp9lQ16dfA8Ip9qVs9nYw9mUoyw3iH2GihnuMeCNotFqmNFhMAGvZC1vCLMpe6SkWwOLS9/2Ro3qH80ME4j/dPPDTbiPRP/O/DP+jQBk+8qGNzxcpQy4SotsRwQI8F76f5upnkZy/4rx+QxrZBad8VhNey2WJ87HxJgsAcQqKMyy189T9Kry09AtwYfbNw0zvz6PklgsVsPhnVm9TUtRF5Hphwk6wPa3f3pw3PBiAuNbT1xWa84wDATl62bSsTLBDnYodeSFuf0mQWI34QuNMpd0B/E7EoRIrAb/d4Vp1P8/JGENMVzlGCXa3N7Gw4mViqJ9rtAqzaSzx+32Asih5UYgekxtbhunuUnGDNm4CfODu9OJ92NtU4Exvh9YZXT7DrxfURiXPqk6W6K5l3cQym41Yfm2Dw3DzDWPQC3Ky6b85NoBL8eyalnyWsIGKl3H2fUANU72GNRDo1jOrMSzDoDbjN/kMXR/IgCKgqLnqZY3rQV/KhD61tAqsk6OPv9E3HFixYthR147h/lGRb3MkebaONpgkxyhYaHwsB7Yv+HMb42+g1bKQ9ji9xLA1u0uf1iXuWSg==", "X-Forefront-Antispam-Report": "CIP:216.228.117.160; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE;\n SFS:(13230025)(4636009)(396003)(346002)(39850400004)(136003)(376002)(451199018)(46966006)(36840700001)(40470700004)(8936002)(70206006)(70586007)(316002)(8676002)(4326008)(5660300002)(16526019)(54906003)(110136005)(1076003)(2906002)(41300700001)(7696005)(478600001)(107886003)(6666004)(186003)(6286002)(2616005)(26005)(36756003)(336012)(40460700003)(426003)(47076005)(356005)(83380400001)(36860700001)(55016003)(82310400005)(86362001)(40480700001)(7636003)(82740400003);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "30 Jan 2023 13:20:39.9109 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n c1cef3da-8dc4-4e60-6d1c-08db02c4c858", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n BN8NAM11FT031.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "MN2PR12MB4520", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Per newest PRM definition, sample_id stands for 3 parts\nof information instead of single uint32_t id: sample_id +\nmodify_filed_id + format_select_dw.\n\nAlso new FW capability bits have been introduces to identify\nthe new capability.\n\nSigned-off-by: Rongwei Liu <rongweil@nvidia.com>\nAcked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>\n---\n drivers/common/mlx5/mlx5_devx_cmds.c | 14 +++++++++++---\n drivers/common/mlx5/mlx5_devx_cmds.h | 7 ++++++-\n drivers/common/mlx5/mlx5_prm.h | 28 ++++++++++++++++++++++++++--\n drivers/net/mlx5/mlx5.c | 15 +++++++++++----\n drivers/net/mlx5/mlx5.h | 3 ++-\n drivers/net/mlx5/mlx5_flow_flex.c | 14 +++++++++++---\n 6 files changed, 67 insertions(+), 14 deletions(-)", "diff": "diff --git a/drivers/common/mlx5/mlx5_devx_cmds.c b/drivers/common/mlx5/mlx5_devx_cmds.c\nindex e3a4927d0f..1f65ea7dcb 100644\n--- a/drivers/common/mlx5/mlx5_devx_cmds.c\n+++ b/drivers/common/mlx5/mlx5_devx_cmds.c\n@@ -607,7 +607,8 @@ mlx5_devx_cmd_query_hca_vdpa_attr(void *ctx,\n \n int\n mlx5_devx_cmd_query_parse_samples(struct mlx5_devx_obj *flex_obj,\n-\t\t\t\t uint32_t ids[], uint32_t num)\n+\t\t\t\t struct mlx5_ext_sample_id ids[],\n+\t\t\t\t uint32_t num, uint8_t *anchor)\n {\n \tuint32_t in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {0};\n \tuint32_t out[MLX5_ST_SZ_DW(create_flex_parser_out)] = {0};\n@@ -636,6 +637,7 @@ mlx5_devx_cmd_query_parse_samples(struct mlx5_devx_obj *flex_obj,\n \t\t\t(void *)flex_obj);\n \t\treturn -rte_errno;\n \t}\n+\t*anchor = MLX5_GET(parse_graph_flex, flex, head_anchor_id);\n \tfor (i = 0; i < MLX5_GRAPH_NODE_SAMPLE_NUM; i++) {\n \t\tvoid *s_off = (void *)((char *)sample + i *\n \t\t\t MLX5_ST_SZ_BYTES(parse_graph_flow_match_sample));\n@@ -645,8 +647,8 @@ mlx5_devx_cmd_query_parse_samples(struct mlx5_devx_obj *flex_obj,\n \t\t\t flow_match_sample_en);\n \t\tif (!en)\n \t\t\tcontinue;\n-\t\tids[idx++] = MLX5_GET(parse_graph_flow_match_sample, s_off,\n-\t\t\t\t flow_match_sample_field_id);\n+\t\tids[idx++].id = MLX5_GET(parse_graph_flow_match_sample, s_off,\n+\t\t\t\t\t flow_match_sample_field_id);\n \t}\n \tif (num != idx) {\n \t\trte_errno = EINVAL;\n@@ -794,6 +796,12 @@ mlx5_devx_cmd_query_hca_parse_graph_node_cap\n \t\t\t\t\t max_num_arc_out);\n \tattr->max_num_sample = MLX5_GET(parse_graph_node_cap, hcattr,\n \t\t\t\t\tmax_num_sample);\n+\tattr->anchor_en = MLX5_GET(parse_graph_node_cap, hcattr, anchor_en);\n+\tattr->ext_sample_id = MLX5_GET(parse_graph_node_cap, hcattr, ext_sample_id);\n+\tattr->sample_tunnel_inner2 = MLX5_GET(parse_graph_node_cap, hcattr,\n+\t\t\t\t\t sample_tunnel_inner2);\n+\tattr->zero_size_supported = MLX5_GET(parse_graph_node_cap, hcattr,\n+\t\t\t\t\t zero_size_supported);\n \tattr->sample_id_in_out = MLX5_GET(parse_graph_node_cap, hcattr,\n \t\t\t\t\t sample_id_in_out);\n \tattr->max_base_header_length = MLX5_GET(parse_graph_node_cap, hcattr,\ndiff --git a/drivers/common/mlx5/mlx5_devx_cmds.h b/drivers/common/mlx5/mlx5_devx_cmds.h\nindex c94b9eac06..5b33010155 100644\n--- a/drivers/common/mlx5/mlx5_devx_cmds.h\n+++ b/drivers/common/mlx5/mlx5_devx_cmds.h\n@@ -114,6 +114,10 @@ struct mlx5_hca_flex_attr {\n \tuint8_t max_num_arc_out;\n \tuint8_t max_num_sample;\n \tuint8_t max_num_prog_sample:5;\t/* From HCA CAP 2 */\n+\tuint8_t anchor_en:1;\n+\tuint8_t ext_sample_id:1;\n+\tuint8_t sample_tunnel_inner2:1;\n+\tuint8_t zero_size_supported:1;\n \tuint8_t sample_id_in_out:1;\n \tuint16_t max_base_header_length;\n \tuint8_t max_sample_base_offset;\n@@ -706,7 +710,8 @@ int mlx5_devx_cmd_modify_tir(struct mlx5_devx_obj *tir,\n \t\t\t struct mlx5_devx_modify_tir_attr *tir_attr);\n __rte_internal\n int mlx5_devx_cmd_query_parse_samples(struct mlx5_devx_obj *flex_obj,\n-\t\t\t\t uint32_t ids[], uint32_t num);\n+\t\t\t\t struct mlx5_ext_sample_id ids[],\n+\t\t\t\t uint32_t num, uint8_t *anchor);\n \n __rte_internal\n struct mlx5_devx_obj *\ndiff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h\nindex 9294f65e24..b32dc735a1 100644\n--- a/drivers/common/mlx5/mlx5_prm.h\n+++ b/drivers/common/mlx5/mlx5_prm.h\n@@ -1894,7 +1894,11 @@ struct mlx5_ifc_parse_graph_node_cap_bits {\n \tu8 max_num_arc_in[0x08];\n \tu8 max_num_arc_out[0x08];\n \tu8 max_num_sample[0x08];\n-\tu8 reserved_at_78[0x07];\n+\tu8 reserved_at_78[0x03];\n+\tu8 anchor_en[0x1];\n+\tu8 ext_sample_id[0x1];\n+\tu8 sample_tunnel_inner2[0x1];\n+\tu8 zero_size_supported[0x1];\n \tu8 sample_id_in_out[0x1];\n \tu8 max_base_header_length[0x10];\n \tu8 reserved_at_90[0x08];\n@@ -1904,6 +1908,24 @@ struct mlx5_ifc_parse_graph_node_cap_bits {\n \tu8 header_length_mask_width[0x08];\n };\n \n+/* ext_sample_id structure, see PRM Table: Flow Match Sample ID Format. */\n+struct mlx5_ext_sample_id {\n+\tunion {\n+\t\tstruct {\n+#if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN\n+\t\t\tuint32_t format_select_dw:8;\n+\t\t\tuint32_t modify_field_id:12;\n+\t\t\tuint32_t sample_id:12;\n+#else\n+\t\t\tuint32_t sample_id:12;\n+\t\t\tuint32_t modify_field_id:12;\n+\t\t\tuint32_t format_select_dw:8;\n+#endif\n+\t\t};\n+\t\tuint32_t id;\n+\t};\n+};\n+\n struct mlx5_ifc_flow_table_prop_layout_bits {\n \tu8 ft_support[0x1];\n \tu8 flow_tag[0x1];\n@@ -4542,7 +4564,9 @@ struct mlx5_ifc_parse_graph_flex_bits {\n \tu8 header_length_mode[0x4];\n \tu8 header_length_field_offset[0x10];\n \tu8 next_header_field_offset[0x10];\n-\tu8 reserved_at_160[0x1b];\n+\tu8 reserved_at_160[0x12];\n+\tu8 head_anchor_id[0x6];\n+\tu8 reserved_at_178[0x3];\n \tu8 next_header_field_size[0x5];\n \tu8 header_length_field_mask[0x20];\n \tu8 reserved_at_224[0x20];\ndiff --git a/drivers/net/mlx5/mlx5.c b/drivers/net/mlx5/mlx5.c\nindex b8643cebdd..0b97c4e78d 100644\n--- a/drivers/net/mlx5/mlx5.c\n+++ b/drivers/net/mlx5/mlx5.c\n@@ -964,11 +964,13 @@ int\n mlx5_flex_parser_ecpri_alloc(struct rte_eth_dev *dev)\n {\n \tstruct mlx5_priv *priv = dev->data->dev_private;\n+\tstruct mlx5_hca_flex_attr *attr = &priv->sh->cdev->config.hca_attr.flex;\n \tstruct mlx5_ecpri_parser_profile *prf =\t&priv->sh->ecpri_parser;\n \tstruct mlx5_devx_graph_node_attr node = {\n \t\t.modify_field_select = 0,\n \t};\n-\tuint32_t ids[8];\n+\tstruct mlx5_ext_sample_id ids[8];\n+\tuint8_t anchor_id;\n \tint ret;\n \n \tif (!priv->sh->cdev->config.hca_attr.parse_graph_flex_node) {\n@@ -1004,15 +1006,20 @@ mlx5_flex_parser_ecpri_alloc(struct rte_eth_dev *dev)\n \t\treturn (rte_errno == 0) ? -ENODEV : -rte_errno;\n \t}\n \tprf->num = 2;\n-\tret = mlx5_devx_cmd_query_parse_samples(prf->obj, ids, prf->num);\n+\tret = mlx5_devx_cmd_query_parse_samples(prf->obj, ids, prf->num, &anchor_id);\n \tif (ret) {\n \t\tDRV_LOG(ERR, \"Failed to query sample IDs.\");\n \t\treturn (rte_errno == 0) ? -ENODEV : -rte_errno;\n \t}\n \tprf->offset[0] = 0x0;\n \tprf->offset[1] = sizeof(uint32_t);\n-\tprf->ids[0] = ids[0];\n-\tprf->ids[1] = ids[1];\n+\tif (attr->ext_sample_id) {\n+\t\tprf->ids[0] = ids[0].sample_id;\n+\t\tprf->ids[1] = ids[1].sample_id;\n+\t} else {\n+\t\tprf->ids[0] = ids[0].id;\n+\t\tprf->ids[1] = ids[1].id;\n+\t}\n \treturn 0;\n }\n \ndiff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h\nindex 16b33e1548..83fb316ad8 100644\n--- a/drivers/net/mlx5/mlx5.h\n+++ b/drivers/net/mlx5/mlx5.h\n@@ -1307,9 +1307,10 @@ struct mlx5_lag {\n struct mlx5_flex_parser_devx {\n \tstruct mlx5_list_entry entry; /* List element at the beginning. */\n \tuint32_t num_samples;\n+\tuint8_t anchor_id;\n \tvoid *devx_obj;\n \tstruct mlx5_devx_graph_node_attr devx_conf;\n-\tuint32_t sample_ids[MLX5_GRAPH_NODE_SAMPLE_NUM];\n+\tstruct mlx5_ext_sample_id sample_ids[MLX5_GRAPH_NODE_SAMPLE_NUM];\n };\n \n /* Pattern field descriptor - how to translate flex pattern into samples. */\ndiff --git a/drivers/net/mlx5/mlx5_flow_flex.c b/drivers/net/mlx5/mlx5_flow_flex.c\nindex bec07b13c1..24b7226ee6 100644\n--- a/drivers/net/mlx5/mlx5_flow_flex.c\n+++ b/drivers/net/mlx5/mlx5_flow_flex.c\n@@ -226,15 +226,18 @@ mlx5_flex_flow_translate_item(struct rte_eth_dev *dev,\n \tvoid *misc4_m = MLX5_ADDR_OF(fte_match_param, matcher,\n \t\t\t\t misc_parameters_4);\n \tvoid *misc4_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_4);\n+\tstruct mlx5_priv *priv = dev->data->dev_private;\n+\tstruct mlx5_hca_flex_attr *attr = &priv->sh->cdev->config.hca_attr.flex;\n \tstruct mlx5_flex_item *tp;\n \tuint32_t i, pos = 0;\n+\tuint32_t sample_id;\n \n \tRTE_SET_USED(dev);\n \tMLX5_ASSERT(item->spec && item->mask);\n \tspec = item->spec;\n \tmask = item->mask;\n \ttp = (struct mlx5_flex_item *)spec->handle;\n-\tMLX5_ASSERT(mlx5_flex_index(dev->data->dev_private, tp) >= 0);\n+\tMLX5_ASSERT(mlx5_flex_index(priv, tp) >= 0);\n \tfor (i = 0; i < tp->mapnum; i++) {\n \t\tstruct mlx5_flex_pattern_field *map = tp->map + i;\n \t\tuint32_t id = map->reg_id;\n@@ -257,9 +260,13 @@ mlx5_flex_flow_translate_item(struct rte_eth_dev *dev,\n \t\t\tMLX5_ASSERT(id < num_samples);\n \t\t\tid += num_samples;\n \t\t}\n+\t\tif (attr->ext_sample_id)\n+\t\t\tsample_id = tp->devx_fp->sample_ids[id].sample_id;\n+\t\telse\n+\t\t\tsample_id = tp->devx_fp->sample_ids[id].id;\n \t\tmlx5_flex_set_match_sample(misc4_m, misc4_v,\n \t\t\t\t\t def, msk & def, val & msk & def,\n-\t\t\t\t\t tp->devx_fp->sample_ids[id], id);\n+\t\t\t\t\t sample_id, id);\n \t\tpos += map->width;\n \t}\n }\n@@ -1317,7 +1324,8 @@ mlx5_flex_parser_create_cb(void *list_ctx, void *ctx)\n \t/* Query the firmware assigned sample ids. */\n \tret = mlx5_devx_cmd_query_parse_samples(fp->devx_obj,\n \t\t\t\t\t\tfp->sample_ids,\n-\t\t\t\t\t\tfp->num_samples);\n+\t\t\t\t\t\tfp->num_samples,\n+\t\t\t\t\t\t&fp->anchor_id);\n \tif (ret)\n \t\tgoto error;\n \tDRV_LOG(DEBUG, \"DEVx flex parser %p created, samples num: %u\",\n", "prefixes": [ "v3", "05/11" ] }