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GET /api/patches/122241/?format=api
{ "id": 122241, "url": "http://patches.dpdk.org/api/patches/122241/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20230118060039.3074016-6-jiawenwu@trustnetic.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20230118060039.3074016-6-jiawenwu@trustnetic.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20230118060039.3074016-6-jiawenwu@trustnetic.com", "date": "2023-01-18T06:00:36", "name": "[5/8] net/ngbe: add spinlock protection on YT PHY", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "871189d4108946bcc1d43dd7d49f9b0c7acccfcf", "submitter": { "id": 1932, "url": "http://patches.dpdk.org/api/people/1932/?format=api", "name": "Jiawen Wu", "email": "jiawenwu@trustnetic.com" }, "delegate": { "id": 319, "url": "http://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20230118060039.3074016-6-jiawenwu@trustnetic.com/mbox/", "series": [ { "id": 26585, "url": "http://patches.dpdk.org/api/series/26585/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=26585", "date": "2023-01-18T06:00:31", "name": "Wangxun fixes and new supports", "version": 1, "mbox": "http://patches.dpdk.org/series/26585/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/122241/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/122241/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id D0AEE42409;\n\tWed, 18 Jan 2023 07:04:45 +0100 (CET)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id E3D7642D54;\n\tWed, 18 Jan 2023 07:04:23 +0100 (CET)", "from smtpbg156.qq.com (smtpbg156.qq.com [15.184.82.18])\n by mails.dpdk.org (Postfix) with ESMTP id EA76742D59;\n Wed, 18 Jan 2023 07:04:20 +0100 (CET)", "from wxdbg.localdomain.com ( [183.129.236.74])\n by bizesmtp.qq.com (ESMTP) with\n id ; Wed, 18 Jan 2023 14:04:16 +0800 (CST)" ], "X-QQ-mid": "bizesmtp69t1674021857tdpi4o0m", "X-QQ-SSF": "01400000000000H0X000B00A0000000", "X-QQ-FEAT": "FVl8EHhfVR7uhbB1A9ra2Qpk4/PxebGUOEhy4y3z18OFkrpES4q+J1UumQihH\n 0/ev6kf+9O0A2LAkMXcUf6SJGoN4KhcNOUTNEEGnbWRr6d/XY8OJODHTWAqsDX4x6n8bjuI\n W5c30UDg5jfbLLxa0f0MQPsFAPSRN7LdSjpSI44D+saW9QVKGTH3WEW1o9x1ff94FCwwpLH\n mLnWvTWLWG23yJn03hlEO5y8cKSpc5m/JIXHDq4pqiciL/RX2yV9VUBcmASy19TRmv1aVjy\n BwYNKo8t/C2dBSwAcspC9B6W5DFxIXXHzBWc4Wj51OvAIyRW7zjToHFlYM3KdMv9Ff1rg4i\n I+ib8q4PITWPGQaP5myhHcz2TXq77UBH/wjP050F/3Un4wvgCj9XmtImG2kGy8BwE+WwXGG", "X-QQ-GoodBg": "2", "From": "Jiawen Wu <jiawenwu@trustnetic.com>", "To": "dev@dpdk.org", "Cc": "Jiawen Wu <jiawenwu@trustnetic.com>,\n\tstable@dpdk.org", "Subject": "[PATCH 5/8] net/ngbe: add spinlock protection on YT PHY", "Date": "Wed, 18 Jan 2023 14:00:36 +0800", "Message-Id": "<20230118060039.3074016-6-jiawenwu@trustnetic.com>", "X-Mailer": "git-send-email 2.27.0", "In-Reply-To": "<20230118060039.3074016-1-jiawenwu@trustnetic.com>", "References": "<20230118060039.3074016-1-jiawenwu@trustnetic.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-QQ-SENDSIZE": "520", "Feedback-ID": "bizesmtp:trustnetic.com:qybglogicsvr:qybglogicsvr5", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "For yt8521s/yt8531s PHY, if other registers are accessing between\nreads/writes of ext field registers, the value of ext filed registers\nwill get weird for unknown reasons. So it's protected when all of ext\nfield registers accessing.\n\nFixes: 44e97550ca68 (\"net/ngbe: identify and reset PHY\")\nCc: stable@dpdk.org\n\nSigned-off-by: Jiawen Wu <jiawenwu@trustnetic.com>\n---\n drivers/net/ngbe/base/ngbe_phy_yt.c | 36 +++++++++++++++++++++++++++++\n drivers/net/ngbe/base/ngbe_type.h | 1 +\n 2 files changed, 37 insertions(+)", "diff": "diff --git a/drivers/net/ngbe/base/ngbe_phy_yt.c b/drivers/net/ngbe/base/ngbe_phy_yt.c\nindex c88946f7c3..726d6c8ef5 100644\n--- a/drivers/net/ngbe/base/ngbe_phy_yt.c\n+++ b/drivers/net/ngbe/base/ngbe_phy_yt.c\n@@ -100,11 +100,15 @@ s32 ngbe_write_phy_reg_sds_ext_yt(struct ngbe_hw *hw,\n \n s32 ngbe_init_phy_yt(struct ngbe_hw *hw)\n {\n+\trte_spinlock_init(&hw->phy_lock);\n+\n+\trte_spinlock_lock(&hw->phy_lock);\n \t/* close sds area register */\n \tngbe_write_phy_reg_ext_yt(hw, YT_SMI_PHY, 0, 0);\n \t/* enable interrupts */\n \tngbe_write_phy_reg_mdi(hw, YT_INTR, 0,\n \t\t\t\tYT_INTR_ENA_MASK | YT_SDS_INTR_ENA_MASK);\n+\trte_spinlock_unlock(&hw->phy_lock);\n \n \thw->phy.set_phy_power(hw, false);\n \n@@ -123,7 +127,9 @@ s32 ngbe_setup_phy_link_yt(struct ngbe_hw *hw, u32 speed,\n \thw->phy.autoneg_advertised = 0;\n \n \t/* check chip_mode first */\n+\trte_spinlock_lock(&hw->phy_lock);\n \tngbe_read_phy_reg_ext_yt(hw, YT_CHIP, 0, &value);\n+\trte_spinlock_unlock(&hw->phy_lock);\n \tif ((value & YT_CHIP_MODE_MASK) == YT_CHIP_MODE_SEL(0)) {\n \t\t/* UTP to rgmii */\n \t\tif (!hw->mac.autoneg) {\n@@ -146,11 +152,14 @@ s32 ngbe_setup_phy_link_yt(struct ngbe_hw *hw, u32 speed,\n \t\t\t}\n \t\t\t/* duplex full */\n \t\t\tvalue |= YT_BCR_DUPLEX | YT_BCR_RESET;\n+\t\t\trte_spinlock_lock(&hw->phy_lock);\n \t\t\tngbe_write_phy_reg_mdi(hw, YT_BCR, 0, value);\n+\t\t\trte_spinlock_unlock(&hw->phy_lock);\n \n \t\t\tgoto skip_an;\n \t\t}\n \n+\t\trte_spinlock_lock(&hw->phy_lock);\n \t\t/*disable 100/10base-T Self-negotiation ability*/\n \t\tngbe_read_phy_reg_mdi(hw, YT_ANA, 0, &value);\n \t\tvalue &= ~(YT_ANA_100BASET_FULL | YT_ANA_100BASET_HALF |\n@@ -189,6 +198,7 @@ s32 ngbe_setup_phy_link_yt(struct ngbe_hw *hw, u32 speed,\n \t\tngbe_read_phy_reg_mdi(hw, YT_BCR, 0, &value);\n \t\tvalue |= YT_BCR_RESET | YT_BCR_ANE | YT_BCR_RESTART_AN;\n \t\tngbe_write_phy_reg_mdi(hw, YT_BCR, 0, value);\n+\t\trte_spinlock_unlock(&hw->phy_lock);\n skip_an:\n \t\thw->phy.set_phy_power(hw, true);\n \t} else if ((value & YT_CHIP_MODE_MASK) == YT_CHIP_MODE_SEL(1)) {\n@@ -199,6 +209,7 @@ s32 ngbe_setup_phy_link_yt(struct ngbe_hw *hw, u32 speed,\n \t\tvalue = YT_RGMII_CONF1_RXDELAY |\n \t\t\tYT_RGMII_CONF1_TXDELAY_FE |\n \t\t\tYT_RGMII_CONF1_TXDELAY;\n+\t\trte_spinlock_lock(&hw->phy_lock);\n \t\tngbe_write_phy_reg_ext_yt(hw, YT_RGMII_CONF1, 0, value);\n \t\tvalue = YT_CHIP_MODE_SEL(1) |\n \t\t\tYT_CHIP_SW_LDO_EN |\n@@ -225,17 +236,21 @@ s32 ngbe_setup_phy_link_yt(struct ngbe_hw *hw, u32 speed,\n \t\t\tvalue = YT_BCR_RESET | YT_BCR_DUPLEX |\n \t\t\t\tYT_BCR_SPEED_SELECT1;\n \t\thw->phy.write_reg(hw, YT_BCR, 0, value);\n+\t\trte_spinlock_unlock(&hw->phy_lock);\n \n \t\thw->phy.set_phy_power(hw, true);\n \t} else if ((value & YT_CHIP_MODE_MASK) == YT_CHIP_MODE_SEL(2)) {\n \t\thw->phy.set_phy_power(hw, true);\n \n+\t\trte_spinlock_lock(&hw->phy_lock);\n \t\thw->phy.read_reg(hw, YT_SPST, 0, &value);\n+\t\trte_spinlock_unlock(&hw->phy_lock);\n \t\tif (value & YT_SPST_LINK) {\n \t\t\t/* fiber up */\n \t\t\thw->phy.autoneg_advertised |= NGBE_LINK_SPEED_1GB_FULL;\n \t\t} else {\n \t\t\t/* utp up */\n+\t\t\trte_spinlock_lock(&hw->phy_lock);\n \t\t\t/*disable 100/10base-T Self-negotiation ability*/\n \t\t\tngbe_read_phy_reg_mdi(hw, YT_ANA, 0, &value);\n \t\t\tvalue &= ~(YT_ANA_100BASET_FULL | YT_ANA_100BASET_HALF |\n@@ -279,10 +294,12 @@ s32 ngbe_setup_phy_link_yt(struct ngbe_hw *hw, u32 speed,\n \t\t\tngbe_read_phy_reg_mdi(hw, YT_BCR, 0, &value);\n \t\t\tvalue |= YT_BCR_RESET;\n \t\t\tngbe_write_phy_reg_mdi(hw, YT_BCR, 0, value);\n+\t\t\trte_spinlock_unlock(&hw->phy_lock);\n \t\t}\n \t} else if ((value & YT_CHIP_MODE_MASK) == YT_CHIP_MODE_SEL(4)) {\n \t\thw->phy.autoneg_advertised |= NGBE_LINK_SPEED_1GB_FULL;\n \n+\t\trte_spinlock_lock(&hw->phy_lock);\n \t\tngbe_read_phy_reg_ext_yt(hw, YT_RGMII_CONF1, 0, &value);\n \t\tvalue |= YT_RGMII_CONF1_MODE;\n \t\tngbe_write_phy_reg_ext_yt(hw, YT_RGMII_CONF1, 0, value);\n@@ -297,6 +314,7 @@ s32 ngbe_setup_phy_link_yt(struct ngbe_hw *hw, u32 speed,\n \t\tngbe_read_phy_reg_ext_yt(hw, YT_CHIP, 0, &value);\n \t\tvalue &= ~YT_SMI_PHY_SW_RST;\n \t\tngbe_write_phy_reg_ext_yt(hw, YT_CHIP, 0, value);\n+\t\trte_spinlock_unlock(&hw->phy_lock);\n \n \t\thw->phy.set_phy_power(hw, true);\n \t} else if ((value & YT_CHIP_MODE_MASK) == YT_CHIP_MODE_SEL(5)) {\n@@ -320,7 +338,9 @@ s32 ngbe_setup_phy_link_yt(struct ngbe_hw *hw, u32 speed,\n \t\t\t}\n \t\t\t/* duplex full */\n \t\t\tvalue |= YT_BCR_DUPLEX | YT_BCR_RESET;\n+\t\t\trte_spinlock_lock(&hw->phy_lock);\n \t\t\thw->phy.write_reg(hw, YT_BCR, 0, value);\n+\t\t\trte_spinlock_unlock(&hw->phy_lock);\n \n \t\t\tgoto skip_an_sr;\n \t\t}\n@@ -339,19 +359,23 @@ s32 ngbe_setup_phy_link_yt(struct ngbe_hw *hw, u32 speed,\n \n \t\t/* duplex full */\n \t\tvalue |= YT_BCR_DUPLEX | YT_BCR_RESET;\n+\t\trte_spinlock_lock(&hw->phy_lock);\n \t\thw->phy.write_reg(hw, YT_BCR, 0, value);\n \n \t\t/* software reset to make the above configuration take effect */\n \t\thw->phy.read_reg(hw, YT_BCR, 0, &value);\n \t\tvalue |= YT_BCR_RESET | YT_BCR_ANE | YT_BCR_RESTART_AN;\n \t\thw->phy.write_reg(hw, 0x0, 0, value);\n+\t\trte_spinlock_unlock(&hw->phy_lock);\n \n skip_an_sr:\n \t\thw->phy.set_phy_power(hw, true);\n \t}\n \n+\trte_spinlock_lock(&hw->phy_lock);\n \tngbe_write_phy_reg_ext_yt(hw, YT_SMI_PHY, 0, 0);\n \tngbe_read_phy_reg_mdi(hw, YT_INTR_STATUS, 0, &value);\n+\trte_spinlock_unlock(&hw->phy_lock);\n \n \treturn 0;\n }\n@@ -366,6 +390,7 @@ s32 ngbe_reset_phy_yt(struct ngbe_hw *hw)\n \t\thw->phy.type != ngbe_phy_yt8521s_sfi)\n \t\treturn NGBE_ERR_PHY_TYPE;\n \n+\trte_spinlock_lock(&hw->phy_lock);\n \t/* check chip_mode first */\n \tngbe_read_phy_reg_ext_yt(hw, YT_CHIP, 0, &ctrl);\n \tif (ctrl & YT_CHIP_MODE_MASK) {\n@@ -395,6 +420,7 @@ s32 ngbe_reset_phy_yt(struct ngbe_hw *hw)\n \t\t\tmsleep(1);\n \t\t}\n \t}\n+\trte_spinlock_unlock(&hw->phy_lock);\n \n \tif (i == YT_PHY_RST_WAIT_PERIOD) {\n \t\tDEBUGOUT(\"PHY reset polling failed to complete.\");\n@@ -409,7 +435,9 @@ s32 ngbe_get_phy_advertised_pause_yt(struct ngbe_hw *hw, u8 *pause_bit)\n \tu16 value;\n \ts32 status = 0;\n \n+\trte_spinlock_lock(&hw->phy_lock);\n \tstatus = hw->phy.read_reg(hw, YT_ANA, 0, &value);\n+\trte_spinlock_unlock(&hw->phy_lock);\n \tvalue &= YT_FANA_PAUSE_MASK;\n \t*pause_bit = (u8)(value >> 7);\n \n@@ -421,7 +449,9 @@ s32 ngbe_get_phy_lp_advertised_pause_yt(struct ngbe_hw *hw, u8 *pause_bit)\n \tu16 value;\n \ts32 status = 0;\n \n+\trte_spinlock_lock(&hw->phy_lock);\n \tstatus = hw->phy.read_reg(hw, YT_LPAR, 0, &value);\n+\trte_spinlock_unlock(&hw->phy_lock);\n \tvalue &= YT_FLPAR_PAUSE_MASK;\n \t*pause_bit = (u8)(value >> 7);\n \n@@ -433,10 +463,12 @@ s32 ngbe_set_phy_pause_adv_yt(struct ngbe_hw *hw, u16 pause_bit)\n \tu16 value;\n \ts32 status = 0;\n \n+\trte_spinlock_lock(&hw->phy_lock);\n \tstatus = hw->phy.read_reg(hw, YT_ANA, 0, &value);\n \tvalue &= ~YT_FANA_PAUSE_MASK;\n \tvalue |= pause_bit;\n \tstatus = hw->phy.write_reg(hw, YT_ANA, 0, value);\n+\trte_spinlock_unlock(&hw->phy_lock);\n \n \treturn status;\n }\n@@ -453,6 +485,7 @@ s32 ngbe_check_phy_link_yt(struct ngbe_hw *hw,\n \t/* Initialize speed and link to default case */\n \t*link_up = false;\n \t*speed = NGBE_LINK_SPEED_UNKNOWN;\n+\trte_spinlock_lock(&hw->phy_lock);\n \n \tngbe_write_phy_reg_ext_yt(hw, YT_SMI_PHY, 0, 0);\n \tngbe_read_phy_reg_mdi(hw, YT_INTR_STATUS, 0, &insr);\n@@ -472,6 +505,7 @@ s32 ngbe_check_phy_link_yt(struct ngbe_hw *hw,\n \t\t\t*link_up = true;\n \t}\n \n+\trte_spinlock_unlock(&hw->phy_lock);\n \tif (*link_up) {\n \t\tif (phy_speed == YT_SPST_SPEED_1000M)\n \t\t\t*speed = NGBE_LINK_SPEED_1GB_FULL;\n@@ -488,6 +522,7 @@ s32 ngbe_set_phy_power_yt(struct ngbe_hw *hw, bool on)\n {\n \tu16 value = 0;\n \n+\trte_spinlock_lock(&hw->phy_lock);\n \t/* power down/up in fiber mode */\n \thw->phy.read_reg(hw, YT_BCR, 0, &value);\n \tif (on)\n@@ -504,6 +539,7 @@ s32 ngbe_set_phy_power_yt(struct ngbe_hw *hw, bool on)\n \telse\n \t\tvalue |= YT_BCR_PWDN;\n \tngbe_write_phy_reg_mdi(hw, YT_BCR, 0, value);\n+\trte_spinlock_unlock(&hw->phy_lock);\n \n \treturn 0;\n }\ndiff --git a/drivers/net/ngbe/base/ngbe_type.h b/drivers/net/ngbe/base/ngbe_type.h\nindex aa5c41146c..05804eeab7 100644\n--- a/drivers/net/ngbe/base/ngbe_type.h\n+++ b/drivers/net/ngbe/base/ngbe_type.h\n@@ -433,6 +433,7 @@ struct ngbe_hw {\n \tbool gpio_ctl;\n \tu32 led_conf;\n \tbool init_phy;\n+\trte_spinlock_t phy_lock;\n \tstruct {\n \t\tu64 rx_qp_packets;\n \t\tu64 tx_qp_packets;\n", "prefixes": [ "5/8" ] }