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GET /api/patches/122232/?format=api
{ "id": 122232, "url": "http://patches.dpdk.org/api/patches/122232/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20230118025347.1567078-8-junfeng.guo@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20230118025347.1567078-8-junfeng.guo@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20230118025347.1567078-8-junfeng.guo@intel.com", "date": "2023-01-18T02:53:46", "name": "[RFC,7/8] net/gve: support jumbo frame for GQI", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "e5c06d16e8efff4f0fc89c9ea7d232377ea22c1b", "submitter": { "id": 1785, "url": "http://patches.dpdk.org/api/people/1785/?format=api", "name": "Junfeng Guo", "email": "junfeng.guo@intel.com" }, "delegate": { "id": 319, "url": "http://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20230118025347.1567078-8-junfeng.guo@intel.com/mbox/", "series": [ { "id": 26583, "url": "http://patches.dpdk.org/api/series/26583/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=26583", "date": "2023-01-18T02:53:39", "name": "gve PMD enhancement", "version": 1, "mbox": "http://patches.dpdk.org/series/26583/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/122232/comments/", "check": "warning", "checks": "http://patches.dpdk.org/api/patches/122232/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 5C33D42407;\n\tWed, 18 Jan 2023 03:59:45 +0100 (CET)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id A0C9442D5D;\n\tWed, 18 Jan 2023 03:59:21 +0100 (CET)", "from mga11.intel.com (mga11.intel.com [192.55.52.93])\n by mails.dpdk.org (Postfix) with ESMTP id D6CF242D5D\n for <dev@dpdk.org>; Wed, 18 Jan 2023 03:59:19 +0100 (CET)", "from fmsmga008.fm.intel.com ([10.253.24.58])\n by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 17 Jan 2023 18:59:19 -0800", "from dpdk-jf-ntb-one.sh.intel.com ([10.67.111.104])\n by fmsmga008.fm.intel.com with ESMTP; 17 Jan 2023 18:59:16 -0800" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1674010760; x=1705546760;\n h=from:to:cc:subject:date:message-id:in-reply-to:\n references:mime-version:content-transfer-encoding;\n bh=3ztCh2ZPPctYTGF9UOOMn7a52dNfWwqxrmS7OrHE7rQ=;\n b=nEl3mqzQYkRPnpT+cxaIBr2JMII+lqtnstt27E9eQg4/r9Bslzeg7v+r\n ZiJuSMQ8sSsWDbE47Z/Zk5zILiIFfCixDrxPJUckaSTeluZlnYv1YKkxY\n 8cGs/e29rCXbiOtUe9zeMq99uj+AzXTw16j+5j88vUtjzYz7UYmp21dxD\n qCgmw+tzHR/Z36b7O0SgAqXhrhEgeL1dtEbpMbMeJg/KTGG2Ioc5Afl6Y\n n15YsYW8PfNWjh1Egn7+6w5C3G7cPAKrMMVA9Zz3OL/BhJ4H5nkQS45Tf\n roB4XVwgwDC6SyRi+mdpCrjStoC0Jgc0QNujFDGDIAnLs9HxeDbHPxZ4f Q==;", "X-IronPort-AV": [ "E=McAfee;i=\"6500,9779,10593\"; a=\"322575532\"", "E=Sophos;i=\"5.97,224,1669104000\"; d=\"scan'208\";a=\"322575532\"", "E=McAfee;i=\"6500,9779,10593\"; a=\"722911228\"", "E=Sophos;i=\"5.97,224,1669104000\"; d=\"scan'208\";a=\"722911228\"" ], "X-ExtLoop1": "1", "From": "Junfeng Guo <junfeng.guo@intel.com>", "To": "qi.z.zhang@intel.com, jingjing.wu@intel.com, ferruh.yigit@amd.com,\n beilei.xing@intel.com", "Cc": "dev@dpdk.org, xiaoyun.li@intel.com, helin.zhang@intel.com,\n Junfeng Guo <junfeng.guo@intel.com>, Jordan Kimbrough <jrkim@google.com>,\n Rushil Gupta <rushilg@google.com>, Jeroen de Borst <jeroendb@google.com>", "Subject": "[RFC 7/8] net/gve: support jumbo frame for GQI", "Date": "Wed, 18 Jan 2023 10:53:46 +0800", "Message-Id": "<20230118025347.1567078-8-junfeng.guo@intel.com>", "X-Mailer": "git-send-email 2.34.1", "In-Reply-To": "<20230118025347.1567078-1-junfeng.guo@intel.com>", "References": "<20230118025347.1567078-1-junfeng.guo@intel.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Add multi-segment support to enable GQI Rx Jumbo Frame.\n\nSigned-off-by: Jordan Kimbrough <jrkim@google.com>\nSigned-off-by: Rushil Gupta <rushilg@google.com>\nSigned-off-by: Junfeng Guo <junfeng.guo@intel.com>\nSigned-off-by: Jeroen de Borst <jeroendb@google.com>\n---\n drivers/net/gve/gve_ethdev.h | 8 +++\n drivers/net/gve/gve_rx.c | 128 ++++++++++++++++++++++++++---------\n 2 files changed, 105 insertions(+), 31 deletions(-)", "diff": "diff --git a/drivers/net/gve/gve_ethdev.h b/drivers/net/gve/gve_ethdev.h\nindex 2e0f96499d..608a2f2fb4 100644\n--- a/drivers/net/gve/gve_ethdev.h\n+++ b/drivers/net/gve/gve_ethdev.h\n@@ -138,6 +138,13 @@ struct gve_tx_queue {\n \tuint8_t is_gqi_qpl;\n };\n \n+struct gve_rx_ctx {\n+\tstruct rte_mbuf *mbuf_head;\n+\tstruct rte_mbuf *mbuf_tail;\n+\tuint16_t total_frags;\n+\tbool drop_pkt;\n+};\n+\n struct gve_rx_queue {\n \tvolatile struct gve_rx_desc *rx_desc_ring;\n \tvolatile union gve_rx_data_slot *rx_data_ring;\n@@ -146,6 +153,7 @@ struct gve_rx_queue {\n \tuint64_t rx_ring_phys_addr;\n \tstruct rte_mbuf **sw_ring;\n \tstruct rte_mempool *mpool;\n+\tstruct gve_rx_ctx ctx;\n \n \tuint16_t rx_tail;\n \tuint16_t nb_rx_desc;\ndiff --git a/drivers/net/gve/gve_rx.c b/drivers/net/gve/gve_rx.c\nindex 9ba975c9b4..2468fc70ee 100644\n--- a/drivers/net/gve/gve_rx.c\n+++ b/drivers/net/gve/gve_rx.c\n@@ -5,6 +5,8 @@\n #include \"gve_ethdev.h\"\n #include \"base/gve_adminq.h\"\n \n+#define GVE_PKT_CONT_BIT_IS_SET(x) (GVE_RXF_PKT_CONT & (x))\n+\n static inline void\n gve_rx_refill(struct gve_rx_queue *rxq)\n {\n@@ -80,40 +82,70 @@ gve_rx_refill(struct gve_rx_queue *rxq)\n \t}\n }\n \n-uint16_t\n-gve_rx_burst(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)\n+/*\n+ * This method processes a single rte_mbuf and handles packet segmentation\n+ * In QPL mode it copies data from the mbuf to the gve_rx_queue.\n+ */\n+static void\n+gve_rx_mbuf(struct gve_rx_queue *rxq, struct rte_mbuf *rxe, uint16_t len,\n+\t uint16_t rx_id)\n {\n-\tvolatile struct gve_rx_desc *rxr, *rxd;\n-\tstruct gve_rx_queue *rxq = rx_queue;\n-\tuint16_t rx_id = rxq->rx_tail;\n-\tstruct rte_mbuf *rxe;\n-\tuint16_t nb_rx, len;\n+\tuint16_t padding = 0;\n \tuint64_t addr;\n-\tuint16_t i;\n-\n-\trxr = rxq->rx_desc_ring;\n-\tnb_rx = 0;\n-\n-\tfor (i = 0; i < nb_pkts; i++) {\n-\t\trxd = &rxr[rx_id];\n-\t\tif (GVE_SEQNO(rxd->flags_seq) != rxq->expected_seqno)\n-\t\t\tbreak;\n \n-\t\tif (rxd->flags_seq & GVE_RXF_ERR)\n-\t\t\tcontinue;\n-\n-\t\tlen = rte_be_to_cpu_16(rxd->len) - GVE_RX_PAD;\n-\t\trxe = rxq->sw_ring[rx_id];\n-\t\tif (rxq->is_gqi_qpl) {\n-\t\t\taddr = (uint64_t)(rxq->qpl->mz->addr) + rx_id * PAGE_SIZE + GVE_RX_PAD;\n-\t\t\trte_memcpy((void *)((size_t)rxe->buf_addr + rxe->data_off),\n-\t\t\t\t (void *)(size_t)addr, len);\n-\t\t}\n+\trxe->data_len = len;\n+\tif (!rxq->ctx.mbuf_head) {\n+\t\trxq->ctx.mbuf_head = rxe;\n+\t\trxq->ctx.mbuf_tail = rxe;\n+\t\trxe->nb_segs = 1;\n \t\trxe->pkt_len = len;\n \t\trxe->data_len = len;\n \t\trxe->port = rxq->port_id;\n \t\trxe->ol_flags = 0;\n+\t\tpadding = GVE_RX_PAD;\n+\t} else {\n+\t\trxq->ctx.mbuf_head->pkt_len += len;\n+\t\trxq->ctx.mbuf_head->nb_segs += 1;\n+\t\trxq->ctx.mbuf_tail->next = rxe;\n+\t\trxq->ctx.mbuf_tail = rxe;\n+\t}\n+\tif (rxq->is_gqi_qpl) {\n+\t\taddr = (uint64_t)(rxq->qpl->mz->addr) + rx_id * PAGE_SIZE + padding;\n+\t\trte_memcpy((void *)((size_t)rxe->buf_addr + rxe->data_off),\n+\t\t\t\t (void *)(size_t)addr, len);\n+\t}\n+}\n+\n+/*\n+ * This method processes a single packet fragment associated with the\n+ * passed packet descriptor.\n+ * This methods returns whether the fragment is the last fragment\n+ * of a packet.\n+ */\n+static bool\n+gve_rx(struct gve_rx_queue *rxq, volatile struct gve_rx_desc *rxd, uint16_t rx_id)\n+{\n+\tbool is_last_frag = !GVE_PKT_CONT_BIT_IS_SET(rxd->flags_seq);\n+\tuint16_t frag_size = rte_be_to_cpu_16(rxd->len);\n+\tstruct gve_rx_ctx *ctx = &rxq->ctx;\n+\tbool is_first_frag = ctx->total_frags == 0;\n+\tstruct rte_mbuf *rxe;\n+\n+\tif (ctx->drop_pkt)\n+\t\tgoto finish_frag;\n \n+\tif (rxd->flags_seq & GVE_RXF_ERR) {\n+\t\tctx->drop_pkt = true;\n+\t\tgoto finish_frag;\n+\t}\n+\n+\tif (is_first_frag)\n+\t\tfrag_size -= GVE_RX_PAD;\n+\n+\trxe = rxq->sw_ring[rx_id];\n+\tgve_rx_mbuf(rxq, rxe, frag_size, rx_id);\n+\n+\tif (is_first_frag) {\n \t\tif (rxd->flags_seq & GVE_RXF_TCP)\n \t\t\trxe->packet_type |= RTE_PTYPE_L4_TCP;\n \t\tif (rxd->flags_seq & GVE_RXF_UDP)\n@@ -127,18 +159,52 @@ gve_rx_burst(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)\n \t\t\trxe->ol_flags |= RTE_MBUF_F_RX_RSS_HASH;\n \t\t\trxe->hash.rss = rte_be_to_cpu_32(rxd->rss_hash);\n \t\t}\n+\t}\n \n-\t\trxq->expected_seqno = gve_next_seqno(rxq->expected_seqno);\n+finish_frag:\n+\tctx->total_frags++;\n+\treturn is_last_frag;\n+}\n+\n+static void\n+gve_rx_ctx_clear(struct gve_rx_ctx *ctx)\n+{\n+\tctx->mbuf_head = NULL;\n+\tctx->mbuf_tail = NULL;\n+\tctx->drop_pkt = false;\n+\tctx->total_frags = 0;\n+}\n+\n+uint16_t\n+gve_rx_burst(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)\n+{\n+\tvolatile struct gve_rx_desc *rxr, *rxd;\n+\tstruct gve_rx_queue *rxq = rx_queue;\n+\tstruct gve_rx_ctx *ctx = &rxq->ctx;\n+\tuint16_t rx_id = rxq->rx_tail;\n+\tuint16_t nb_rx;\n+\n+\trxr = rxq->rx_desc_ring;\n+\tnb_rx = 0;\n+\n+\twhile (nb_rx < nb_pkts) {\n+\t\trxd = &rxr[rx_id];\n+\t\tif (GVE_SEQNO(rxd->flags_seq) != rxq->expected_seqno)\n+\t\t\tbreak;\n+\n+\t\tif (gve_rx(rxq, rxd, rx_id)) {\n+\t\t\tif (!ctx->drop_pkt)\n+\t\t\t\trx_pkts[nb_rx++] = ctx->mbuf_head;\n+\t\t\trxq->nb_avail += ctx->total_frags;\n+\t\t\tgve_rx_ctx_clear(ctx);\n+\t\t}\n \n \t\trx_id++;\n \t\tif (rx_id == rxq->nb_rx_desc)\n \t\t\trx_id = 0;\n-\n-\t\trx_pkts[nb_rx] = rxe;\n-\t\tnb_rx++;\n+\t\trxq->expected_seqno = gve_next_seqno(rxq->expected_seqno);\n \t}\n \n-\trxq->nb_avail += nb_rx;\n \trxq->rx_tail = rx_id;\n \n \tif (rxq->nb_avail > rxq->free_thresh)\n", "prefixes": [ "RFC", "7/8" ] }