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GET /api/patches/122185/?format=api
{ "id": 122185, "url": "http://patches.dpdk.org/api/patches/122185/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20230117132619.83712-2-simei.su@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20230117132619.83712-2-simei.su@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20230117132619.83712-2-simei.su@intel.com", "date": "2023-01-17T13:26:17", "name": "[v2,1/3] net/igc: code refactoring", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "d4a2218f281c21285849b0269024fff71514f26d", "submitter": { "id": 1298, "url": "http://patches.dpdk.org/api/people/1298/?format=api", "name": "Simei Su", "email": "simei.su@intel.com" }, "delegate": { "id": 1540, "url": "http://patches.dpdk.org/api/users/1540/?format=api", "username": "qzhan15", "first_name": "Qi", "last_name": "Zhang", "email": "qi.z.zhang@intel.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20230117132619.83712-2-simei.su@intel.com/mbox/", "series": [ { "id": 26578, "url": "http://patches.dpdk.org/api/series/26578/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=26578", "date": "2023-01-17T13:26:16", "name": "net/igc: support PTP timesync", "version": 2, "mbox": "http://patches.dpdk.org/series/26578/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/122185/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/122185/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 66964423FD;\n\tTue, 17 Jan 2023 14:27:04 +0100 (CET)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 2B26C42D0B;\n\tTue, 17 Jan 2023 14:27:01 +0100 (CET)", "from mga18.intel.com (mga18.intel.com [134.134.136.126])\n by mails.dpdk.org (Postfix) with ESMTP id F3191400D4\n for <dev@dpdk.org>; Tue, 17 Jan 2023 14:26:58 +0100 (CET)", "from orsmga002.jf.intel.com ([10.7.209.21])\n by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 17 Jan 2023 05:26:58 -0800", "from unknown (HELO npg-dpdk-simeisu-cvl-119d218.sh.intel.com)\n ([10.67.119.208])\n by orsmga002.jf.intel.com with ESMTP; 17 Jan 2023 05:26:56 -0800" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1673962019; x=1705498019;\n h=from:to:cc:subject:date:message-id:in-reply-to: references;\n bh=pb8ocqnTqmC3XFIdhSXr42NEGPxqD/tfLDykO6/x1UI=;\n b=dCdD5xqOvaTzwsRyICaeIT3RuF276jQA9xpvhm8LHTcWc8iks27+2pMN\n o13/iB8MOiEVndEblo+tB8eOjVrv5DxyZHvJ45Mn0I0bHMD1LO4VvvrQW\n UkXBBVQa4OdT1IVjnch9E2nT+38ODcicuruLeOHgdzrGekNWpK8587xjy\n 1Omb3qvN3pT+QhE0BNRUEN6EdEmE/ktcn2vRw9dJD4dKQx/nYm8ExaJzi\n aWkqXKvSS8UvdKZhhMmhvcnWZXHzX8rBrXqT1a7I8h7ofMCUJwUwxAOQW\n vbQ3bkVpO2a0EsYF+PoZ2wEtZ4YpxK62NbJep4YXrwl1PW1WOj31HSIxa g==;", "X-IronPort-AV": [ "E=McAfee;i=\"6500,9779,10592\"; a=\"308255768\"", "E=Sophos;i=\"5.97,224,1669104000\"; d=\"scan'208\";a=\"308255768\"", "E=McAfee;i=\"6500,9779,10592\"; a=\"659392188\"", "E=Sophos;i=\"5.97,224,1669104000\"; d=\"scan'208\";a=\"659392188\"" ], "X-ExtLoop1": "1", "From": "Simei Su <simei.su@intel.com>", "To": "qi.z.zhang@intel.com,\n\tjunfeng.guo@intel.com", "Cc": "dev@dpdk.org,\n\twenjun1.wu@intel.com,\n\tSimei Su <simei.su@intel.com>", "Subject": "[PATCH v2 1/3] net/igc: code refactoring", "Date": "Tue, 17 Jan 2023 21:26:17 +0800", "Message-Id": "<20230117132619.83712-2-simei.su@intel.com>", "X-Mailer": "git-send-email 2.9.5", "In-Reply-To": "<20230117132619.83712-1-simei.su@intel.com>", "References": "<20221220034103.441524-1-simei.su@intel.com>\n <20230117132619.83712-1-simei.su@intel.com>", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "This patch moves some structures from rxtx.c to rxtx.h for the\ntimesync enabling feature. For example, variables in \"igc_rx_queue\"\nstructure can be used by variables both in igc_ethdev.c and igc_txrx.c\nmore conveniently. It is also consistent with other PMD coding styles.\n\nSigned-off-by: Simei Su <simei.su@intel.com>\n---\n drivers/net/igc/igc_txrx.c | 118 ---------------------------------------------\n drivers/net/igc/igc_txrx.h | 115 +++++++++++++++++++++++++++++++++++++++++++\n 2 files changed, 115 insertions(+), 118 deletions(-)", "diff": "diff --git a/drivers/net/igc/igc_txrx.c b/drivers/net/igc/igc_txrx.c\nindex ffd219b..c462e91 100644\n--- a/drivers/net/igc/igc_txrx.c\n+++ b/drivers/net/igc/igc_txrx.c\n@@ -93,124 +93,6 @@\n \n #define IGC_TX_OFFLOAD_NOTSUP_MASK (RTE_MBUF_F_TX_OFFLOAD_MASK ^ IGC_TX_OFFLOAD_MASK)\n \n-/**\n- * Structure associated with each descriptor of the RX ring of a RX queue.\n- */\n-struct igc_rx_entry {\n-\tstruct rte_mbuf *mbuf; /**< mbuf associated with RX descriptor. */\n-};\n-\n-/**\n- * Structure associated with each RX queue.\n- */\n-struct igc_rx_queue {\n-\tstruct rte_mempool *mb_pool; /**< mbuf pool to populate RX ring. */\n-\tvolatile union igc_adv_rx_desc *rx_ring;\n-\t/**< RX ring virtual address. */\n-\tuint64_t rx_ring_phys_addr; /**< RX ring DMA address. */\n-\tvolatile uint32_t *rdt_reg_addr; /**< RDT register address. */\n-\tvolatile uint32_t *rdh_reg_addr; /**< RDH register address. */\n-\tstruct igc_rx_entry *sw_ring; /**< address of RX software ring. */\n-\tstruct rte_mbuf *pkt_first_seg; /**< First segment of current packet. */\n-\tstruct rte_mbuf *pkt_last_seg; /**< Last segment of current packet. */\n-\tuint16_t nb_rx_desc; /**< number of RX descriptors. */\n-\tuint16_t rx_tail; /**< current value of RDT register. */\n-\tuint16_t nb_rx_hold; /**< number of held free RX desc. */\n-\tuint16_t rx_free_thresh; /**< max free RX desc to hold. */\n-\tuint16_t queue_id; /**< RX queue index. */\n-\tuint16_t reg_idx; /**< RX queue register index. */\n-\tuint16_t port_id; /**< Device port identifier. */\n-\tuint8_t pthresh; /**< Prefetch threshold register. */\n-\tuint8_t hthresh; /**< Host threshold register. */\n-\tuint8_t wthresh; /**< Write-back threshold register. */\n-\tuint8_t crc_len; /**< 0 if CRC stripped, 4 otherwise. */\n-\tuint8_t drop_en;\t/**< If not 0, set SRRCTL.Drop_En. */\n-\tuint32_t flags; /**< RX flags. */\n-\tuint64_t\t offloads; /**< offloads of RTE_ETH_RX_OFFLOAD_* */\n-};\n-\n-/** Offload features */\n-union igc_tx_offload {\n-\tuint64_t data;\n-\tstruct {\n-\t\tuint64_t l3_len:9; /**< L3 (IP) Header Length. */\n-\t\tuint64_t l2_len:7; /**< L2 (MAC) Header Length. */\n-\t\tuint64_t vlan_tci:16;\n-\t\t/**< VLAN Tag Control Identifier(CPU order). */\n-\t\tuint64_t l4_len:8; /**< L4 (TCP/UDP) Header Length. */\n-\t\tuint64_t tso_segsz:16; /**< TCP TSO segment size. */\n-\t\t/* uint64_t unused:8; */\n-\t};\n-};\n-\n-/*\n- * Compare mask for igc_tx_offload.data,\n- * should be in sync with igc_tx_offload layout.\n- */\n-#define TX_MACIP_LEN_CMP_MASK\t0x000000000000FFFFULL /**< L2L3 header mask. */\n-#define TX_VLAN_CMP_MASK\t0x00000000FFFF0000ULL /**< Vlan mask. */\n-#define TX_TCP_LEN_CMP_MASK\t0x000000FF00000000ULL /**< TCP header mask. */\n-#define TX_TSO_MSS_CMP_MASK\t0x00FFFF0000000000ULL /**< TSO segsz mask. */\n-/** Mac + IP + TCP + Mss mask. */\n-#define TX_TSO_CMP_MASK\t\\\n-\t(TX_MACIP_LEN_CMP_MASK | TX_TCP_LEN_CMP_MASK | TX_TSO_MSS_CMP_MASK)\n-\n-/**\n- * Structure to check if new context need be built\n- */\n-struct igc_advctx_info {\n-\tuint64_t flags; /**< ol_flags related to context build. */\n-\t/** tx offload: vlan, tso, l2-l3-l4 lengths. */\n-\tunion igc_tx_offload tx_offload;\n-\t/** compare mask for tx offload. */\n-\tunion igc_tx_offload tx_offload_mask;\n-};\n-\n-/**\n- * Hardware context number\n- */\n-enum {\n-\tIGC_CTX_0 = 0, /**< CTX0 */\n-\tIGC_CTX_1 = 1, /**< CTX1 */\n-\tIGC_CTX_NUM = 2, /**< CTX_NUM */\n-};\n-\n-/**\n- * Structure associated with each descriptor of the TX ring of a TX queue.\n- */\n-struct igc_tx_entry {\n-\tstruct rte_mbuf *mbuf; /**< mbuf associated with TX desc, if any. */\n-\tuint16_t next_id; /**< Index of next descriptor in ring. */\n-\tuint16_t last_id; /**< Index of last scattered descriptor. */\n-};\n-\n-/**\n- * Structure associated with each TX queue.\n- */\n-struct igc_tx_queue {\n-\tvolatile union igc_adv_tx_desc *tx_ring; /**< TX ring address */\n-\tuint64_t tx_ring_phys_addr; /**< TX ring DMA address. */\n-\tstruct igc_tx_entry *sw_ring; /**< virtual address of SW ring. */\n-\tvolatile uint32_t *tdt_reg_addr; /**< Address of TDT register. */\n-\tuint32_t txd_type; /**< Device-specific TXD type */\n-\tuint16_t nb_tx_desc; /**< number of TX descriptors. */\n-\tuint16_t tx_tail; /**< Current value of TDT register. */\n-\tuint16_t tx_head;\n-\t/**< Index of first used TX descriptor. */\n-\tuint16_t queue_id; /**< TX queue index. */\n-\tuint16_t reg_idx; /**< TX queue register index. */\n-\tuint16_t port_id; /**< Device port identifier. */\n-\tuint8_t pthresh; /**< Prefetch threshold register. */\n-\tuint8_t hthresh; /**< Host threshold register. */\n-\tuint8_t wthresh; /**< Write-back threshold register. */\n-\tuint8_t ctx_curr;\n-\n-\t/**< Start context position for transmit queue. */\n-\tstruct igc_advctx_info ctx_cache[IGC_CTX_NUM];\n-\t/**< Hardware context history.*/\n-\tuint64_t\t offloads; /**< offloads of RTE_ETH_TX_OFFLOAD_* */\n-};\n-\n static inline uint64_t\n rx_desc_statuserr_to_pkt_flags(uint32_t statuserr)\n {\ndiff --git a/drivers/net/igc/igc_txrx.h b/drivers/net/igc/igc_txrx.h\nindex 02a0a05..5731761 100644\n--- a/drivers/net/igc/igc_txrx.h\n+++ b/drivers/net/igc/igc_txrx.h\n@@ -11,6 +11,121 @@\n extern \"C\" {\n #endif\n \n+struct igc_rx_entry {\n+\tstruct rte_mbuf *mbuf; /**< mbuf associated with RX descriptor. */\n+};\n+\n+/**\n+ * Structure associated with each RX queue.\n+ */\n+struct igc_rx_queue {\n+\tstruct rte_mempool *mb_pool; /**< mbuf pool to populate RX ring. */\n+\tvolatile union igc_adv_rx_desc *rx_ring;\n+\t/**< RX ring virtual address. */\n+\tuint64_t rx_ring_phys_addr; /**< RX ring DMA address. */\n+\tvolatile uint32_t *rdt_reg_addr; /**< RDT register address. */\n+\tvolatile uint32_t *rdh_reg_addr; /**< RDH register address. */\n+\tstruct igc_rx_entry *sw_ring; /**< address of RX software ring. */\n+\tstruct rte_mbuf *pkt_first_seg; /**< First segment of current packet. */\n+\tstruct rte_mbuf *pkt_last_seg; /**< Last segment of current packet. */\n+\tuint16_t nb_rx_desc; /**< number of RX descriptors. */\n+\tuint16_t rx_tail; /**< current value of RDT register. */\n+\tuint16_t nb_rx_hold; /**< number of held free RX desc. */\n+\tuint16_t rx_free_thresh; /**< max free RX desc to hold. */\n+\tuint16_t queue_id; /**< RX queue index. */\n+\tuint16_t reg_idx; /**< RX queue register index. */\n+\tuint16_t port_id; /**< Device port identifier. */\n+\tuint8_t pthresh; /**< Prefetch threshold register. */\n+\tuint8_t hthresh; /**< Host threshold register. */\n+\tuint8_t wthresh; /**< Write-back threshold register. */\n+\tuint8_t crc_len; /**< 0 if CRC stripped, 4 otherwise. */\n+\tuint8_t drop_en; /**< If not 0, set SRRCTL.Drop_En. */\n+\tuint32_t flags; /**< RX flags. */\n+\tuint64_t offloads; /**< offloads of RTE_ETH_RX_OFFLOAD_* */\n+};\n+\n+/** Offload features */\n+union igc_tx_offload {\n+\tuint64_t data;\n+\tstruct {\n+\t\tuint64_t l3_len:9; /**< L3 (IP) Header Length. */\n+\t\tuint64_t l2_len:7; /**< L2 (MAC) Header Length. */\n+\t\tuint64_t vlan_tci:16;\n+\t\t/**< VLAN Tag Control Identifier(CPU order). */\n+\t\tuint64_t l4_len:8; /**< L4 (TCP/UDP) Header Length. */\n+\t\tuint64_t tso_segsz:16; /**< TCP TSO segment size. */\n+\t\t/* uint64_t unused:8; */\n+\t};\n+};\n+\n+/**\n+ * Compare mask for igc_tx_offload.data,\n+ * should be in sync with igc_tx_offload layout.\n+ */\n+#define TX_MACIP_LEN_CMP_MASK 0x000000000000FFFFULL /**< L2L3 header mask. */\n+#define TX_VLAN_CMP_MASK 0x00000000FFFF0000ULL /**< Vlan mask. */\n+#define TX_TCP_LEN_CMP_MASK 0x000000FF00000000ULL /**< TCP header mask. */\n+#define TX_TSO_MSS_CMP_MASK 0x00FFFF0000000000ULL /**< TSO segsz mask. */\n+/** Mac + IP + TCP + Mss mask. */\n+#define TX_TSO_CMP_MASK \\\n+\t(TX_MACIP_LEN_CMP_MASK | TX_TCP_LEN_CMP_MASK | TX_TSO_MSS_CMP_MASK)\n+\n+/**\n+ * Structure to check if new context need be built\n+ */\n+struct igc_advctx_info {\n+\tuint64_t flags; /**< ol_flags related to context build. */\n+\t/** tx offload: vlan, tso, l2-l3-l4 lengths. */\n+\tunion igc_tx_offload tx_offload;\n+\t/** compare mask for tx offload. */\n+\tunion igc_tx_offload tx_offload_mask;\n+};\n+\n+/**\n+ * Hardware context number\n+ */\n+enum {\n+\tIGC_CTX_0 = 0, /**< CTX0 */\n+\tIGC_CTX_1 = 1, /**< CTX1 */\n+\tIGC_CTX_NUM = 2, /**< CTX_NUM */\n+};\n+\n+/**\n+ * Structure associated with each descriptor of the TX ring of a TX queue.\n+ */\n+struct igc_tx_entry {\n+\tstruct rte_mbuf *mbuf; /**< mbuf associated with TX desc, if any. */\n+\tuint16_t next_id; /**< Index of next descriptor in ring. */\n+\tuint16_t last_id; /**< Index of last scattered descriptor. */\n+};\n+\n+/**\n+ * Structure associated with each TX queue.\n+ */\n+struct igc_tx_queue {\n+\tvolatile union igc_adv_tx_desc *tx_ring; /**< TX ring address */\n+\tuint64_t tx_ring_phys_addr; /**< TX ring DMA address. */\n+\tstruct igc_tx_entry *sw_ring; /**< virtual address of SW ring. */\n+\tvolatile uint32_t *tdt_reg_addr; /**< Address of TDT register. */\n+\tuint32_t txd_type; /**< Device-specific TXD type */\n+\tuint16_t nb_tx_desc; /**< number of TX descriptors. */\n+\tuint16_t tx_tail; /**< Current value of TDT register. */\n+\tuint16_t tx_head;\n+\t/**< Index of first used TX descriptor. */\n+\tuint16_t queue_id; /**< TX queue index. */\n+\tuint16_t reg_idx; /**< TX queue register index. */\n+\tuint16_t port_id; /**< Device port identifier. */\n+\tuint8_t pthresh; /**< Prefetch threshold register. */\n+\tuint8_t hthresh; /**< Host threshold register. */\n+\tuint8_t wthresh; /**< Write-back threshold register. */\n+\tuint8_t ctx_curr;\n+\n+\t/**< Start context position for transmit queue. */\n+\tstruct igc_advctx_info ctx_cache[IGC_CTX_NUM];\n+\t/**< Hardware context history.*/\n+\tuint64_t offloads; /**< offloads of RTE_ETH_TX_OFFLOAD_* */\n+};\n+\n /*\n * RX/TX function prototypes\n */\n", "prefixes": [ "v2", "1/3" ] }