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{
    "id": 121357,
    "url": "http://patches.dpdk.org/api/patches/121357/?format=api",
    "web_url": "http://patches.dpdk.org/project/dpdk/patch/20221223112632.1281139-1-rkudurumalla@marvell.com/",
    "project": {
        "id": 1,
        "url": "http://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<20221223112632.1281139-1-rkudurumalla@marvell.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/20221223112632.1281139-1-rkudurumalla@marvell.com",
    "date": "2022-12-23T11:26:32",
    "name": "[1/1] common/cnxk: add mbox locking",
    "commit_ref": null,
    "pull_url": null,
    "state": "superseded",
    "archived": true,
    "hash": "c278c7f02772d07ad98bfda70db334ed5b92b291",
    "submitter": {
        "id": 2289,
        "url": "http://patches.dpdk.org/api/people/2289/?format=api",
        "name": "Rakesh Kudurumalla",
        "email": "rkudurumalla@marvell.com"
    },
    "delegate": {
        "id": 310,
        "url": "http://patches.dpdk.org/api/users/310/?format=api",
        "username": "jerin",
        "first_name": "Jerin",
        "last_name": "Jacob",
        "email": "jerinj@marvell.com"
    },
    "mbox": "http://patches.dpdk.org/project/dpdk/patch/20221223112632.1281139-1-rkudurumalla@marvell.com/mbox/",
    "series": [
        {
            "id": 26262,
            "url": "http://patches.dpdk.org/api/series/26262/?format=api",
            "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=26262",
            "date": "2022-12-23T11:26:32",
            "name": "[1/1] common/cnxk: add mbox locking",
            "version": 1,
            "mbox": "http://patches.dpdk.org/series/26262/mbox/"
        }
    ],
    "comments": "http://patches.dpdk.org/api/patches/121357/comments/",
    "check": "fail",
    "checks": "http://patches.dpdk.org/api/patches/121357/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@inbox.dpdk.org",
        "Delivered-To": "patchwork@inbox.dpdk.org",
        "Received": [
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        ],
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        "From": "Rakesh Kudurumalla <rkudurumalla@marvell.com>",
        "To": "Nithin Dabilpuram <ndabilpuram@marvell.com>, Kiran Kumar K\n <kirankumark@marvell.com>, Sunil Kumar Kori <skori@marvell.com>, Satha Rao\n <skoteshwar@marvell.com>",
        "CC": "<dev@dpdk.org>, <jerinj@marvell.com>, Rakesh Kudurumalla\n <rkudurumalla@marvell.com>",
        "Subject": "[PATCH 1/1] common/cnxk: add mbox locking",
        "Date": "Fri, 23 Dec 2022 16:56:32 +0530",
        "Message-ID": "<20221223112632.1281139-1-rkudurumalla@marvell.com>",
        "X-Mailer": "git-send-email 2.25.1",
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        "Content-Type": "text/plain",
        "X-Proofpoint-ORIG-GUID": "Am_5ldAMW0pzjeU3PxKQBCvtz8rVe3n7",
        "X-Proofpoint-GUID": "Am_5ldAMW0pzjeU3PxKQBCvtz8rVe3n7",
        "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.205,Aquarius:18.0.923,Hydra:6.0.545,FMLib:17.11.122.1\n definitions=2022-12-23_05,2022-12-22_03,2022-06-22_01",
        "X-BeenThere": "dev@dpdk.org",
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        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
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        "Errors-To": "dev-bounces@dpdk.org"
    },
    "content": "this patch adds mbox locking using spinlock\nto have different subsystems sharing same mbox\n\nSigned-off-by: Rakesh Kudurumalla <rkudurumalla@marvell.com>\n---\n drivers/common/cnxk/cnxk_telemetry_npa.c |  24 +-\n drivers/common/cnxk/roc_cpt.c            | 195 +++++++++++-----\n drivers/common/cnxk/roc_cpt_debug.c      |  40 +++-\n drivers/common/cnxk/roc_dev.c            |  19 +-\n drivers/common/cnxk/roc_idev.c           |   1 +\n drivers/common/cnxk/roc_idev_priv.h      |   1 +\n drivers/common/cnxk/roc_mbox.c           |  11 +-\n drivers/common/cnxk/roc_mbox_priv.h      |  15 ++\n drivers/common/cnxk/roc_nix.c            |  78 +++++--\n drivers/common/cnxk/roc_nix_bpf.c        | 278 +++++++++++++++--------\n drivers/common/cnxk/roc_nix_debug.c      |  40 ++--\n drivers/common/cnxk/roc_nix_fc.c         | 137 ++++++-----\n drivers/common/cnxk/roc_nix_inl.c        |  16 +-\n drivers/common/cnxk/roc_nix_inl_dev.c    |  83 +++++--\n drivers/common/cnxk/roc_nix_mac.c        | 202 ++++++++++------\n drivers/common/cnxk/roc_nix_mcast.c      |  57 +++--\n drivers/common/cnxk/roc_nix_npc.c        |  69 ++++--\n drivers/common/cnxk/roc_nix_ops.c        | 185 +++++++++------\n drivers/common/cnxk/roc_nix_ptp.c        |  77 ++++---\n drivers/common/cnxk/roc_nix_queue.c      | 237 +++++++++++++------\n drivers/common/cnxk/roc_nix_rss.c        |  64 ++++--\n drivers/common/cnxk/roc_nix_stats.c      |  77 +++++--\n drivers/common/cnxk/roc_nix_tm.c         | 103 ++++++---\n drivers/common/cnxk/roc_nix_tm_mark.c    |  26 ++-\n drivers/common/cnxk/roc_nix_tm_ops.c     | 107 ++++++---\n drivers/common/cnxk/roc_nix_tm_utils.c   |  13 +-\n drivers/common/cnxk/roc_nix_vlan.c       | 103 ++++++---\n drivers/common/cnxk/roc_npa.c            | 213 ++++++++++++-----\n drivers/common/cnxk/roc_npa.h            |   3 +\n drivers/common/cnxk/roc_npa_debug.c      |  28 ++-\n drivers/common/cnxk/roc_npc.c            |  66 ++++--\n drivers/common/cnxk/roc_npc_mcam.c       | 116 ++++++----\n drivers/common/cnxk/roc_npc_mcam_dump.c  |   5 +-\n drivers/common/cnxk/roc_npc_utils.c      |  46 ++--\n drivers/common/cnxk/roc_sso.c            | 186 ++++++++++-----\n drivers/common/cnxk/roc_tim.c            |  82 ++++---\n drivers/common/cnxk/version.map          |   2 +\n 37 files changed, 2022 insertions(+), 983 deletions(-)",
    "diff": "diff --git a/drivers/common/cnxk/cnxk_telemetry_npa.c b/drivers/common/cnxk/cnxk_telemetry_npa.c\nindex b6ae108b10..4287eaf968 100644\n--- a/drivers/common/cnxk/cnxk_telemetry_npa.c\n+++ b/drivers/common/cnxk/cnxk_telemetry_npa.c\n@@ -62,10 +62,11 @@ cnxk_tel_npa_aura(int aura_id, struct plt_tel_data *d)\n \tif (plt_bitmap_get(lf->npa_bmp, aura_id))\n \t\treturn -1;\n \n-\treq = mbox_alloc_msg_npa_aq_enq(lf->mbox);\n+\treq = mbox_alloc_msg_npa_aq_enq(mbox_get(lf->mbox));\n \tif (!req) {\n \t\tplt_err(\"Failed to alloc aq enq for npa\");\n-\t\treturn -1;\n+\t\trc = -1;\n+\t\tgoto exit;\n \t}\n \n \treq->aura_id = aura_id;\n@@ -75,7 +76,7 @@ cnxk_tel_npa_aura(int aura_id, struct plt_tel_data *d)\n \trc = mbox_process_msg(lf->mbox, (void *)&rsp);\n \tif (rc) {\n \t\tplt_err(\"Failed to get pool(%d) context\", aura_id);\n-\t\treturn rc;\n+\t\tgoto exit;\n \t}\n \n \taura = &rsp->aura;\n@@ -110,7 +111,10 @@ cnxk_tel_npa_aura(int aura_id, struct plt_tel_data *d)\n \tCNXK_TEL_DICT_INT(d, aura, err_qint_idx, w5_);\n \tCNXK_TEL_DICT_U64(d, aura, thresh, w6_);\n \n-\treturn 0;\n+\trc = 0;\n+exit:\n+\tmbox_put(lf->mbox);\n+\treturn rc;\n }\n \n static int\n@@ -129,10 +133,11 @@ cnxk_tel_npa_pool(int pool_id, struct plt_tel_data *d)\n \tif (plt_bitmap_get(lf->npa_bmp, pool_id))\n \t\treturn -1;\n \n-\treq = mbox_alloc_msg_npa_aq_enq(lf->mbox);\n+\treq = mbox_alloc_msg_npa_aq_enq(mbox_get(lf->mbox));\n \tif (!req) {\n \t\tplt_err(\"Failed to alloc aq enq for npa\");\n-\t\treturn -1;\n+\t\trc = -1;\n+\t\tgoto exit;\n \t}\n \n \treq->aura_id = pool_id;\n@@ -142,7 +147,7 @@ cnxk_tel_npa_pool(int pool_id, struct plt_tel_data *d)\n \trc = mbox_process_msg(lf->mbox, (void *)&rsp);\n \tif (rc) {\n \t\tplt_err(\"Failed to get pool(%d) context\", pool_id);\n-\t\treturn rc;\n+\t\tgoto exit;\n \t}\n \n \tpool = &rsp->pool;\n@@ -176,7 +181,10 @@ cnxk_tel_npa_pool(int pool_id, struct plt_tel_data *d)\n \tCNXK_TEL_DICT_INT(d, pool, thresh_qint_idx, w8_);\n \tCNXK_TEL_DICT_INT(d, pool, err_qint_idx, w8_);\n \n-\treturn 0;\n+\trc = 0;\n+exit:\n+\tmbox_put(lf->mbox);\n+\treturn rc;\n }\n \n static int\ndiff --git a/drivers/common/cnxk/roc_cpt.c b/drivers/common/cnxk/roc_cpt.c\nindex fb97ec89b2..af337223d5 100644\n--- a/drivers/common/cnxk/roc_cpt.c\n+++ b/drivers/common/cnxk/roc_cpt.c\n@@ -225,11 +225,14 @@ cpt_lf_outb_cfg(struct dev *dev, uint16_t sso_pf_func, uint16_t nix_pf_func,\n \t\tuint8_t lf_id, bool ena)\n {\n \tstruct cpt_inline_ipsec_cfg_msg *req;\n-\tstruct mbox *mbox = dev->mbox;\n+\tstruct mbox *mbox = mbox_get(dev->mbox);\n+\tint rc;\n \n \treq = mbox_alloc_msg_cpt_inline_ipsec_cfg(mbox);\n-\tif (req == NULL)\n-\t\treturn -ENOSPC;\n+\tif (req == NULL) {\n+\t\trc = -ENOSPC;\n+\t\tgoto exit;\n+\t}\n \n \treq->dir = CPT_INLINE_OUTBOUND;\n \treq->slot = lf_id;\n@@ -241,7 +244,10 @@ cpt_lf_outb_cfg(struct dev *dev, uint16_t sso_pf_func, uint16_t nix_pf_func,\n \t\treq->enable = 0;\n \t}\n \n-\treturn mbox_process(mbox);\n+\trc = mbox_process(mbox);\n+exit:\n+\tmbox_put(mbox);\n+\treturn rc;\n }\n \n int\n@@ -266,13 +272,20 @@ roc_cpt_inline_ipsec_inb_cfg_read(struct roc_cpt *roc_cpt,\n {\n \tstruct cpt *cpt = roc_cpt_to_cpt_priv(roc_cpt);\n \tstruct dev *dev = &cpt->dev;\n+\tstruct mbox *mbox = mbox_get(dev->mbox);\n \tstruct msg_req *req;\n+\tint rc;\n \n-\treq = mbox_alloc_msg_nix_read_inline_ipsec_cfg(dev->mbox);\n-\tif (req == NULL)\n-\t\treturn -EIO;\n+\treq = mbox_alloc_msg_nix_read_inline_ipsec_cfg(mbox);\n+\tif (req == NULL) {\n+\t\trc = -EIO;\n+\t\tgoto exit;\n+\t}\n \n-\treturn mbox_process_msg(dev->mbox, (void *)&inb_cfg);\n+\trc = mbox_process_msg(mbox, (void *)&inb_cfg);\n+exit:\n+\tmbox_put(mbox);\n+\treturn rc;\n }\n \n int\n@@ -282,19 +295,25 @@ roc_cpt_inline_ipsec_inb_cfg(struct roc_cpt *roc_cpt, uint16_t param1,\n \tstruct cpt *cpt = roc_cpt_to_cpt_priv(roc_cpt);\n \tstruct cpt_rx_inline_lf_cfg_msg *req;\n \tstruct mbox *mbox;\n+\tint rc;\n \n-\tmbox = cpt->dev.mbox;\n+\tmbox = mbox_get(cpt->dev.mbox);\n \n \treq = mbox_alloc_msg_cpt_rx_inline_lf_cfg(mbox);\n-\tif (req == NULL)\n-\t\treturn -ENOSPC;\n+\tif (req == NULL) {\n+\t\trc = -ENOSPC;\n+\t\tgoto exit;\n+\t}\n \n \treq->sso_pf_func = idev_sso_pffunc_get();\n \treq->param1 = param1;\n \treq->param2 = param2;\n \treq->opcode = opcode;\n \n-\treturn mbox_process(mbox);\n+\trc = mbox_process(mbox);\n+exit:\n+\tmbox_put(mbox);\n+\treturn rc;\n }\n \n int\n@@ -303,10 +322,14 @@ roc_cpt_rxc_time_cfg(struct roc_cpt *roc_cpt, struct roc_cpt_rxc_time_cfg *cfg)\n \tstruct cpt *cpt = roc_cpt_to_cpt_priv(roc_cpt);\n \tstruct cpt_rxc_time_cfg_req *req;\n \tstruct dev *dev = &cpt->dev;\n+\tstruct mbox *mbox = mbox_get(dev->mbox);\n+\tint rc;\n \n-\treq = mbox_alloc_msg_cpt_rxc_time_cfg(dev->mbox);\n-\tif (req == NULL)\n-\t\treturn -ENOSPC;\n+\treq = mbox_alloc_msg_cpt_rxc_time_cfg(mbox);\n+\tif (req == NULL) {\n+\t\trc = -ENOSPC;\n+\t\tgoto exit;\n+\t}\n \n \treq->blkaddr = 0;\n \n@@ -321,18 +344,22 @@ roc_cpt_rxc_time_cfg(struct roc_cpt *roc_cpt, struct roc_cpt_rxc_time_cfg *cfg)\n \treq->active_limit = cfg->active_limit;\n \treq->active_thres = cfg->active_thres;\n \n-\treturn mbox_process(dev->mbox);\n+\trc = mbox_process(mbox);\n+exit:\n+\tmbox_put(mbox);\n+\treturn rc;\n }\n \n int\n cpt_get_msix_offset(struct dev *dev, struct msix_offset_rsp **msix_rsp)\n {\n-\tstruct mbox *mbox = dev->mbox;\n+\tstruct mbox *mbox = mbox_get(dev->mbox);\n \tint rc;\n \n \t/* Get MSIX vector offsets */\n \tmbox_alloc_msg_msix_offset(mbox);\n \trc = mbox_process_msg(mbox, (void *)msix_rsp);\n+\tmbox_put(mbox);\n \n \treturn rc;\n }\n@@ -340,55 +367,74 @@ cpt_get_msix_offset(struct dev *dev, struct msix_offset_rsp **msix_rsp)\n int\n cpt_lfs_attach(struct dev *dev, uint8_t blkaddr, bool modify, uint16_t nb_lf)\n {\n-\tstruct mbox *mbox = dev->mbox;\n+\tstruct mbox *mbox = mbox_get(dev->mbox);\n \tstruct rsrc_attach_req *req;\n+\tint rc;\n \n-\tif (blkaddr != RVU_BLOCK_ADDR_CPT0 && blkaddr != RVU_BLOCK_ADDR_CPT1)\n-\t\treturn -EINVAL;\n+\tif (blkaddr != RVU_BLOCK_ADDR_CPT0 && blkaddr != RVU_BLOCK_ADDR_CPT1) {\n+\t\trc = -EINVAL;\n+\t\tgoto exit;\n+\t}\n \n \t/* Attach CPT(lf) */\n \treq = mbox_alloc_msg_attach_resources(mbox);\n-\tif (req == NULL)\n-\t\treturn -ENOSPC;\n+\tif (req == NULL) {\n+\t\trc = -ENOSPC;\n+\t\tgoto exit;\n+\t}\n \n \treq->cptlfs = nb_lf;\n \treq->modify = modify;\n \treq->cpt_blkaddr = blkaddr;\n \n-\treturn mbox_process(mbox);\n+\trc = mbox_process(mbox);\n+exit:\n+\tmbox_put(mbox);\n+\treturn rc;\n }\n \n int\n cpt_lfs_detach(struct dev *dev)\n {\n-\tstruct mbox *mbox = dev->mbox;\n+\tstruct mbox *mbox = mbox_get(dev->mbox);\n \tstruct rsrc_detach_req *req;\n+\tint rc;\n \n \treq = mbox_alloc_msg_detach_resources(mbox);\n-\tif (req == NULL)\n-\t\treturn -ENOSPC;\n+\tif (req == NULL) {\n+\t\trc =  -ENOSPC;\n+\t\tgoto exit;\n+\t}\n \n \treq->cptlfs = 1;\n \treq->partial = 1;\n \n-\treturn mbox_process(mbox);\n+\trc = mbox_process(mbox);\n+exit:\n+\tmbox_put(mbox);\n+\treturn rc;\n }\n \n static int\n cpt_available_lfs_get(struct dev *dev, uint16_t *nb_lf)\n {\n-\tstruct mbox *mbox = dev->mbox;\n+\tstruct mbox *mbox = mbox_get(dev->mbox);\n \tstruct free_rsrcs_rsp *rsp;\n \tint rc;\n \n \tmbox_alloc_msg_free_rsrc_cnt(mbox);\n \n \trc = mbox_process_msg(mbox, (void *)&rsp);\n-\tif (rc)\n-\t\treturn -EIO;\n+\tif (rc) {\n+\t\trc = -EIO;\n+\t\tgoto exit;\n+\t}\n \n \t*nb_lf = PLT_MAX((uint16_t)rsp->cpt, (uint16_t)rsp->cpt1);\n-\treturn 0;\n+\trc = 0;\n+exit:\n+\tmbox_put(mbox);\n+\treturn rc;\n }\n \n int\n@@ -396,14 +442,19 @@ cpt_lfs_alloc(struct dev *dev, uint8_t eng_grpmsk, uint8_t blkaddr,\n \t      bool inl_dev_sso)\n {\n \tstruct cpt_lf_alloc_req_msg *req;\n-\tstruct mbox *mbox = dev->mbox;\n+\tstruct mbox *mbox = mbox_get(dev->mbox);\n+\tint rc;\n \n-\tif (blkaddr != RVU_BLOCK_ADDR_CPT0 && blkaddr != RVU_BLOCK_ADDR_CPT1)\n-\t\treturn -EINVAL;\n+\tif (blkaddr != RVU_BLOCK_ADDR_CPT0 && blkaddr != RVU_BLOCK_ADDR_CPT1) {\n+\t\trc = -EINVAL;\n+\t\tgoto exit;\n+\t}\n \n \treq = mbox_alloc_msg_cpt_lf_alloc(mbox);\n-\tif (!req)\n-\t\treturn -ENOSPC;\n+\tif (!req) {\n+\t\trc = -ENOSPC;\n+\t\tgoto exit;\n+\t}\n \n \treq->nix_pf_func = 0;\n \tif (inl_dev_sso && nix_inl_dev_pffunc_get())\n@@ -413,34 +464,49 @@ cpt_lfs_alloc(struct dev *dev, uint8_t eng_grpmsk, uint8_t blkaddr,\n \treq->eng_grpmsk = eng_grpmsk;\n \treq->blkaddr = blkaddr;\n \n-\treturn mbox_process(mbox);\n+\trc = mbox_process(mbox);\n+exit:\n+\tmbox_put(mbox);\n+\treturn rc;\n }\n \n int\n cpt_lfs_free(struct dev *dev)\n {\n-\tmbox_alloc_msg_cpt_lf_free(dev->mbox);\n+\tstruct mbox *mbox = mbox_get(dev->mbox);\n+\tint rc;\n \n-\treturn mbox_process(dev->mbox);\n+\tmbox_alloc_msg_cpt_lf_free(mbox);\n+\n+\trc = mbox_process(mbox);\n+\tmbox_put(mbox);\n+\treturn rc;\n }\n \n static int\n cpt_hardware_caps_get(struct dev *dev, struct roc_cpt *roc_cpt)\n {\n \tstruct cpt_caps_rsp_msg *rsp;\n+\tstruct mbox *mbox = mbox_get(dev->mbox);\n \tint ret;\n \n-\tmbox_alloc_msg_cpt_caps_get(dev->mbox);\n+\tmbox_alloc_msg_cpt_caps_get(mbox);\n \n-\tret = mbox_process_msg(dev->mbox, (void *)&rsp);\n-\tif (ret)\n-\t\treturn -EIO;\n+\tret = mbox_process_msg(mbox, (void *)&rsp);\n+\tif (ret) {\n+\t\tret = -EIO;\n+\t\tgoto exit;\n+\t}\n \n \troc_cpt->cpt_revision = rsp->cpt_revision;\n \tmbox_memcpy(roc_cpt->hw_caps, rsp->eng_caps,\n \t\t    sizeof(union cpt_eng_caps) * CPT_MAX_ENG_TYPES);\n \n-\treturn 0;\n+\tret = 0;\n+\n+exit:\n+\tmbox_put(mbox);\n+\treturn ret;\n }\n \n static uint32_t\n@@ -733,14 +799,21 @@ cpt_lf_reset(struct roc_cpt_lf *lf)\n {\n \tstruct cpt_lf_rst_req *req;\n \tstruct dev *dev = lf->dev;\n+\tstruct mbox *mbox = mbox_get(dev->mbox);\n+\tint rc;\n \n-\treq = mbox_alloc_msg_cpt_lf_reset(dev->mbox);\n-\tif (req == NULL)\n-\t\treturn -EIO;\n+\treq = mbox_alloc_msg_cpt_lf_reset(mbox);\n+\tif (req == NULL) {\n+\t\trc = -EIO;\n+\t\tgoto exit;\n+\t}\n \n \treq->slot = lf->lf_id;\n \n-\treturn mbox_process(dev->mbox);\n+\trc = mbox_process(mbox);\n+exit:\n+\tmbox_put(mbox);\n+\treturn rc;\n }\n \n static void\n@@ -878,11 +951,14 @@ roc_cpt_eng_grp_add(struct roc_cpt *roc_cpt, enum cpt_eng_type eng_type)\n \tstruct dev *dev = &cpt->dev;\n \tstruct cpt_eng_grp_req *req;\n \tstruct cpt_eng_grp_rsp *rsp;\n+\tstruct mbox *mbox = mbox_get(dev->mbox);\n \tint ret;\n \n-\treq = mbox_alloc_msg_cpt_eng_grp_get(dev->mbox);\n-\tif (req == NULL)\n-\t\treturn -EIO;\n+\treq = mbox_alloc_msg_cpt_eng_grp_get(mbox);\n+\tif (req == NULL) {\n+\t\tret = -EIO;\n+\t\tgoto exit;\n+\t}\n \n \tswitch (eng_type) {\n \tcase CPT_ENG_TYPE_AE:\n@@ -890,22 +966,29 @@ roc_cpt_eng_grp_add(struct roc_cpt *roc_cpt, enum cpt_eng_type eng_type)\n \tcase CPT_ENG_TYPE_IE:\n \t\tbreak;\n \tdefault:\n-\t\treturn -EINVAL;\n+\t\tret = -EINVAL;\n+\t\tgoto exit;\n \t}\n \n \treq->eng_type = eng_type;\n \tret = mbox_process_msg(dev->mbox, (void *)&rsp);\n-\tif (ret)\n-\t\treturn -EIO;\n+\tif (ret) {\n+\t\tret = -EIO;\n+\t\tgoto exit;\n+\t}\n \n \tif (rsp->eng_grp_num > 8) {\n \t\tplt_err(\"Invalid CPT engine group\");\n-\t\treturn -ENOTSUP;\n+\t\tret = -ENOTSUP;\n+\t\tgoto exit;\n \t}\n \n \troc_cpt->eng_grp[eng_type] = rsp->eng_grp_num;\n \n-\treturn rsp->eng_grp_num;\n+\tret = rsp->eng_grp_num;\n+exit:\n+\tmbox_put(mbox);\n+\treturn ret;\n }\n \n void\ndiff --git a/drivers/common/cnxk/roc_cpt_debug.c b/drivers/common/cnxk/roc_cpt_debug.c\nindex 5602e536af..dce3638507 100644\n--- a/drivers/common/cnxk/roc_cpt_debug.c\n+++ b/drivers/common/cnxk/roc_cpt_debug.c\n@@ -71,11 +71,14 @@ cpt_af_reg_read(struct roc_cpt *roc_cpt, uint64_t reg, uint64_t *val)\n \tstruct cpt *cpt = roc_cpt_to_cpt_priv(roc_cpt);\n \tstruct cpt_rd_wr_reg_msg *msg;\n \tstruct dev *dev = &cpt->dev;\n+\tstruct mbox *mbox = mbox_get(dev->mbox);\n \tint ret;\n \n-\tmsg = mbox_alloc_msg_cpt_rd_wr_register(dev->mbox);\n-\tif (msg == NULL)\n-\t\treturn -EIO;\n+\tmsg = mbox_alloc_msg_cpt_rd_wr_register(mbox);\n+\tif (msg == NULL) {\n+\t\tret = -EIO;\n+\t\tgoto exit;\n+\t}\n \n \tmsg->hdr.pcifunc = dev->pf_func;\n \n@@ -84,12 +87,17 @@ cpt_af_reg_read(struct roc_cpt *roc_cpt, uint64_t reg, uint64_t *val)\n \tmsg->ret_val = val;\n \n \tret = mbox_process_msg(dev->mbox, (void *)&msg);\n-\tif (ret)\n-\t\treturn -EIO;\n+\tif (ret) {\n+\t\tret =  -EIO;\n+\t\tgoto exit;\n+\t}\n \n \t*val = msg->val;\n \n-\treturn 0;\n+\tret = 0;\n+exit:\n+\tmbox_put(mbox);\n+\treturn ret;\n }\n \n static int\n@@ -99,16 +107,21 @@ cpt_sts_print(struct roc_cpt *roc_cpt)\n \tstruct dev *dev = &cpt->dev;\n \tstruct cpt_sts_req *req;\n \tstruct cpt_sts_rsp *rsp;\n+\tstruct mbox *mbox = mbox_get(dev->mbox);\n \tint ret;\n \n-\treq = mbox_alloc_msg_cpt_sts_get(dev->mbox);\n-\tif (req == NULL)\n-\t\treturn -EIO;\n+\treq = mbox_alloc_msg_cpt_sts_get(mbox);\n+\tif (req == NULL) {\n+\t\tret = -EIO;\n+\t\tgoto exit;\n+\t}\n \n \treq->blkaddr = 0;\n \tret = mbox_process_msg(dev->mbox, (void *)&rsp);\n-\tif (ret)\n-\t\treturn -EIO;\n+\tif (ret) {\n+\t\tret = -EIO;\n+\t\tgoto exit;\n+\t}\n \n \tplt_print(\"    %s:\\t0x%016\" PRIx64, \"inst_req_pc\", rsp->inst_req_pc);\n \tplt_print(\"    %s:\\t0x%016\" PRIx64, \"inst_lat_pc\", rsp->inst_lat_pc);\n@@ -161,7 +174,10 @@ cpt_sts_print(struct roc_cpt *roc_cpt)\n \tplt_print(\"    %s:\\t\\t0x%016\" PRIx64, \"cptclk_cnt\", rsp->cptclk_cnt);\n \tplt_print(\"    %s:\\t\\t0x%016\" PRIx64, \"diag\", rsp->diag);\n \n-\treturn 0;\n+\tret = 0;\n+exit:\n+\tmbox_put(mbox);\n+\treturn ret;\n }\n \n int\ndiff --git a/drivers/common/cnxk/roc_dev.c b/drivers/common/cnxk/roc_dev.c\nindex 59128a3552..32a6d2ca0c 100644\n--- a/drivers/common/cnxk/roc_dev.c\n+++ b/drivers/common/cnxk/roc_dev.c\n@@ -135,8 +135,6 @@ af_pf_wait_msg(struct dev *dev, uint16_t vf, int num_msg)\n \t/* Enable interrupts */\n \tplt_write64(~0ull, dev->bar2 + RVU_PF_INT_ENA_W1S);\n \n-\tplt_spinlock_lock(&mdev->mbox_lock);\n-\n \treq_hdr = (struct mbox_hdr *)((uintptr_t)mdev->mbase + mbox->rx_start);\n \tif (req_hdr->num_msgs != num_msg)\n \t\tplt_err(\"Routed messages: %d received: %d\", num_msg,\n@@ -203,7 +201,6 @@ af_pf_wait_msg(struct dev *dev, uint16_t vf, int num_msg)\n \n \t\toffset = mbox->rx_start + msg->next_msgoff;\n \t}\n-\tplt_spinlock_unlock(&mdev->mbox_lock);\n \n \treturn req_hdr->num_msgs;\n }\n@@ -225,6 +222,7 @@ vf_pf_process_msgs(struct dev *dev, uint16_t vf)\n \n \toffset = mbox->rx_start + PLT_ALIGN(sizeof(*req_hdr), MBOX_MSG_ALIGN);\n \n+\tmbox_get(dev->mbox);\n \tfor (i = 0; i < req_hdr->num_msgs; i++) {\n \t\tmsg = (struct mbox_msghdr *)((uintptr_t)mdev->mbase + offset);\n \t\tsize = mbox->rx_start + msg->next_msgoff - offset;\n@@ -278,6 +276,7 @@ vf_pf_process_msgs(struct dev *dev, uint16_t vf)\n \t\taf_pf_wait_msg(dev, vf, routed);\n \t\tmbox_reset(dev->mbox, 0);\n \t}\n+\tmbox_put(dev->mbox);\n \n \t/* Send mbox responses to VF */\n \tif (mdev->num_msgs) {\n@@ -1015,10 +1014,13 @@ static int\n dev_setup_shared_lmt_region(struct mbox *mbox, bool valid_iova, uint64_t iova)\n {\n \tstruct lmtst_tbl_setup_req *req;\n+\tint rc;\n \n-\treq = mbox_alloc_msg_lmtst_tbl_setup(mbox);\n-\tif (!req)\n-\t\treturn -ENOSPC;\n+\treq = mbox_alloc_msg_lmtst_tbl_setup(mbox_get(mbox));\n+\tif (!req) {\n+\t\trc = -ENOSPC;\n+\t\tgoto exit;\n+\t}\n \n \t/* This pcifunc is defined with primary pcifunc whose LMT address\n \t * will be shared. If call contains valid IOVA, following pcifunc\n@@ -1028,7 +1030,10 @@ dev_setup_shared_lmt_region(struct mbox *mbox, bool valid_iova, uint64_t iova)\n \treq->use_local_lmt_region = valid_iova;\n \treq->lmt_iova = iova;\n \n-\treturn mbox_process(mbox);\n+\trc = mbox_process(mbox);\n+exit:\n+\tmbox_put(mbox);\n+\treturn rc;\n }\n \n /* Total no of lines * size of each lmtline */\ndiff --git a/drivers/common/cnxk/roc_idev.c b/drivers/common/cnxk/roc_idev.c\nindex 4d2eff93ce..62a4fd8880 100644\n--- a/drivers/common/cnxk/roc_idev.c\n+++ b/drivers/common/cnxk/roc_idev.c\n@@ -40,6 +40,7 @@ idev_set_defaults(struct idev_cfg *idev)\n \tidev->cpt = NULL;\n \tidev->nix_inl_dev = NULL;\n \tplt_spinlock_init(&idev->nix_inl_dev_lock);\n+\tplt_spinlock_init(&idev->npa_dev_lock);\n \t__atomic_store_n(&idev->npa_refcnt, 0, __ATOMIC_RELEASE);\n }\n \ndiff --git a/drivers/common/cnxk/roc_idev_priv.h b/drivers/common/cnxk/roc_idev_priv.h\nindex 315cc6f52c..b97d2936a2 100644\n--- a/drivers/common/cnxk/roc_idev_priv.h\n+++ b/drivers/common/cnxk/roc_idev_priv.h\n@@ -33,6 +33,7 @@ struct idev_cfg {\n \tstruct nix_inl_dev *nix_inl_dev;\n \tstruct idev_nix_inl_cfg inl_cfg;\n \tplt_spinlock_t nix_inl_dev_lock;\n+\tplt_spinlock_t npa_dev_lock;\n };\n \n /* Generic */\ndiff --git a/drivers/common/cnxk/roc_mbox.c b/drivers/common/cnxk/roc_mbox.c\nindex 6f4ee68c5d..7dcd188ca7 100644\n--- a/drivers/common/cnxk/roc_mbox.c\n+++ b/drivers/common/cnxk/roc_mbox.c\n@@ -50,14 +50,12 @@ mbox_reset(struct mbox *mbox, int devid)\n \tstruct mbox_hdr *rx_hdr =\n \t\t(struct mbox_hdr *)((uintptr_t)mdev->mbase + mbox->rx_start);\n \n-\tplt_spinlock_lock(&mdev->mbox_lock);\n \tmdev->msg_size = 0;\n \tmdev->rsp_size = 0;\n \ttx_hdr->msg_size = 0;\n \ttx_hdr->num_msgs = 0;\n \trx_hdr->msg_size = 0;\n \trx_hdr->num_msgs = 0;\n-\tplt_spinlock_unlock(&mdev->mbox_lock);\n }\n \n int\n@@ -167,7 +165,6 @@ mbox_alloc_msg_rsp(struct mbox *mbox, int devid, int size, int size_rsp)\n \tstruct mbox_dev *mdev = &mbox->dev[devid];\n \tstruct mbox_msghdr *msghdr = NULL;\n \n-\tplt_spinlock_lock(&mdev->mbox_lock);\n \tsize = PLT_ALIGN(size, MBOX_MSG_ALIGN);\n \tsize_rsp = PLT_ALIGN(size_rsp, MBOX_MSG_ALIGN);\n \t/* Check if there is space in mailbox */\n@@ -191,7 +188,6 @@ mbox_alloc_msg_rsp(struct mbox *mbox, int devid, int size, int size_rsp)\n \tmdev->rsp_size += size_rsp;\n \tmsghdr->next_msgoff = mdev->msg_size + msgs_offset();\n exit:\n-\tplt_spinlock_unlock(&mdev->mbox_lock);\n \n \treturn msghdr;\n }\n@@ -409,11 +405,14 @@ send_ready_msg(struct mbox *mbox, uint16_t *pcifunc)\n \tstruct ready_msg_rsp *rsp;\n \tint rc;\n \n-\tmbox_alloc_msg_ready(mbox);\n+\tmbox_alloc_msg_ready(mbox_get(mbox));\n \n \trc = mbox_process_msg(mbox, (void *)&rsp);\n-\tif (rc)\n+\tif (rc) {\n+\t\tmbox_put(mbox);\n \t\treturn rc;\n+\t}\n+\tmbox_put(mbox);\n \n \tif (rsp->hdr.ver != MBOX_VERSION) {\n \t\tplt_err(\"Incompatible MBox versions(AF: 0x%04x Client: 0x%04x)\",\ndiff --git a/drivers/common/cnxk/roc_mbox_priv.h b/drivers/common/cnxk/roc_mbox_priv.h\nindex 84516fbd5f..4fafca6f72 100644\n--- a/drivers/common/cnxk/roc_mbox_priv.h\n+++ b/drivers/common/cnxk/roc_mbox_priv.h\n@@ -151,6 +151,21 @@ mbox_process_msg_tmo(struct mbox *mbox, void **msg, uint32_t tmo)\n \treturn mbox_get_rsp_tmo(mbox, 0, msg, tmo);\n }\n \n+static inline struct mbox *\n+mbox_get(struct mbox *mbox)\n+{\n+\tstruct mbox_dev *mdev = &mbox->dev[0];\n+\tplt_spinlock_lock(&mdev->mbox_lock);\n+\treturn mbox;\n+}\n+\n+static inline void\n+mbox_put(struct mbox *mbox)\n+{\n+\tstruct mbox_dev *mdev = &mbox->dev[0];\n+\tplt_spinlock_unlock(&mdev->mbox_lock);\n+}\n+\n int send_ready_msg(struct mbox *mbox, uint16_t *pf_func /* out */);\n int reply_invalid_msg(struct mbox *mbox, int devid, uint16_t pf_func,\n \t\t      uint16_t id);\ndiff --git a/drivers/common/cnxk/roc_nix.c b/drivers/common/cnxk/roc_nix.c\nindex 2a320cc291..fbf318a77d 100644\n--- a/drivers/common/cnxk/roc_nix.c\n+++ b/drivers/common/cnxk/roc_nix.c\n@@ -86,11 +86,14 @@ roc_nix_lf_inl_ipsec_cfg(struct roc_nix *roc_nix, struct roc_nix_ipsec_cfg *cfg,\n {\n \tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n \tstruct nix_inline_ipsec_lf_cfg *lf_cfg;\n-\tstruct mbox *mbox = (&nix->dev)->mbox;\n+\tstruct mbox *mbox = mbox_get((&nix->dev)->mbox);\n+\tint rc;\n \n \tlf_cfg = mbox_alloc_msg_nix_inline_ipsec_lf_cfg(mbox);\n-\tif (lf_cfg == NULL)\n-\t\treturn -ENOSPC;\n+\tif (lf_cfg == NULL) {\n+\t\trc = -ENOSPC;\n+\t\tgoto exit;\n+\t}\n \n \tif (enb) {\n \t\tlf_cfg->enable = 1;\n@@ -105,21 +108,30 @@ roc_nix_lf_inl_ipsec_cfg(struct roc_nix *roc_nix, struct roc_nix_ipsec_cfg *cfg,\n \t\tlf_cfg->enable = 0;\n \t}\n \n-\treturn mbox_process(mbox);\n+\trc = mbox_process(mbox);\n+exit:\n+\tmbox_put(mbox);\n+\treturn rc;\n }\n \n int\n roc_nix_cpt_ctx_cache_sync(struct roc_nix *roc_nix)\n {\n \tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n-\tstruct mbox *mbox = (&nix->dev)->mbox;\n+\tstruct mbox *mbox = mbox_get((&nix->dev)->mbox);\n \tstruct msg_req *req;\n+\tint rc;\n \n \treq = mbox_alloc_msg_cpt_ctx_cache_sync(mbox);\n-\tif (req == NULL)\n-\t\treturn -ENOSPC;\n+\tif (req == NULL) {\n+\t\trc = -ENOSPC;\n+\t\tgoto exit;\n+\t}\n \n-\treturn mbox_process(mbox);\n+\trc = mbox_process(mbox);\n+exit:\n+\tmbox_put(mbox);\n+\treturn rc;\n }\n \n int\n@@ -147,14 +159,14 @@ roc_nix_lf_alloc(struct roc_nix *roc_nix, uint32_t nb_rxq, uint32_t nb_txq,\n \t\t uint64_t rx_cfg)\n {\n \tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n-\tstruct mbox *mbox = (&nix->dev)->mbox;\n+\tstruct mbox *mbox = mbox_get((&nix->dev)->mbox);\n \tstruct nix_lf_alloc_req *req;\n \tstruct nix_lf_alloc_rsp *rsp;\n \tint rc = -ENOSPC;\n \n \treq = mbox_alloc_msg_nix_lf_alloc(mbox);\n \tif (req == NULL)\n-\t\treturn rc;\n+\t\tgoto fail;\n \treq->rq_cnt = nb_rxq;\n \treq->sq_cnt = nb_txq;\n \tif (roc_nix->tx_compl_ena)\n@@ -203,11 +215,14 @@ roc_nix_lf_alloc(struct roc_nix *roc_nix, uint32_t nb_rxq, uint32_t nb_txq,\n \tnix->nb_rx_queues = nb_rxq;\n \tnix->nb_tx_queues = nb_txq;\n \tnix->sqs = plt_zmalloc(sizeof(struct roc_nix_sq *) * nb_txq, 0);\n-\tif (!nix->sqs)\n-\t\treturn -ENOMEM;\n+\tif (!nix->sqs) {\n+\t\trc = -ENOMEM;\n+\t\tgoto fail;\n+\t}\n \n \tnix_tel_node_add(roc_nix);\n fail:\n+\tmbox_put(mbox);\n \treturn rc;\n }\n \n@@ -215,7 +230,7 @@ int\n roc_nix_lf_free(struct roc_nix *roc_nix)\n {\n \tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n-\tstruct mbox *mbox = (&nix->dev)->mbox;\n+\tstruct mbox *mbox = mbox_get((&nix->dev)->mbox);\n \tstruct nix_lf_free_req *req;\n \tstruct ndc_sync_op *ndc_req;\n \tint rc = -ENOSPC;\n@@ -226,7 +241,7 @@ roc_nix_lf_free(struct roc_nix *roc_nix)\n \t/* Sync NDC-NIX for LF */\n \tndc_req = mbox_alloc_msg_ndc_sync_op(mbox);\n \tif (ndc_req == NULL)\n-\t\treturn rc;\n+\t\tgoto exit;\n \tndc_req->nix_lf_tx_sync = 1;\n \tndc_req->nix_lf_rx_sync = 1;\n \trc = mbox_process(mbox);\n@@ -234,38 +249,46 @@ roc_nix_lf_free(struct roc_nix *roc_nix)\n \t\tplt_err(\"Error on NDC-NIX-[TX, RX] LF sync, rc %d\", rc);\n \n \treq = mbox_alloc_msg_nix_lf_free(mbox);\n-\tif (req == NULL)\n-\t\treturn -ENOSPC;\n+\tif (req == NULL) {\n+\t\trc = -ENOSPC;\n+\t\tgoto exit;\n+\t}\n \t/* Let AF driver free all this nix lf's\n \t * NPC entries allocated using NPC MBOX.\n \t */\n \treq->flags = 0;\n \n-\treturn mbox_process(mbox);\n+\trc = mbox_process(mbox);\n+exit:\n+\tmbox_put(mbox);\n+\treturn rc;\n }\n \n static inline int\n nix_lf_attach(struct dev *dev)\n {\n-\tstruct mbox *mbox = dev->mbox;\n+\tstruct mbox *mbox = mbox_get(dev->mbox);\n \tstruct rsrc_attach_req *req;\n \tint rc = -ENOSPC;\n \n \t/* Attach NIX(lf) */\n \treq = mbox_alloc_msg_attach_resources(mbox);\n \tif (req == NULL)\n-\t\treturn rc;\n+\t\tgoto exit;\n \treq->modify = true;\n \treq->nixlf = true;\n \n-\treturn mbox_process(mbox);\n+\trc = mbox_process(mbox);\n+exit:\n+\tmbox_put(mbox);\n+\treturn rc;\n }\n \n static inline int\n nix_lf_get_msix_offset(struct dev *dev, struct nix *nix)\n {\n \tstruct msix_offset_rsp *msix_rsp;\n-\tstruct mbox *mbox = dev->mbox;\n+\tstruct mbox *mbox = mbox_get(dev->mbox);\n \tint rc;\n \n \t/* Get MSIX vector offsets */\n@@ -274,30 +297,34 @@ nix_lf_get_msix_offset(struct dev *dev, struct nix *nix)\n \tif (rc == 0)\n \t\tnix->msixoff = msix_rsp->nix_msixoff;\n \n+\tmbox_put(mbox);\n \treturn rc;\n }\n \n static inline int\n nix_lf_detach(struct nix *nix)\n {\n-\tstruct mbox *mbox = (&nix->dev)->mbox;\n+\tstruct mbox *mbox = mbox_get((&nix->dev)->mbox);\n \tstruct rsrc_detach_req *req;\n \tint rc = -ENOSPC;\n \n \treq = mbox_alloc_msg_detach_resources(mbox);\n \tif (req == NULL)\n-\t\treturn rc;\n+\t\tgoto exit;\n \treq->partial = true;\n \treq->nixlf = true;\n \n-\treturn mbox_process(mbox);\n+\trc = mbox_process(mbox);\n+exit:\n+\tmbox_put(mbox);\n+\treturn rc;\n }\n \n static int\n roc_nix_get_hw_info(struct roc_nix *roc_nix)\n {\n \tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n-\tstruct mbox *mbox = (&nix->dev)->mbox;\n+\tstruct mbox *mbox = mbox_get((&nix->dev)->mbox);\n \tstruct nix_hw_info *hw_info;\n \tint rc;\n \n@@ -313,6 +340,7 @@ roc_nix_get_hw_info(struct roc_nix *roc_nix)\n \t\t\troc_nix->dwrr_mtu = hw_info->rpm_dwrr_mtu;\n \t}\n \n+\tmbox_put(mbox);\n \treturn rc;\n }\n \ndiff --git a/drivers/common/cnxk/roc_nix_bpf.c b/drivers/common/cnxk/roc_nix_bpf.c\nindex 55a831f833..d60396289b 100644\n--- a/drivers/common/cnxk/roc_nix_bpf.c\n+++ b/drivers/common/cnxk/roc_nix_bpf.c\n@@ -24,15 +24,6 @@ static uint8_t sw_to_hw_lvl_map[] = {NIX_RX_BAND_PROF_LAYER_LEAF,\n \t\t\t\t     NIX_RX_BAND_PROF_LAYER_MIDDLE,\n \t\t\t\t     NIX_RX_BAND_PROF_LAYER_TOP};\n \n-static inline struct mbox *\n-get_mbox(struct roc_nix *roc_nix)\n-{\n-\tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n-\tstruct dev *dev = &nix->dev;\n-\n-\treturn dev->mbox;\n-}\n-\n static inline uint64_t\n meter_rate_to_nix(uint64_t value, uint64_t *exponent_p, uint64_t *mantissa_p,\n \t\t  uint64_t *div_exp_p, uint32_t timeunit_p)\n@@ -313,12 +304,16 @@ int\n roc_nix_bpf_timeunit_get(struct roc_nix *roc_nix, uint32_t *time_unit)\n {\n \tstruct nix_bandprof_get_hwinfo_rsp *rsp;\n-\tstruct mbox *mbox = get_mbox(roc_nix);\n+\tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n+\tstruct dev *dev = &nix->dev;\n+\tstruct mbox *mbox = mbox_get(dev->mbox);\n \tstruct msg_req *req;\n \tint rc = -ENOSPC;\n \n-\tif (roc_model_is_cn9k())\n-\t\treturn NIX_ERR_HW_NOTSUP;\n+\tif (roc_model_is_cn9k()) {\n+\t\trc = NIX_ERR_HW_NOTSUP;\n+\t\tgoto exit;\n+\t}\n \n \treq = mbox_alloc_msg_nix_bandprof_get_hwinfo(mbox);\n \tif (req == NULL)\n@@ -331,6 +326,7 @@ roc_nix_bpf_timeunit_get(struct roc_nix *roc_nix, uint32_t *time_unit)\n \t*time_unit = rsp->policer_timeunit;\n \n exit:\n+\tmbox_put(mbox);\n \treturn rc;\n }\n \n@@ -340,16 +336,22 @@ roc_nix_bpf_count_get(struct roc_nix *roc_nix, uint8_t lvl_mask,\n {\n \tuint8_t mask = lvl_mask & NIX_BPF_LEVEL_F_MASK;\n \tstruct nix_bandprof_get_hwinfo_rsp *rsp;\n-\tstruct mbox *mbox = get_mbox(roc_nix);\n+\tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n+\tstruct dev *dev = &nix->dev;\n+\tstruct mbox *mbox = mbox_get(dev->mbox);\n \tuint8_t leaf_idx, mid_idx, top_idx;\n \tstruct msg_req *req;\n \tint rc = -ENOSPC;\n \n-\tif (roc_model_is_cn9k())\n-\t\treturn NIX_ERR_HW_NOTSUP;\n+\tif (roc_model_is_cn9k()) {\n+\t\trc = NIX_ERR_HW_NOTSUP;\n+\t\tgoto exit;\n+\t}\n \n-\tif (!mask)\n-\t\treturn NIX_ERR_PARAM;\n+\tif (!mask) {\n+\t\trc = NIX_ERR_PARAM;\n+\t\tgoto exit;\n+\t}\n \n \treq = mbox_alloc_msg_nix_bandprof_get_hwinfo(mbox);\n \tif (req == NULL)\n@@ -373,6 +375,7 @@ roc_nix_bpf_count_get(struct roc_nix *roc_nix, uint8_t lvl_mask,\n \t\tcount[top_idx] = rsp->prof_count[sw_to_hw_lvl_map[top_idx]];\n \n exit:\n+\tmbox_put(mbox);\n \treturn rc;\n }\n \n@@ -382,33 +385,45 @@ roc_nix_bpf_alloc(struct roc_nix *roc_nix, uint8_t lvl_mask,\n \t\t  struct roc_nix_bpf_objs *profs)\n {\n \tuint8_t mask = lvl_mask & NIX_BPF_LEVEL_F_MASK;\n-\tstruct mbox *mbox = get_mbox(roc_nix);\n+\tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n+\tstruct dev *dev = &nix->dev;\n+\tstruct mbox *mbox = mbox_get(dev->mbox);\n \tstruct nix_bandprof_alloc_req *req;\n \tstruct nix_bandprof_alloc_rsp *rsp;\n \tuint8_t leaf_idx, mid_idx, top_idx;\n \tint rc = -ENOSPC, i;\n \n-\tif (roc_model_is_cn9k())\n-\t\treturn NIX_ERR_HW_NOTSUP;\n+\tif (roc_model_is_cn9k()) {\n+\t\trc = NIX_ERR_HW_NOTSUP;\n+\t\tgoto exit;\n+\t}\n \n-\tif (!mask)\n-\t\treturn NIX_ERR_PARAM;\n+\tif (!mask) {\n+\t\trc = NIX_ERR_PARAM;\n+\t\tgoto exit;\n+\t}\n \n \tleaf_idx = roc_nix_bpf_level_to_idx(mask & ROC_NIX_BPF_LEVEL_F_LEAF);\n \tmid_idx = roc_nix_bpf_level_to_idx(mask & ROC_NIX_BPF_LEVEL_F_MID);\n \ttop_idx = roc_nix_bpf_level_to_idx(mask & ROC_NIX_BPF_LEVEL_F_TOP);\n \n \tif ((leaf_idx != ROC_NIX_BPF_LEVEL_IDX_INVALID) &&\n-\t    (per_lvl_cnt[leaf_idx] > NIX_MAX_BPF_COUNT_LEAF_LAYER))\n-\t\treturn NIX_ERR_INVALID_RANGE;\n+\t    (per_lvl_cnt[leaf_idx] > NIX_MAX_BPF_COUNT_LEAF_LAYER)) {\n+\t\trc = NIX_ERR_INVALID_RANGE;\n+\t\tgoto exit;\n+\t}\n \n \tif ((mid_idx != ROC_NIX_BPF_LEVEL_IDX_INVALID) &&\n-\t    (per_lvl_cnt[mid_idx] > NIX_MAX_BPF_COUNT_MID_LAYER))\n-\t\treturn NIX_ERR_INVALID_RANGE;\n+\t    (per_lvl_cnt[mid_idx] > NIX_MAX_BPF_COUNT_MID_LAYER)) {\n+\t\trc = NIX_ERR_INVALID_RANGE;\n+\t\tgoto exit;\n+\t}\n \n \tif ((top_idx != ROC_NIX_BPF_LEVEL_IDX_INVALID) &&\n-\t    (per_lvl_cnt[top_idx] > NIX_MAX_BPF_COUNT_TOP_LAYER))\n-\t\treturn NIX_ERR_INVALID_RANGE;\n+\t    (per_lvl_cnt[top_idx] > NIX_MAX_BPF_COUNT_TOP_LAYER)) {\n+\t\trc = NIX_ERR_INVALID_RANGE;\n+\t\tgoto exit;\n+\t}\n \n \treq = mbox_alloc_msg_nix_bandprof_alloc(mbox);\n \tif (req == NULL)\n@@ -464,6 +479,7 @@ roc_nix_bpf_alloc(struct roc_nix *roc_nix, uint8_t lvl_mask,\n \t}\n \n exit:\n+\tmbox_put(mbox);\n \treturn rc;\n }\n \n@@ -471,17 +487,23 @@ int\n roc_nix_bpf_free(struct roc_nix *roc_nix, struct roc_nix_bpf_objs *profs,\n \t\t uint8_t num_prof)\n {\n-\tstruct mbox *mbox = get_mbox(roc_nix);\n+\tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n+\tstruct dev *dev = &nix->dev;\n+\tstruct mbox *mbox = mbox_get(dev->mbox);\n \tstruct nix_bandprof_free_req *req;\n \tuint8_t level;\n-\tint i, j;\n+\tint i, j, rc;\n \n-\tif (num_prof >= NIX_RX_BAND_PROF_LAYER_MAX)\n-\t\treturn NIX_ERR_INVALID_RANGE;\n+\tif (num_prof >= NIX_RX_BAND_PROF_LAYER_MAX) {\n+\t\trc = NIX_ERR_INVALID_RANGE;\n+\t\tgoto exit;\n+\t}\n \n \treq = mbox_alloc_msg_nix_bandprof_free(mbox);\n-\tif (req == NULL)\n-\t\treturn -ENOSPC;\n+\tif (req == NULL) {\n+\t\trc = -ENOSPC;\n+\t\tgoto exit;\n+\t}\n \n \tfor (i = 0; i < num_prof; i++) {\n \t\tlevel = sw_to_hw_lvl_map[profs[i].level];\n@@ -490,21 +512,32 @@ roc_nix_bpf_free(struct roc_nix *roc_nix, struct roc_nix_bpf_objs *profs,\n \t\t\treq->prof_idx[level][j] = profs[i].ids[j];\n \t}\n \n-\treturn mbox_process(mbox);\n+\trc = mbox_process(mbox);\n+exit:\n+\tmbox_put(mbox);\n+\treturn rc;\n }\n \n int\n roc_nix_bpf_free_all(struct roc_nix *roc_nix)\n {\n-\tstruct mbox *mbox = get_mbox(roc_nix);\n+\tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n+\tstruct dev *dev = &nix->dev;\n+\tstruct mbox *mbox = mbox_get(dev->mbox);\n \tstruct nix_bandprof_free_req *req;\n+\tint rc;\n \n \treq = mbox_alloc_msg_nix_bandprof_free(mbox);\n-\tif (req == NULL)\n-\t\treturn -ENOSPC;\n+\tif (req == NULL) {\n+\t\trc = -ENOSPC;\n+\t\tgoto exit;\n+\t}\n \n \treq->free_all = true;\n-\treturn mbox_process(mbox);\n+\trc = mbox_process(mbox);\n+exit:\n+\tmbox_put(mbox);\n+\treturn rc;\n }\n \n int\n@@ -513,7 +546,9 @@ roc_nix_bpf_config(struct roc_nix *roc_nix, uint16_t id,\n \t\t   struct roc_nix_bpf_cfg *cfg)\n {\n \tuint64_t exponent_p = 0, mantissa_p = 0, div_exp_p = 0;\n-\tstruct mbox *mbox = get_mbox(roc_nix);\n+\tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n+\tstruct dev *dev = &nix->dev;\n+\tstruct mbox *mbox = dev->mbox;\n \tstruct nix_cn10k_aq_enq_req *aq;\n \tuint32_t policer_timeunit;\n \tuint8_t level_idx;\n@@ -533,9 +568,11 @@ roc_nix_bpf_config(struct roc_nix *roc_nix, uint16_t id,\n \tif (level_idx == ROC_NIX_BPF_LEVEL_IDX_INVALID)\n \t\treturn NIX_ERR_PARAM;\n \n-\taq = mbox_alloc_msg_nix_cn10k_aq_enq(mbox);\n-\tif (aq == NULL)\n-\t\treturn -ENOSPC;\n+\taq = mbox_alloc_msg_nix_cn10k_aq_enq(mbox_get(mbox));\n+\tif (aq == NULL) {\n+\t\trc = -ENOSPC;\n+\t\tgoto exit;\n+\t}\n \taq->qidx = (sw_to_hw_lvl_map[level_idx] << 14) | id;\n \taq->ctype = NIX_AQ_CTYPE_BAND_PROF;\n \taq->op = NIX_AQ_INSTOP_WRITE;\n@@ -631,7 +668,8 @@ roc_nix_bpf_config(struct roc_nix *roc_nix, uint16_t id,\n \t\tbreak;\n \n \tdefault:\n-\t\treturn NIX_ERR_PARAM;\n+\t\trc = NIX_ERR_PARAM;\n+\t\tgoto exit;\n \t}\n \n \taq->prof.lmode = cfg->lmode;\n@@ -652,7 +690,10 @@ roc_nix_bpf_config(struct roc_nix *roc_nix, uint16_t id,\n \taq->prof_mask.yc_action = ~(aq->prof_mask.yc_action);\n \taq->prof_mask.rc_action = ~(aq->prof_mask.rc_action);\n \n-\treturn mbox_process(mbox);\n+\trc = mbox_process(mbox);\n+exit:\n+\tmbox_put(mbox);\n+\treturn rc;\n }\n \n int\n@@ -660,19 +701,26 @@ roc_nix_bpf_ena_dis(struct roc_nix *roc_nix, uint16_t id, struct roc_nix_rq *rq,\n \t\t    bool enable)\n {\n \tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n-\tstruct mbox *mbox = get_mbox(roc_nix);\n+\tstruct dev *dev = &nix->dev;\n+\tstruct mbox *mbox = mbox_get(dev->mbox);\n \tstruct nix_cn10k_aq_enq_req *aq;\n \tint rc;\n \n-\tif (roc_model_is_cn9k())\n-\t\treturn NIX_ERR_HW_NOTSUP;\n+\tif (roc_model_is_cn9k()) {\n+\t\trc = NIX_ERR_HW_NOTSUP;\n+\t\tgoto exit;\n+\t}\n \n-\tif (rq->qid >= nix->nb_rx_queues)\n-\t\treturn NIX_ERR_QUEUE_INVALID_RANGE;\n+\tif (rq->qid >= nix->nb_rx_queues) {\n+\t\trc =  NIX_ERR_QUEUE_INVALID_RANGE;\n+\t\tgoto exit;\n+\t}\n \n \taq = mbox_alloc_msg_nix_cn10k_aq_enq(mbox);\n-\tif (aq == NULL)\n-\t\treturn -ENOSPC;\n+\tif (aq == NULL) {\n+\t\trc = -ENOSPC;\n+\t\tgoto exit;\n+\t}\n \taq->qidx = rq->qid;\n \taq->ctype = NIX_AQ_CTYPE_RQ;\n \taq->op = NIX_AQ_INSTOP_WRITE;\n@@ -691,6 +739,7 @@ roc_nix_bpf_ena_dis(struct roc_nix *roc_nix, uint16_t id, struct roc_nix_rq *rq,\n \trq->bpf_id = id;\n \n exit:\n+\tmbox_put(mbox);\n \treturn rc;\n }\n \n@@ -698,22 +747,30 @@ int\n roc_nix_bpf_dump(struct roc_nix *roc_nix, uint16_t id,\n \t\t enum roc_nix_bpf_level_flag lvl_flag)\n {\n-\tstruct mbox *mbox = get_mbox(roc_nix);\n+\tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n+\tstruct dev *dev = &nix->dev;\n+\tstruct mbox *mbox = mbox_get(dev->mbox);\n \tstruct nix_cn10k_aq_enq_rsp *rsp;\n \tstruct nix_cn10k_aq_enq_req *aq;\n \tuint8_t level_idx;\n \tint rc;\n \n-\tif (roc_model_is_cn9k())\n-\t\treturn NIX_ERR_HW_NOTSUP;\n+\tif (roc_model_is_cn9k()) {\n+\t\trc = NIX_ERR_HW_NOTSUP;\n+\t\tgoto exit;\n+\t}\n \n \tlevel_idx = roc_nix_bpf_level_to_idx(lvl_flag);\n-\tif (level_idx == ROC_NIX_BPF_LEVEL_IDX_INVALID)\n-\t\treturn NIX_ERR_PARAM;\n+\tif (level_idx == ROC_NIX_BPF_LEVEL_IDX_INVALID) {\n+\t\trc = NIX_ERR_PARAM;\n+\t\tgoto exit;\n+\t}\n \n \taq = mbox_alloc_msg_nix_cn10k_aq_enq(mbox);\n-\tif (aq == NULL)\n-\t\treturn -ENOSPC;\n+\tif (aq == NULL) {\n+\t\trc = -ENOSPC;\n+\t\tgoto exit;\n+\t}\n \taq->qidx = (sw_to_hw_lvl_map[level_idx] << 14 | id);\n \taq->ctype = NIX_AQ_CTYPE_BAND_PROF;\n \taq->op = NIX_AQ_INSTOP_READ;\n@@ -722,7 +779,8 @@ roc_nix_bpf_dump(struct roc_nix *roc_nix, uint16_t id,\n \t\tplt_dump(\"============= band prof id =%d ===============\", id);\n \t\tnix_lf_bpf_dump(&rsp->prof);\n \t}\n-\n+exit:\n+\tmbox_put(mbox);\n \treturn rc;\n }\n \n@@ -731,7 +789,9 @@ roc_nix_bpf_pre_color_tbl_setup(struct roc_nix *roc_nix, uint16_t id,\n \t\t\t\tenum roc_nix_bpf_level_flag lvl_flag,\n \t\t\t\tstruct roc_nix_bpf_precolor *tbl)\n {\n-\tstruct mbox *mbox = get_mbox(roc_nix);\n+\tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n+\tstruct dev *dev = &nix->dev;\n+\tstruct mbox *mbox = dev->mbox;\n \tstruct nix_cn10k_aq_enq_req *aq;\n \tuint8_t pc_mode, tn_ena;\n \tuint8_t level_idx;\n@@ -797,9 +857,11 @@ roc_nix_bpf_pre_color_tbl_setup(struct roc_nix *roc_nix, uint16_t id,\n \t}\n \n \t/* Update corresponding bandwidth profile too */\n-\taq = mbox_alloc_msg_nix_cn10k_aq_enq(mbox);\n-\tif (aq == NULL)\n-\t\treturn -ENOSPC;\n+\taq = mbox_alloc_msg_nix_cn10k_aq_enq(mbox_get(mbox));\n+\tif (aq == NULL) {\n+\t\trc = -ENOSPC;\n+\t\tgoto exit;\n+\t}\n \taq->qidx = (sw_to_hw_lvl_map[level_idx] << 14) | id;\n \taq->ctype = NIX_AQ_CTYPE_BAND_PROF;\n \taq->op = NIX_AQ_INSTOP_WRITE;\n@@ -808,9 +870,10 @@ roc_nix_bpf_pre_color_tbl_setup(struct roc_nix *roc_nix, uint16_t id,\n \taq->prof_mask.pc_mode = ~(aq->prof_mask.pc_mode);\n \taq->prof_mask.tnl_ena = ~(aq->prof_mask.tnl_ena);\n \n-\treturn mbox_process(mbox);\n+\trc = mbox_process(mbox);\n \n exit:\n+\tmbox_put(mbox);\n \treturn rc;\n }\n \n@@ -819,20 +882,29 @@ roc_nix_bpf_connect(struct roc_nix *roc_nix,\n \t\t    enum roc_nix_bpf_level_flag lvl_flag, uint16_t src_id,\n \t\t    uint16_t dst_id)\n {\n-\tstruct mbox *mbox = get_mbox(roc_nix);\n+\tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n+\tstruct dev *dev = &nix->dev;\n+\tstruct mbox *mbox = mbox_get(dev->mbox);\n \tstruct nix_cn10k_aq_enq_req *aq;\n \tuint8_t level_idx;\n+\tint rc;\n \n-\tif (roc_model_is_cn9k())\n-\t\treturn NIX_ERR_HW_NOTSUP;\n+\tif (roc_model_is_cn9k()) {\n+\t\trc = NIX_ERR_HW_NOTSUP;\n+\t\tgoto exit;\n+\t}\n \n \tlevel_idx = roc_nix_bpf_level_to_idx(lvl_flag);\n-\tif (level_idx == ROC_NIX_BPF_LEVEL_IDX_INVALID)\n-\t\treturn NIX_ERR_PARAM;\n+\tif (level_idx == ROC_NIX_BPF_LEVEL_IDX_INVALID) {\n+\t\trc = NIX_ERR_PARAM;\n+\t\tgoto exit;\n+\t}\n \n \taq = mbox_alloc_msg_nix_cn10k_aq_enq(mbox);\n-\tif (aq == NULL)\n-\t\treturn -ENOSPC;\n+\tif (aq == NULL) {\n+\t\trc = -ENOSPC;\n+\t\tgoto exit;\n+\t}\n \taq->qidx = (sw_to_hw_lvl_map[level_idx] << 14) | src_id;\n \taq->ctype = NIX_AQ_CTYPE_BAND_PROF;\n \taq->op = NIX_AQ_INSTOP_WRITE;\n@@ -847,7 +919,10 @@ roc_nix_bpf_connect(struct roc_nix *roc_nix,\n \t\taq->prof_mask.band_prof_id = ~(aq->prof_mask.band_prof_id);\n \t}\n \n-\treturn mbox_process(mbox);\n+\trc = mbox_process(mbox);\n+exit:\n+\tmbox_put(mbox);\n+\treturn rc;\n }\n \n int\n@@ -859,28 +934,36 @@ roc_nix_bpf_stats_read(struct roc_nix *roc_nix, uint16_t id, uint64_t mask,\n \tuint8_t green_octs_drop, yellow_octs_drop, red_octs_drop;\n \tuint8_t green_pkt_pass, green_octs_pass, green_pkt_drop;\n \tuint8_t red_pkt_pass, red_octs_pass, red_pkt_drop;\n-\tstruct mbox *mbox = get_mbox(roc_nix);\n+\tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n+\tstruct dev *dev = &nix->dev;\n+\tstruct mbox *mbox = mbox_get(dev->mbox);\n \tstruct nix_cn10k_aq_enq_rsp *rsp;\n \tstruct nix_cn10k_aq_enq_req *aq;\n \tuint8_t level_idx;\n \tint rc;\n \n-\tif (roc_model_is_cn9k())\n-\t\treturn NIX_ERR_HW_NOTSUP;\n+\tif (roc_model_is_cn9k()) {\n+\t\trc = NIX_ERR_HW_NOTSUP;\n+\t\tgoto exit;\n+\t}\n \n \tlevel_idx = roc_nix_bpf_level_to_idx(lvl_flag);\n-\tif (level_idx == ROC_NIX_BPF_LEVEL_IDX_INVALID)\n-\t\treturn NIX_ERR_PARAM;\n+\tif (level_idx == ROC_NIX_BPF_LEVEL_IDX_INVALID) {\n+\t\trc = NIX_ERR_PARAM;\n+\t\tgoto exit;\n+\t}\n \n \taq = mbox_alloc_msg_nix_cn10k_aq_enq(mbox);\n-\tif (aq == NULL)\n-\t\treturn -ENOSPC;\n+\tif (aq == NULL) {\n+\t\trc = -ENOSPC;\n+\t\tgoto exit;\n+\t}\n \taq->qidx = (sw_to_hw_lvl_map[level_idx] << 14 | id);\n \taq->ctype = NIX_AQ_CTYPE_BAND_PROF;\n \taq->op = NIX_AQ_INSTOP_READ;\n \trc = mbox_process_msg(mbox, (void *)&rsp);\n \tif (rc)\n-\t\treturn rc;\n+\t\tgoto exit;\n \n \tgreen_pkt_pass =\n \t\troc_nix_bpf_stats_to_idx(mask & ROC_NIX_BPF_GREEN_PKT_F_PASS);\n@@ -943,27 +1026,39 @@ roc_nix_bpf_stats_read(struct roc_nix *roc_nix, uint16_t id, uint64_t mask,\n \tif (red_octs_drop != ROC_NIX_BPF_STATS_MAX)\n \t\tstats[red_octs_drop] = rsp->prof.red_octs_drop;\n \n-\treturn 0;\n+\trc = 0;\n+exit:\n+\tmbox_put(mbox);\n+\treturn rc;\n }\n \n int\n roc_nix_bpf_stats_reset(struct roc_nix *roc_nix, uint16_t id, uint64_t mask,\n \t\t\tenum roc_nix_bpf_level_flag lvl_flag)\n {\n-\tstruct mbox *mbox = get_mbox(roc_nix);\n+\tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n+\tstruct dev *dev = &nix->dev;\n+\tstruct mbox *mbox = mbox_get(dev->mbox);\n \tstruct nix_cn10k_aq_enq_req *aq;\n \tuint8_t level_idx;\n+\tint rc;\n \n-\tif (roc_model_is_cn9k())\n-\t\treturn NIX_ERR_HW_NOTSUP;\n+\tif (roc_model_is_cn9k()) {\n+\t\trc = NIX_ERR_HW_NOTSUP;\n+\t\tgoto exit;\n+\t}\n \n \tlevel_idx = roc_nix_bpf_level_to_idx(lvl_flag);\n-\tif (level_idx == ROC_NIX_BPF_LEVEL_IDX_INVALID)\n-\t\treturn NIX_ERR_PARAM;\n+\tif (level_idx == ROC_NIX_BPF_LEVEL_IDX_INVALID) {\n+\t\trc = NIX_ERR_PARAM;\n+\t\tgoto exit;\n+\t}\n \n \taq = mbox_alloc_msg_nix_cn10k_aq_enq(mbox);\n-\tif (aq == NULL)\n-\t\treturn -ENOSPC;\n+\tif (aq == NULL) {\n+\t\trc = -ENOSPC;\n+\t\tgoto exit;\n+\t}\n \taq->qidx = (sw_to_hw_lvl_map[level_idx] << 14 | id);\n \taq->ctype = NIX_AQ_CTYPE_BAND_PROF;\n \taq->op = NIX_AQ_INSTOP_WRITE;\n@@ -1023,7 +1118,10 @@ roc_nix_bpf_stats_reset(struct roc_nix *roc_nix, uint16_t id, uint64_t mask,\n \t\taq->prof_mask.red_octs_drop = ~(aq->prof_mask.red_octs_drop);\n \t}\n \n-\treturn mbox_process(mbox);\n+\trc = mbox_process(mbox);\n+exit:\n+\tmbox_put(mbox);\n+\treturn rc;\n }\n \n int\ndiff --git a/drivers/common/cnxk/roc_nix_debug.c b/drivers/common/cnxk/roc_nix_debug.c\nindex 6f82350b53..2c354b44bf 100644\n--- a/drivers/common/cnxk/roc_nix_debug.c\n+++ b/drivers/common/cnxk/roc_nix_debug.c\n@@ -332,17 +332,18 @@ roc_nix_lf_reg_dump(struct roc_nix *roc_nix, uint64_t *data)\n int\n nix_q_ctx_get(struct dev *dev, uint8_t ctype, uint16_t qid, __io void **ctx_p)\n {\n-\tstruct mbox *mbox = dev->mbox;\n+\tstruct mbox *mbox = mbox_get(dev->mbox);\n \tint rc;\n \n \tif (roc_model_is_cn9k()) {\n \t\tstruct nix_aq_enq_rsp *rsp;\n \t\tstruct nix_aq_enq_req *aq;\n-\t\tint rc;\n \n \t\taq = mbox_alloc_msg_nix_aq_enq(mbox);\n-\t\tif (!aq)\n-\t\t\treturn -ENOSPC;\n+\t\tif (!aq) {\n+\t\t\trc = -ENOSPC;\n+\t\t\tgoto exit;\n+\t\t}\n \n \t\taq->qidx = qid;\n \t\taq->ctype = ctype;\n@@ -350,7 +351,7 @@ nix_q_ctx_get(struct dev *dev, uint8_t ctype, uint16_t qid, __io void **ctx_p)\n \n \t\trc = mbox_process_msg(mbox, (void *)&rsp);\n \t\tif (rc)\n-\t\t\treturn rc;\n+\t\t\tgoto exit;\n \t\tif (ctype == NIX_AQ_CTYPE_RQ)\n \t\t\t*ctx_p = &rsp->rq;\n \t\telse if (ctype == NIX_AQ_CTYPE_SQ)\n@@ -362,8 +363,10 @@ nix_q_ctx_get(struct dev *dev, uint8_t ctype, uint16_t qid, __io void **ctx_p)\n \t\tstruct nix_cn10k_aq_enq_req *aq;\n \n \t\taq = mbox_alloc_msg_nix_cn10k_aq_enq(mbox);\n-\t\tif (!aq)\n-\t\t\treturn -ENOSPC;\n+\t\tif (!aq) {\n+\t\t\trc = -ENOSPC;\n+\t\t\tgoto exit;\n+\t\t}\n \n \t\taq->qidx = qid;\n \t\taq->ctype = ctype;\n@@ -371,7 +374,7 @@ nix_q_ctx_get(struct dev *dev, uint8_t ctype, uint16_t qid, __io void **ctx_p)\n \n \t\trc = mbox_process_msg(mbox, (void *)&rsp);\n \t\tif (rc)\n-\t\t\treturn rc;\n+\t\t\tgoto exit;\n \n \t\tif (ctype == NIX_AQ_CTYPE_RQ)\n \t\t\t*ctx_p = &rsp->rq;\n@@ -380,7 +383,10 @@ nix_q_ctx_get(struct dev *dev, uint8_t ctype, uint16_t qid, __io void **ctx_p)\n \t\telse\n \t\t\t*ctx_p = &rsp->cq;\n \t}\n-\treturn 0;\n+\trc = 0;\n+exit:\n+\tmbox_put(mbox);\n+\treturn rc;\n }\n \n static inline void\n@@ -733,14 +739,18 @@ roc_nix_queues_ctx_dump(struct roc_nix *roc_nix, FILE *file)\n \t\t}\n \n \t\t/* Dump SQB Aura minimal info */\n-\t\tnpa_aq = mbox_alloc_msg_npa_aq_enq(npa_lf->mbox);\n-\t\tif (npa_aq == NULL)\n-\t\t\treturn -ENOSPC;\n+\t\tnpa_aq = mbox_alloc_msg_npa_aq_enq(mbox_get(npa_lf->mbox));\n+\t\tif (npa_aq == NULL) {\n+\t\t\trc = -ENOSPC;\n+\t\t\tmbox_put(npa_lf->mbox);\n+\t\t\tgoto fail;\n+\t\t}\n \t\tnpa_aq->aura_id = sqb_aura;\n \t\tnpa_aq->ctype = NPA_AQ_CTYPE_AURA;\n \t\tnpa_aq->op = NPA_AQ_INSTOP_READ;\n \n \t\trc = mbox_process_msg(npa_lf->mbox, (void *)&npa_rsp);\n+\t\tmbox_put(npa_lf->mbox);\n \t\tif (rc) {\n \t\t\tplt_err(\"Failed to get sq's sqb_aura context\");\n \t\t\tcontinue;\n@@ -1103,7 +1113,7 @@ nix_tm_dump_lvl(struct nix *nix, struct nix_tm_node_list *list, uint8_t hw_lvl)\n \t\tif (!k)\n \t\t\tcontinue;\n \n-\t\treq = mbox_alloc_msg_nix_txschq_cfg(mbox);\n+\t\treq = mbox_alloc_msg_nix_txschq_cfg(mbox_get(mbox));\n \t\treq->read = 1;\n \t\treq->lvl = node->hw_lvl;\n \t\treq->num_regs = k;\n@@ -1116,6 +1126,7 @@ nix_tm_dump_lvl(struct nix *nix, struct nix_tm_node_list *list, uint8_t hw_lvl)\n \t\t} else {\n \t\t\tnix_dump(file, \"\\t!!!Failed to dump registers!!!\");\n \t\t}\n+\t\tmbox_put(mbox);\n \t}\n \n \tif (found)\n@@ -1128,7 +1139,7 @@ nix_tm_dump_lvl(struct nix *nix, struct nix_tm_node_list *list, uint8_t hw_lvl)\n \t\tif (!k)\n \t\t\treturn;\n \n-\t\treq = mbox_alloc_msg_nix_txschq_cfg(mbox);\n+\t\treq = mbox_alloc_msg_nix_txschq_cfg(mbox_get(mbox));\n \t\treq->read = 1;\n \t\treq->lvl = NIX_TXSCH_LVL_TL1;\n \t\treq->num_regs = k;\n@@ -1141,6 +1152,7 @@ nix_tm_dump_lvl(struct nix *nix, struct nix_tm_node_list *list, uint8_t hw_lvl)\n \t\t} else {\n \t\t\tnix_dump(file, \"\\t!!!Failed to dump registers!!!\");\n \t\t}\n+\t\tmbox_put(mbox);\n \t\tnix_dump(file, \"\\n\");\n \t}\n }\ndiff --git a/drivers/common/cnxk/roc_nix_fc.c b/drivers/common/cnxk/roc_nix_fc.c\nindex 033e17a4bf..569fe8dc48 100644\n--- a/drivers/common/cnxk/roc_nix_fc.c\n+++ b/drivers/common/cnxk/roc_nix_fc.c\n@@ -5,15 +5,6 @@\n #include \"roc_api.h\"\n #include \"roc_priv.h\"\n \n-static inline struct mbox *\n-get_mbox(struct roc_nix *roc_nix)\n-{\n-\tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n-\tstruct dev *dev = &nix->dev;\n-\n-\treturn dev->mbox;\n-}\n-\n static int\n nix_fc_rxchan_bpid_get(struct roc_nix *roc_nix, struct roc_nix_fc_cfg *fc_cfg)\n {\n@@ -33,7 +24,8 @@ static int\n nix_fc_rxchan_bpid_set(struct roc_nix *roc_nix, bool enable)\n {\n \tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n-\tstruct mbox *mbox = get_mbox(roc_nix);\n+\tstruct dev *dev = &nix->dev;\n+\tstruct mbox *mbox = mbox_get(dev->mbox);\n \tstruct nix_bp_cfg_req *req;\n \tstruct nix_bp_cfg_rsp *rsp;\n \tint rc = -ENOSPC, i;\n@@ -41,7 +33,7 @@ nix_fc_rxchan_bpid_set(struct roc_nix *roc_nix, bool enable)\n \tif (enable) {\n \t\treq = mbox_alloc_msg_nix_bp_enable(mbox);\n \t\tif (req == NULL)\n-\t\t\treturn rc;\n+\t\t\tgoto exit;\n \n \t\treq->chan_base = 0;\n \t\tif (roc_nix_is_lbk(roc_nix) || roc_nix_is_sdp(roc_nix))\n@@ -63,7 +55,7 @@ nix_fc_rxchan_bpid_set(struct roc_nix *roc_nix, bool enable)\n \t} else {\n \t\treq = mbox_alloc_msg_nix_bp_disable(mbox);\n \t\tif (req == NULL)\n-\t\t\treturn rc;\n+\t\t\tgoto exit;\n \t\treq->chan_base = 0;\n \t\treq->chan_cnt = nix->chan_cnt;\n \n@@ -83,7 +75,7 @@ nix_fc_rxchan_bpid_set(struct roc_nix *roc_nix, bool enable)\n \t    !roc_errata_cpt_hang_on_x2p_bp()) {\n \t\treq = mbox_alloc_msg_nix_cpt_bp_enable(mbox);\n \t\tif (req == NULL)\n-\t\t\treturn rc;\n+\t\t\tgoto exit;\n \t\treq->chan_base = 0;\n \t\treq->chan_cnt = 1;\n \t\treq->bpid_per_chan = 0;\n@@ -94,7 +86,7 @@ nix_fc_rxchan_bpid_set(struct roc_nix *roc_nix, bool enable)\n \t} else {\n \t\treq = mbox_alloc_msg_nix_cpt_bp_disable(mbox);\n \t\tif (req == NULL)\n-\t\t\treturn rc;\n+\t\t\tgoto exit;\n \t\treq->chan_base = 0;\n \t\treq->chan_cnt = 1;\n \t\treq->bpid_per_chan = 0;\n@@ -105,13 +97,16 @@ nix_fc_rxchan_bpid_set(struct roc_nix *roc_nix, bool enable)\n \t}\n \n exit:\n+\tmbox_put(mbox);\n \treturn rc;\n }\n \n static int\n nix_fc_cq_config_get(struct roc_nix *roc_nix, struct roc_nix_fc_cfg *fc_cfg)\n {\n-\tstruct mbox *mbox = get_mbox(roc_nix);\n+\tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n+\tstruct dev *dev = &nix->dev;\n+\tstruct mbox *mbox = mbox_get(dev->mbox);\n \tstruct nix_aq_enq_rsp *rsp;\n \tint rc;\n \n@@ -119,8 +114,10 @@ nix_fc_cq_config_get(struct roc_nix *roc_nix, struct roc_nix_fc_cfg *fc_cfg)\n \t\tstruct nix_aq_enq_req *aq;\n \n \t\taq = mbox_alloc_msg_nix_aq_enq(mbox);\n-\t\tif (!aq)\n-\t\t\treturn -ENOSPC;\n+\t\tif (!aq) {\n+\t\t\trc = -ENOSPC;\n+\t\t\tgoto exit;\n+\t\t}\n \n \t\taq->qidx = fc_cfg->cq_cfg.rq;\n \t\taq->ctype = NIX_AQ_CTYPE_CQ;\n@@ -129,8 +126,10 @@ nix_fc_cq_config_get(struct roc_nix *roc_nix, struct roc_nix_fc_cfg *fc_cfg)\n \t\tstruct nix_cn10k_aq_enq_req *aq;\n \n \t\taq = mbox_alloc_msg_nix_cn10k_aq_enq(mbox);\n-\t\tif (!aq)\n-\t\t\treturn -ENOSPC;\n+\t\tif (!aq) {\n+\t\t\trc = -ENOSPC;\n+\t\t\tgoto exit;\n+\t\t}\n \n \t\taq->qidx = fc_cfg->cq_cfg.rq;\n \t\taq->ctype = NIX_AQ_CTYPE_CQ;\n@@ -146,13 +145,16 @@ nix_fc_cq_config_get(struct roc_nix *roc_nix, struct roc_nix_fc_cfg *fc_cfg)\n \tfc_cfg->type = ROC_NIX_FC_CQ_CFG;\n \n exit:\n+\tmbox_put(mbox);\n \treturn rc;\n }\n \n static int\n nix_fc_rq_config_get(struct roc_nix *roc_nix, struct roc_nix_fc_cfg *fc_cfg)\n {\n-\tstruct mbox *mbox = get_mbox(roc_nix);\n+\tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n+\tstruct dev *dev = &nix->dev;\n+\tstruct mbox *mbox = mbox_get(dev->mbox);\n \tstruct nix_aq_enq_rsp *rsp;\n \tstruct npa_aq_enq_req *npa_req;\n \tstruct npa_aq_enq_rsp *npa_rsp;\n@@ -162,8 +164,10 @@ nix_fc_rq_config_get(struct roc_nix *roc_nix, struct roc_nix_fc_cfg *fc_cfg)\n \t\tstruct nix_aq_enq_req *aq;\n \n \t\taq = mbox_alloc_msg_nix_aq_enq(mbox);\n-\t\tif (!aq)\n-\t\t\treturn -ENOSPC;\n+\t\tif (!aq) {\n+\t\t\trc = -ENOSPC;\n+\t\t\tgoto exit;\n+\t\t}\n \n \t\taq->qidx = fc_cfg->rq_cfg.rq;\n \t\taq->ctype = NIX_AQ_CTYPE_RQ;\n@@ -172,8 +176,10 @@ nix_fc_rq_config_get(struct roc_nix *roc_nix, struct roc_nix_fc_cfg *fc_cfg)\n \t\tstruct nix_cn10k_aq_enq_req *aq;\n \n \t\taq = mbox_alloc_msg_nix_cn10k_aq_enq(mbox);\n-\t\tif (!aq)\n-\t\t\treturn -ENOSPC;\n+\t\tif (!aq) {\n+\t\t\trc = -ENOSPC;\n+\t\t\tgoto exit;\n+\t\t}\n \n \t\taq->qidx = fc_cfg->rq_cfg.rq;\n \t\taq->ctype = NIX_AQ_CTYPE_RQ;\n@@ -185,8 +191,10 @@ nix_fc_rq_config_get(struct roc_nix *roc_nix, struct roc_nix_fc_cfg *fc_cfg)\n \t\tgoto exit;\n \n \tnpa_req = mbox_alloc_msg_npa_aq_enq(mbox);\n-\tif (!npa_req)\n-\t\treturn -ENOSPC;\n+\tif (!npa_req) {\n+\t\trc = -ENOSPC;\n+\t\tgoto exit;\n+\t}\n \n \tnpa_req->aura_id = rsp->rq.lpb_aura;\n \tnpa_req->ctype = NPA_AQ_CTYPE_AURA;\n@@ -201,6 +209,7 @@ nix_fc_rq_config_get(struct roc_nix *roc_nix, struct roc_nix_fc_cfg *fc_cfg)\n \tfc_cfg->type = ROC_NIX_FC_RQ_CFG;\n \n exit:\n+\tmbox_put(mbox);\n \treturn rc;\n }\n \n@@ -208,14 +217,18 @@ static int\n nix_fc_cq_config_set(struct roc_nix *roc_nix, struct roc_nix_fc_cfg *fc_cfg)\n {\n \tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n-\tstruct mbox *mbox = get_mbox(roc_nix);\n+\tstruct dev *dev = &nix->dev;\n+\tstruct mbox *mbox = mbox_get(dev->mbox);\n+\tint rc;\n \n \tif (roc_model_is_cn9k()) {\n \t\tstruct nix_aq_enq_req *aq;\n \n \t\taq = mbox_alloc_msg_nix_aq_enq(mbox);\n-\t\tif (!aq)\n-\t\t\treturn -ENOSPC;\n+\t\tif (!aq) {\n+\t\t\trc = -ENOSPC;\n+\t\t\tgoto exit;\n+\t\t}\n \n \t\taq->qidx = fc_cfg->cq_cfg.rq;\n \t\taq->ctype = NIX_AQ_CTYPE_CQ;\n@@ -234,8 +247,10 @@ nix_fc_cq_config_set(struct roc_nix *roc_nix, struct roc_nix_fc_cfg *fc_cfg)\n \t\tstruct nix_cn10k_aq_enq_req *aq;\n \n \t\taq = mbox_alloc_msg_nix_cn10k_aq_enq(mbox);\n-\t\tif (!aq)\n-\t\t\treturn -ENOSPC;\n+\t\tif (!aq) {\n+\t\t\trc = -ENOSPC;\n+\t\t\tgoto exit;\n+\t\t}\n \n \t\taq->qidx = fc_cfg->cq_cfg.rq;\n \t\taq->ctype = NIX_AQ_CTYPE_CQ;\n@@ -252,7 +267,10 @@ nix_fc_cq_config_set(struct roc_nix *roc_nix, struct roc_nix_fc_cfg *fc_cfg)\n \t\taq->cq_mask.bp_ena = ~(aq->cq_mask.bp_ena);\n \t}\n \n-\treturn mbox_process(mbox);\n+\trc = mbox_process(mbox);\n+exit:\n+\tmbox_put(mbox);\n+\treturn rc;\n }\n \n static int\n@@ -323,7 +341,8 @@ enum roc_nix_fc_mode\n roc_nix_fc_mode_get(struct roc_nix *roc_nix)\n {\n \tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n-\tstruct mbox *mbox = get_mbox(roc_nix);\n+\tstruct dev *dev = &nix->dev;\n+\tstruct mbox *mbox = mbox_get(dev->mbox);\n \tstruct cgx_pause_frm_cfg *req, *rsp;\n \tenum roc_nix_fc_mode mode;\n \tint rc = -ENOSPC;\n@@ -331,18 +350,19 @@ roc_nix_fc_mode_get(struct roc_nix *roc_nix)\n \t/* Flow control on LBK link is always available */\n \tif (roc_nix_is_lbk(roc_nix)) {\n \t\tif (nix->tx_pause && nix->rx_pause)\n-\t\t\treturn ROC_NIX_FC_FULL;\n+\t\t\trc = ROC_NIX_FC_FULL;\n \t\telse if (nix->rx_pause)\n-\t\t\treturn ROC_NIX_FC_RX;\n+\t\t\trc = ROC_NIX_FC_RX;\n \t\telse if (nix->tx_pause)\n-\t\t\treturn ROC_NIX_FC_TX;\n+\t\t\trc = ROC_NIX_FC_TX;\n \t\telse\n-\t\t\treturn ROC_NIX_FC_NONE;\n+\t\t\trc = ROC_NIX_FC_NONE;\n+\t\tgoto exit;\n \t}\n \n \treq = mbox_alloc_msg_cgx_cfg_pause_frm(mbox);\n \tif (req == NULL)\n-\t\treturn rc;\n+\t\tgoto exit;\n \treq->set = 0;\n \n \trc = mbox_process_msg(mbox, (void *)&rsp);\n@@ -360,17 +380,19 @@ roc_nix_fc_mode_get(struct roc_nix *roc_nix)\n \n \tnix->rx_pause = rsp->rx_pause;\n \tnix->tx_pause = rsp->tx_pause;\n-\treturn mode;\n+\trc = mode;\n \n exit:\n-\treturn ROC_NIX_FC_NONE;\n+\tmbox_put(mbox);\n+\treturn rc;\n }\n \n int\n roc_nix_fc_mode_set(struct roc_nix *roc_nix, enum roc_nix_fc_mode mode)\n {\n \tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n-\tstruct mbox *mbox = get_mbox(roc_nix);\n+\tstruct dev *dev = &nix->dev;\n+\tstruct mbox *mbox = mbox_get(dev->mbox);\n \tstruct cgx_pause_frm_cfg *req;\n \tuint8_t tx_pause, rx_pause;\n \tint rc = -ENOSPC;\n@@ -382,12 +404,13 @@ roc_nix_fc_mode_set(struct roc_nix *roc_nix, enum roc_nix_fc_mode mode)\n \tif (roc_nix_is_lbk(roc_nix)) {\n \t\tnix->rx_pause = rx_pause;\n \t\tnix->tx_pause = tx_pause;\n-\t\treturn 0;\n+\t\trc = 0;\n+\t\tgoto exit;\n \t}\n \n \treq = mbox_alloc_msg_cgx_cfg_pause_frm(mbox);\n \tif (req == NULL)\n-\t\treturn rc;\n+\t\tgoto exit;\n \treq->set = 1;\n \treq->rx_pause = rx_pause;\n \treq->tx_pause = tx_pause;\n@@ -400,6 +423,7 @@ roc_nix_fc_mode_set(struct roc_nix *roc_nix, enum roc_nix_fc_mode mode)\n \tnix->tx_pause = tx_pause;\n \n exit:\n+\tmbox_put(mbox);\n \treturn rc;\n }\n \n@@ -421,11 +445,11 @@ roc_nix_fc_npa_bp_cfg(struct roc_nix *roc_nix, uint64_t pool_id, uint8_t ena,\n \n \tif (!lf)\n \t\treturn;\n-\tmbox = lf->mbox;\n+\tmbox = mbox_get(lf->mbox);\n \n \treq = mbox_alloc_msg_npa_aq_enq(mbox);\n \tif (req == NULL)\n-\t\treturn;\n+\t\tgoto exit;\n \n \treq->aura_id = roc_npa_aura_handle_to_aura(pool_id);\n \treq->ctype = NPA_AQ_CTYPE_AURA;\n@@ -433,7 +457,7 @@ roc_nix_fc_npa_bp_cfg(struct roc_nix *roc_nix, uint64_t pool_id, uint8_t ena,\n \n \trc = mbox_process_msg(mbox, (void *)&rsp);\n \tif (rc)\n-\t\treturn;\n+\t\tgoto exit;\n \n \tlimit = rsp->aura.limit;\n \tshift = rsp->aura.shift;\n@@ -454,7 +478,7 @@ roc_nix_fc_npa_bp_cfg(struct roc_nix *roc_nix, uint64_t pool_id, uint8_t ena,\n \t\t    !force) {\n \t\t\treq = mbox_alloc_msg_npa_aq_enq(mbox);\n \t\t\tif (req == NULL)\n-\t\t\t\treturn;\n+\t\t\t\tgoto exit;\n \n \t\t\tplt_info(\"Disabling BP/FC on aura 0x%\" PRIx64\n \t\t\t\t \" as it shared across ports or tc\",\n@@ -472,16 +496,16 @@ roc_nix_fc_npa_bp_cfg(struct roc_nix *roc_nix, uint64_t pool_id, uint8_t ena,\n \t\tif ((nix1 != nix->is_nix1) || (bpid != nix->bpid[tc]))\n \t\t\tplt_info(\"Ignoring aura 0x%\" PRIx64 \"->%u bpid mapping\",\n \t\t\t\t pool_id, nix->bpid[tc]);\n-\t\treturn;\n+\t\tgoto exit;\n \t}\n \n \t/* BP was previously enabled but now disabled skip. */\n \tif (rsp->aura.bp && ena)\n-\t\treturn;\n+\t\tgoto exit;\n \n \treq = mbox_alloc_msg_npa_aq_enq(mbox);\n \tif (req == NULL)\n-\t\treturn;\n+\t\tgoto exit;\n \n \treq->aura_id = roc_npa_aura_handle_to_aura(pool_id);\n \treq->ctype = NPA_AQ_CTYPE_AURA;\n@@ -506,20 +530,26 @@ roc_nix_fc_npa_bp_cfg(struct roc_nix *roc_nix, uint64_t pool_id, uint8_t ena,\n \treq->aura_mask.bp_ena = ~(req->aura_mask.bp_ena);\n \n \tmbox_process(mbox);\n+exit:\n+\tmbox_put(mbox);\n+\treturn;\n }\n \n int\n roc_nix_pfc_mode_set(struct roc_nix *roc_nix, struct roc_nix_pfc_cfg *pfc_cfg)\n {\n \tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n-\tstruct mbox *mbox = get_mbox(roc_nix);\n+\tstruct dev *dev = &nix->dev;\n+\tstruct mbox *mbox = mbox_get(dev->mbox);\n \tuint8_t tx_pause, rx_pause;\n \tstruct cgx_pfc_cfg *req;\n \tstruct cgx_pfc_rsp *rsp;\n \tint rc = -ENOSPC;\n \n-\tif (roc_nix_is_lbk(roc_nix))\n-\t\treturn NIX_ERR_OP_NOTSUP;\n+\tif (roc_nix_is_lbk(roc_nix)) {\n+\t\trc =  NIX_ERR_OP_NOTSUP;\n+\t\tgoto exit;\n+\t}\n \n \trx_pause = (pfc_cfg->mode == ROC_NIX_FC_FULL) ||\n \t\t   (pfc_cfg->mode == ROC_NIX_FC_RX);\n@@ -546,6 +576,7 @@ roc_nix_pfc_mode_set(struct roc_nix *roc_nix, struct roc_nix_pfc_cfg *pfc_cfg)\n \t\tnix->cev &= ~BIT(pfc_cfg->tc);\n \n exit:\n+\tmbox_put(mbox);\n \treturn rc;\n }\n \ndiff --git a/drivers/common/cnxk/roc_nix_inl.c b/drivers/common/cnxk/roc_nix_inl.c\nindex 782536db4c..70b4ae9277 100644\n--- a/drivers/common/cnxk/roc_nix_inl.c\n+++ b/drivers/common/cnxk/roc_nix_inl.c\n@@ -422,19 +422,19 @@ nix_inl_rq_mask_cfg(struct roc_nix *roc_nix, bool enable)\n \tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n \tstruct nix_rq_cpt_field_mask_cfg_req *msk_req;\n \tstruct idev_cfg *idev = idev_get_cfg();\n-\tstruct mbox *mbox = (&nix->dev)->mbox;\n+\tstruct mbox *mbox = mbox_get((&nix->dev)->mbox);\n \tstruct idev_nix_inl_cfg *inl_cfg;\n \tuint64_t aura_handle;\n \tint rc = -ENOSPC;\n \tint i;\n \n \tif (!idev)\n-\t\treturn rc;\n+\t\tgoto exit;\n \n \tinl_cfg = &idev->inl_cfg;\n \tmsk_req = mbox_alloc_msg_nix_lf_inline_rq_cfg(mbox);\n \tif (msk_req == NULL)\n-\t\treturn rc;\n+\t\tgoto exit;\n \n \tfor (i = 0; i < RQ_CTX_MASK_MAX; i++)\n \t\tmsk_req->rq_ctx_word_mask[i] = 0xFFFFFFFFFFFFFFFF;\n@@ -479,7 +479,10 @@ nix_inl_rq_mask_cfg(struct roc_nix *roc_nix, bool enable)\n \tmsk_req->ipsec_cfg1.spb_cpt_sizem1 = (inl_cfg->buf_sz >> 7) - 1;\n \tmsk_req->ipsec_cfg1.spb_cpt_enable = enable;\n \n-\treturn mbox_process(mbox);\n+\trc = mbox_process(mbox);\n+exit:\n+\tmbox_put(mbox);\n+\treturn rc;\n }\n \n bool\n@@ -853,6 +856,7 @@ roc_nix_inl_dev_rq_get(struct roc_nix_rq *rq, bool enable)\n \tstruct nix_inl_dev *inl_dev;\n \tstruct roc_nix_rq *inl_rq;\n \tuint16_t inl_rq_id;\n+\tstruct mbox *mbox;\n \tstruct dev *dev;\n \tint rc;\n \n@@ -950,20 +954,24 @@ roc_nix_inl_dev_rq_get(struct roc_nix_rq *rq, bool enable)\n \tinl_rq->sso_ena = true;\n \n \t/* Prepare and send RQ init mbox */\n+\tmbox = mbox_get(dev->mbox);\n \tif (roc_model_is_cn9k())\n \t\trc = nix_rq_cn9k_cfg(dev, inl_rq, inl_dev->qints, false, enable);\n \telse\n \t\trc = nix_rq_cfg(dev, inl_rq, inl_dev->qints, false, enable);\n \tif (rc) {\n \t\tplt_err(\"Failed to prepare aq_enq msg, rc=%d\", rc);\n+\t\tmbox_put(mbox);\n \t\treturn rc;\n \t}\n \n \trc = mbox_process(dev->mbox);\n \tif (rc) {\n \t\tplt_err(\"Failed to send aq_enq msg, rc=%d\", rc);\n+\t\tmbox_put(mbox);\n \t\treturn rc;\n \t}\n+\tmbox_put(mbox);\n \n \t/* Check meta aura */\n \tif (enable && nix->need_meta_aura) {\ndiff --git a/drivers/common/cnxk/roc_nix_inl_dev.c b/drivers/common/cnxk/roc_nix_inl_dev.c\nindex c3d94dd0da..a4a50bc423 100644\n--- a/drivers/common/cnxk/roc_nix_inl_dev.c\n+++ b/drivers/common/cnxk/roc_nix_inl_dev.c\n@@ -111,27 +111,36 @@ nix_inl_selftest(void)\n static int\n nix_inl_cpt_ctx_cache_sync(struct nix_inl_dev *inl_dev)\n {\n-\tstruct mbox *mbox = (&inl_dev->dev)->mbox;\n+\tstruct mbox *mbox = mbox_get((&inl_dev->dev)->mbox);\n \tstruct msg_req *req;\n+\tint rc;\n \n \treq = mbox_alloc_msg_cpt_ctx_cache_sync(mbox);\n-\tif (req == NULL)\n-\t\treturn -ENOSPC;\n+\tif (req == NULL) {\n+\t\trc = -ENOSPC;\n+\t\tgoto exit;\n+\t}\n \n-\treturn mbox_process(mbox);\n+\trc = mbox_process(mbox);\n+exit:\n+\tmbox_put(mbox);\n+\treturn rc;\n }\n \n static int\n nix_inl_nix_ipsec_cfg(struct nix_inl_dev *inl_dev, bool ena)\n {\n \tstruct nix_inline_ipsec_lf_cfg *lf_cfg;\n-\tstruct mbox *mbox = (&inl_dev->dev)->mbox;\n+\tstruct mbox *mbox = mbox_get((&inl_dev->dev)->mbox);\n \tuint64_t max_sa;\n \tuint32_t sa_w;\n+\tint rc;\n \n \tlf_cfg = mbox_alloc_msg_nix_inline_ipsec_lf_cfg(mbox);\n-\tif (lf_cfg == NULL)\n-\t\treturn -ENOSPC;\n+\tif (lf_cfg == NULL) {\n+\t\trc = -ENOSPC;\n+\t\tgoto exit;\n+\t}\n \n \tif (ena) {\n \n@@ -156,7 +165,10 @@ nix_inl_nix_ipsec_cfg(struct nix_inl_dev *inl_dev, bool ena)\n \t\tlf_cfg->enable = 0;\n \t}\n \n-\treturn mbox_process(mbox);\n+\trc = mbox_process(mbox);\n+exit:\n+\tmbox_put(mbox);\n+\treturn rc;\n }\n \n static int\n@@ -343,9 +355,11 @@ nix_inl_nix_setup(struct nix_inl_dev *inl_dev)\n \tmax_sa = plt_align32pow2(ipsec_in_max_spi - ipsec_in_min_spi + 1);\n \n \t/* Alloc NIX LF needed for single RQ */\n-\treq = mbox_alloc_msg_nix_lf_alloc(mbox);\n-\tif (req == NULL)\n+\treq = mbox_alloc_msg_nix_lf_alloc(mbox_get(mbox));\n+\tif (req == NULL) {\n+\t\tmbox_put(mbox);\n \t\treturn rc;\n+\t}\n \t/* We will have per-port RQ if it is not with channel masking */\n \treq->rq_cnt = inl_dev->nb_rqs;\n \treq->sq_cnt = 1;\n@@ -366,6 +380,7 @@ nix_inl_nix_setup(struct nix_inl_dev *inl_dev)\n \trc = mbox_process_msg(mbox, (void *)&rsp);\n \tif (rc) {\n \t\tplt_err(\"Failed to alloc lf, rc=%d\", rc);\n+\t\tmbox_put(mbox);\n \t\treturn rc;\n \t}\n \n@@ -373,16 +388,19 @@ nix_inl_nix_setup(struct nix_inl_dev *inl_dev)\n \tinl_dev->lf_rx_stats = rsp->lf_rx_stats;\n \tinl_dev->qints = rsp->qints;\n \tinl_dev->cints = rsp->cints;\n+\tmbox_put(mbox);\n \n \t/* Get VWQE info if supported */\n \tif (roc_model_is_cn10k()) {\n-\t\tmbox_alloc_msg_nix_get_hw_info(mbox);\n+\t\tmbox_alloc_msg_nix_get_hw_info(mbox_get(mbox));\n \t\trc = mbox_process_msg(mbox, (void *)&hw_info);\n \t\tif (rc) {\n \t\t\tplt_err(\"Failed to get HW info, rc=%d\", rc);\n+\t\t\tmbox_put(mbox);\n \t\t\tgoto lf_free;\n \t\t}\n \t\tinl_dev->vwqe_interval = hw_info->vwqe_delay;\n+\t\tmbox_put(mbox);\n \t}\n \n \t/* Register nix interrupts */\n@@ -438,8 +456,9 @@ nix_inl_nix_setup(struct nix_inl_dev *inl_dev)\n unregister_irqs:\n \tnix_inl_nix_unregister_irqs(inl_dev);\n lf_free:\n-\tmbox_alloc_msg_nix_lf_free(mbox);\n+\tmbox_alloc_msg_nix_lf_free(mbox_get(mbox));\n \trc |= mbox_process(mbox);\n+\tmbox_put(mbox);\n \treturn rc;\n }\n \n@@ -458,25 +477,33 @@ nix_inl_nix_release(struct nix_inl_dev *inl_dev)\n \t\tplt_err(\"Failed to disable Inbound IPSec, rc=%d\", rc);\n \n \t/* Sync NDC-NIX for LF */\n-\tndc_req = mbox_alloc_msg_ndc_sync_op(mbox);\n-\tif (ndc_req == NULL)\n+\tndc_req = mbox_alloc_msg_ndc_sync_op(mbox_get(mbox));\n+\tif (ndc_req == NULL) {\n+\t\tmbox_put(mbox);\n \t\treturn rc;\n+\t}\n \tndc_req->nix_lf_rx_sync = 1;\n \trc = mbox_process(mbox);\n \tif (rc)\n \t\tplt_err(\"Error on NDC-NIX-RX LF sync, rc %d\", rc);\n+\tmbox_put(mbox);\n \n \t/* Unregister IRQs */\n \tnix_inl_nix_unregister_irqs(inl_dev);\n \n \t/* By default all associated mcam rules are deleted */\n-\treq = mbox_alloc_msg_nix_lf_free(mbox);\n-\tif (req == NULL)\n+\treq = mbox_alloc_msg_nix_lf_free(mbox_get(mbox));\n+\tif (req == NULL) {\n+\t\tmbox_put(mbox);\n \t\treturn -ENOSPC;\n+\t}\n \n \trc = mbox_process(mbox);\n-\tif (rc)\n+\tif (rc) {\n+\t\tmbox_put(mbox);\n \t\treturn rc;\n+\t}\n+\tmbox_put(mbox);\n \n \tplt_free(inl_dev->rqs);\n \tplt_free(inl_dev->inb_sa_base);\n@@ -490,14 +517,14 @@ nix_inl_lf_attach(struct nix_inl_dev *inl_dev)\n {\n \tstruct msix_offset_rsp *msix_rsp;\n \tstruct dev *dev = &inl_dev->dev;\n-\tstruct mbox *mbox = dev->mbox;\n+\tstruct mbox *mbox = mbox_get(dev->mbox);\n \tstruct rsrc_attach_req *req;\n \tuint64_t nix_blkaddr;\n \tint rc = -ENOSPC;\n \n \treq = mbox_alloc_msg_attach_resources(mbox);\n \tif (req == NULL)\n-\t\treturn rc;\n+\t\tgoto exit;\n \treq->modify = true;\n \t/* Attach 1 NIXLF, SSO HWS and SSO HWGRP */\n \treq->nixlf = true;\n@@ -510,13 +537,13 @@ nix_inl_lf_attach(struct nix_inl_dev *inl_dev)\n \n \trc = mbox_process(dev->mbox);\n \tif (rc)\n-\t\treturn rc;\n+\t\tgoto exit;\n \n \t/* Get MSIX vector offsets */\n \tmbox_alloc_msg_msix_offset(mbox);\n \trc = mbox_process_msg(dev->mbox, (void **)&msix_rsp);\n \tif (rc)\n-\t\treturn rc;\n+\t\tgoto exit;\n \n \tinl_dev->nix_msixoff = msix_rsp->nix_msixoff;\n \tinl_dev->ssow_msixoff = msix_rsp->ssow_msixoff[0];\n@@ -532,27 +559,33 @@ nix_inl_lf_attach(struct nix_inl_dev *inl_dev)\n \tinl_dev->sso_base = dev->bar2 + (RVU_BLOCK_ADDR_SSO << 20);\n \tinl_dev->cpt_base = dev->bar2 + (RVU_BLOCK_ADDR_CPT0 << 20);\n \n-\treturn 0;\n+\trc = 0;\n+exit:\n+\tmbox_put(mbox);\n+\treturn rc;\n }\n \n static int\n nix_inl_lf_detach(struct nix_inl_dev *inl_dev)\n {\n \tstruct dev *dev = &inl_dev->dev;\n-\tstruct mbox *mbox = dev->mbox;\n+\tstruct mbox *mbox = mbox_get(dev->mbox);\n \tstruct rsrc_detach_req *req;\n \tint rc = -ENOSPC;\n \n \treq = mbox_alloc_msg_detach_resources(mbox);\n \tif (req == NULL)\n-\t\treturn rc;\n+\t\tgoto exit;\n \treq->partial = true;\n \treq->nixlf = true;\n \treq->ssow = true;\n \treq->sso = true;\n \treq->cptlfs = !!inl_dev->attach_cptlf;\n \n-\treturn mbox_process(dev->mbox);\n+\trc = mbox_process(dev->mbox);\n+exit:\n+\tmbox_put(mbox);\n+\treturn rc;\n }\n \n static int\ndiff --git a/drivers/common/cnxk/roc_nix_mac.c b/drivers/common/cnxk/roc_nix_mac.c\nindex 36259941c9..ac30fb52d1 100644\n--- a/drivers/common/cnxk/roc_nix_mac.c\n+++ b/drivers/common/cnxk/roc_nix_mac.c\n@@ -5,82 +5,104 @@\n #include \"roc_api.h\"\n #include \"roc_priv.h\"\n \n-static inline struct mbox *\n-nix_to_mbox(struct nix *nix)\n-{\n-\tstruct dev *dev = &nix->dev;\n-\n-\treturn dev->mbox;\n-}\n-\n int\n roc_nix_mac_rxtx_start_stop(struct roc_nix *roc_nix, bool start)\n {\n \tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n-\tstruct mbox *mbox = nix_to_mbox(nix);\n+\tstruct dev *dev = &nix->dev;\n+\tstruct mbox *mbox = mbox_get(dev->mbox);\n+\tint rc;\n \n-\tif (roc_nix_is_vf_or_sdp(roc_nix))\n-\t\treturn NIX_ERR_OP_NOTSUP;\n+\tif (roc_nix_is_vf_or_sdp(roc_nix)) {\n+\t\trc = NIX_ERR_OP_NOTSUP;\n+\t\tgoto exit;\n+\t}\n \n \tif (start)\n \t\tmbox_alloc_msg_cgx_start_rxtx(mbox);\n \telse\n \t\tmbox_alloc_msg_cgx_stop_rxtx(mbox);\n \n-\treturn mbox_process(mbox);\n+\trc = mbox_process(mbox);\n+exit:\n+\tmbox_put(mbox);\n+\treturn rc;\n }\n \n int\n roc_nix_mac_link_event_start_stop(struct roc_nix *roc_nix, bool start)\n {\n \tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n-\tstruct mbox *mbox = nix_to_mbox(nix);\n+\tstruct dev *dev = &nix->dev;\n+\tstruct mbox *mbox = mbox_get(dev->mbox);\n+\tint rc;\n \n-\tif (roc_nix_is_vf_or_sdp(roc_nix))\n-\t\treturn NIX_ERR_OP_NOTSUP;\n+\tif (roc_nix_is_vf_or_sdp(roc_nix)) {\n+\t\trc = NIX_ERR_OP_NOTSUP;\n+\t\tgoto exit;\n+\t}\n \n \tif (start)\n \t\tmbox_alloc_msg_cgx_start_linkevents(mbox);\n \telse\n \t\tmbox_alloc_msg_cgx_stop_linkevents(mbox);\n \n-\treturn mbox_process(mbox);\n+\trc = mbox_process(mbox);\n+exit:\n+\tmbox_put(mbox);\n+\treturn rc;\n }\n \n int\n roc_nix_mac_loopback_enable(struct roc_nix *roc_nix, bool enable)\n {\n \tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n-\tstruct mbox *mbox = nix_to_mbox(nix);\n+\tstruct dev *dev = &nix->dev;\n+\tstruct mbox *mbox = mbox_get(dev->mbox);\n+\tint rc;\n \n-\tif (enable && roc_nix_is_vf_or_sdp(roc_nix))\n-\t\treturn NIX_ERR_OP_NOTSUP;\n+\tif (enable && roc_nix_is_vf_or_sdp(roc_nix)) {\n+\t\trc = NIX_ERR_OP_NOTSUP;\n+\t\tgoto exit;\n+\t}\n \n \tif (enable)\n \t\tmbox_alloc_msg_cgx_intlbk_enable(mbox);\n \telse\n \t\tmbox_alloc_msg_cgx_intlbk_disable(mbox);\n \n-\treturn mbox_process(mbox);\n+\trc = mbox_process(mbox);\n+exit:\n+\tmbox_put(mbox);\n+\treturn rc;\n }\n \n int\n roc_nix_mac_addr_set(struct roc_nix *roc_nix, const uint8_t addr[])\n {\n \tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n-\tstruct mbox *mbox = nix_to_mbox(nix);\n+\tstruct dev *dev = &nix->dev;\n+\tstruct mbox *mbox = mbox_get(dev->mbox);\n \tstruct cgx_mac_addr_set_or_get *req;\n+\tint rc;\n \n-\tif (roc_nix_is_vf_or_sdp(roc_nix))\n-\t\treturn NIX_ERR_OP_NOTSUP;\n+\tif (roc_nix_is_vf_or_sdp(roc_nix)) {\n+\t\trc = NIX_ERR_OP_NOTSUP;\n+\t\tgoto exit;\n+\t}\n \n-\tif (dev_active_vfs(&nix->dev))\n-\t\treturn NIX_ERR_OP_NOTSUP;\n+\tif (dev_active_vfs(&nix->dev)) {\n+\t\trc = NIX_ERR_OP_NOTSUP;\n+\t\tgoto exit;\n+\t}\n \n \treq = mbox_alloc_msg_cgx_mac_addr_set(mbox);\n \tmbox_memcpy(req->mac_addr, addr, PLT_ETHER_ADDR_LEN);\n \n-\treturn mbox_process(mbox);\n+\trc = mbox_process(mbox);\n+exit:\n+\tmbox_put(mbox);\n+\treturn rc;\n }\n \n int\n@@ -88,79 +110,106 @@ roc_nix_mac_max_entries_get(struct roc_nix *roc_nix)\n {\n \tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n \tstruct cgx_max_dmac_entries_get_rsp *rsp;\n-\tstruct mbox *mbox = nix_to_mbox(nix);\n+\tstruct dev *dev = &nix->dev;\n+\tstruct mbox *mbox = mbox_get(dev->mbox);\n \tint rc;\n \n-\tif (roc_nix_is_vf_or_sdp(roc_nix))\n-\t\treturn NIX_ERR_OP_NOTSUP;\n+\tif (roc_nix_is_vf_or_sdp(roc_nix)) {\n+\t\trc = NIX_ERR_OP_NOTSUP;\n+\t\tgoto exit;\n+\t}\n \n \tmbox_alloc_msg_cgx_mac_max_entries_get(mbox);\n \trc = mbox_process_msg(mbox, (void *)&rsp);\n \tif (rc)\n-\t\treturn rc;\n+\t\tgoto exit;\n \n-\treturn rsp->max_dmac_filters ? rsp->max_dmac_filters : 1;\n+\trc = rsp->max_dmac_filters ? rsp->max_dmac_filters : 1;\n+exit:\n+\tmbox_put(mbox);\n+\treturn rc;\n }\n \n int\n roc_nix_mac_addr_add(struct roc_nix *roc_nix, uint8_t addr[])\n {\n \tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n-\tstruct mbox *mbox = nix_to_mbox(nix);\n \tstruct cgx_mac_addr_add_req *req;\n \tstruct cgx_mac_addr_add_rsp *rsp;\n+\tstruct dev *dev = &nix->dev;\n+\tstruct mbox *mbox = mbox_get(dev->mbox);\n \tint rc;\n \n-\tif (roc_nix_is_vf_or_sdp(roc_nix))\n-\t\treturn NIX_ERR_OP_NOTSUP;\n+\tif (roc_nix_is_vf_or_sdp(roc_nix)) {\n+\t\trc = NIX_ERR_OP_NOTSUP;\n+\t\tgoto exit;\n+\t}\n \n-\tif (dev_active_vfs(&nix->dev))\n-\t\treturn NIX_ERR_OP_NOTSUP;\n+\tif (dev_active_vfs(&nix->dev)) {\n+\t\trc = NIX_ERR_OP_NOTSUP;\n+\t\tgoto exit;\n+\t}\n \n \treq = mbox_alloc_msg_cgx_mac_addr_add(mbox);\n \tmbox_memcpy(req->mac_addr, addr, PLT_ETHER_ADDR_LEN);\n \n \trc = mbox_process_msg(mbox, (void *)&rsp);\n \tif (rc < 0)\n-\t\treturn rc;\n+\t\tgoto exit;\n \n-\treturn rsp->index;\n+\trc = rsp->index;\n+exit:\n+\tmbox_put(mbox);\n+\treturn rc;\n }\n \n int\n roc_nix_mac_addr_del(struct roc_nix *roc_nix, uint32_t index)\n {\n \tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n-\tstruct mbox *mbox = nix_to_mbox(nix);\n+\tstruct dev *dev = &nix->dev;\n+\tstruct mbox *mbox = mbox_get(dev->mbox);\n \tstruct cgx_mac_addr_del_req *req;\n \tint rc = -ENOSPC;\n \n-\tif (roc_nix_is_vf_or_sdp(roc_nix))\n-\t\treturn NIX_ERR_OP_NOTSUP;\n+\tif (roc_nix_is_vf_or_sdp(roc_nix)) {\n+\t\trc = NIX_ERR_OP_NOTSUP;\n+\t\tgoto exit;\n+\t}\n \n \treq = mbox_alloc_msg_cgx_mac_addr_del(mbox);\n \tif (req == NULL)\n-\t\treturn rc;\n+\t\tgoto exit;\n \treq->index = index;\n \n-\treturn mbox_process(mbox);\n+\trc = mbox_process(mbox);\n+exit:\n+\tmbox_put(mbox);\n+\treturn rc;\n }\n \n int\n roc_nix_mac_promisc_mode_enable(struct roc_nix *roc_nix, int enable)\n {\n \tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n-\tstruct mbox *mbox = nix_to_mbox(nix);\n+\tstruct dev *dev = &nix->dev;\n+\tstruct mbox *mbox = mbox_get(dev->mbox);\n+\tint rc;\n \n-\tif (roc_nix_is_vf_or_sdp(roc_nix))\n-\t\treturn NIX_ERR_OP_NOTSUP;\n+\tif (roc_nix_is_vf_or_sdp(roc_nix)) {\n+\t\trc = NIX_ERR_OP_NOTSUP;\n+\t\tgoto exit;\n+\t}\n \n \tif (enable)\n \t\tmbox_alloc_msg_cgx_promisc_enable(mbox);\n \telse\n \t\tmbox_alloc_msg_cgx_promisc_disable(mbox);\n \n-\treturn mbox_process(mbox);\n+\trc = mbox_process(mbox);\n+exit:\n+\tmbox_put(mbox);\n+\treturn rc;\n }\n \n int\n@@ -168,14 +217,15 @@ roc_nix_mac_link_info_get(struct roc_nix *roc_nix,\n \t\t\t  struct roc_nix_link_info *link_info)\n {\n \tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n-\tstruct mbox *mbox = nix_to_mbox(nix);\n+\tstruct dev *dev = &nix->dev;\n+\tstruct mbox *mbox = mbox_get(dev->mbox);\n \tstruct cgx_link_info_msg *rsp;\n \tint rc;\n \n \tmbox_alloc_msg_cgx_get_linkinfo(mbox);\n \trc = mbox_process_msg(mbox, (void *)&rsp);\n \tif (rc)\n-\t\treturn rc;\n+\t\tgoto exit;\n \n \tlink_info->status = rsp->link_info.link_up;\n \tlink_info->full_duplex = rsp->link_info.full_duplex;\n@@ -185,22 +235,29 @@ roc_nix_mac_link_info_get(struct roc_nix *roc_nix,\n \tlink_info->fec = rsp->link_info.fec;\n \tlink_info->port = rsp->link_info.port;\n \n-\treturn 0;\n+\trc = 0;\n+exit:\n+\tmbox_put(mbox);\n+\treturn rc;\n }\n \n int\n roc_nix_mac_link_state_set(struct roc_nix *roc_nix, uint8_t up)\n {\n \tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n-\tstruct mbox *mbox = nix_to_mbox(nix);\n+\tstruct dev *dev = &nix->dev;\n+\tstruct mbox *mbox = mbox_get(dev->mbox);\n \tstruct cgx_set_link_state_msg *req;\n \tint rc = -ENOSPC;\n \n \treq = mbox_alloc_msg_cgx_set_link_state(mbox);\n \tif (req == NULL)\n-\t\treturn rc;\n+\t\tgoto exit;\n \treq->enable = up;\n-\treturn mbox_process(mbox);\n+\trc = mbox_process(mbox);\n+exit:\n+\tmbox_put(mbox);\n+\treturn rc;\n }\n \n int\n@@ -208,29 +265,37 @@ roc_nix_mac_link_info_set(struct roc_nix *roc_nix,\n \t\t\t  struct roc_nix_link_info *link_info)\n {\n \tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n-\tstruct mbox *mbox = nix_to_mbox(nix);\n+\tstruct dev *dev = &nix->dev;\n+\tstruct mbox *mbox = mbox_get(dev->mbox);\n \tstruct cgx_set_link_mode_req *req;\n \tint rc;\n \n \trc = roc_nix_mac_link_state_set(roc_nix, link_info->status);\n \tif (rc)\n-\t\treturn rc;\n+\t\tgoto exit;\n \n \treq = mbox_alloc_msg_cgx_set_link_mode(mbox);\n-\tif (req == NULL)\n-\t\treturn -ENOSPC;\n+\tif (req == NULL) {\n+\t\trc =  -ENOSPC;\n+\t\tgoto exit;\n+\t}\n \treq->args.speed = link_info->speed;\n \treq->args.duplex = link_info->full_duplex;\n \treq->args.an = link_info->autoneg;\n \n-\treturn mbox_process(mbox);\n+\trc = mbox_process(mbox);\n+exit:\n+\tmbox_put(mbox);\n+\treturn rc;\n+\n }\n \n int\n roc_nix_mac_mtu_set(struct roc_nix *roc_nix, uint16_t mtu)\n {\n \tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n-\tstruct mbox *mbox = nix_to_mbox(nix);\n+\tstruct dev *dev = &nix->dev;\n+\tstruct mbox *mbox = mbox_get(dev->mbox);\n \tstruct nix_frs_cfg *req;\n \tbool sdp_link = false;\n \tint rc = -ENOSPC;\n@@ -240,25 +305,29 @@ roc_nix_mac_mtu_set(struct roc_nix *roc_nix, uint16_t mtu)\n \n \treq = mbox_alloc_msg_nix_set_hw_frs(mbox);\n \tif (req == NULL)\n-\t\treturn rc;\n+\t\tgoto exit;\n \treq->maxlen = mtu;\n \treq->update_smq = true;\n \treq->sdp_link = sdp_link;\n \n \trc = mbox_process(mbox);\n \tif (rc)\n-\t\treturn rc;\n+\t\tgoto exit;\n \n \t/* Save MTU for later use */\n \tnix->mtu = mtu;\n-\treturn 0;\n+\trc = 0;\n+exit:\n+\tmbox_put(mbox);\n+\treturn rc;\n }\n \n int\n roc_nix_mac_max_rx_len_set(struct roc_nix *roc_nix, uint16_t maxlen)\n {\n \tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n-\tstruct mbox *mbox = nix_to_mbox(nix);\n+\tstruct dev *dev = &nix->dev;\n+\tstruct mbox *mbox = mbox_get(dev->mbox);\n \tstruct nix_frs_cfg *req;\n \tbool sdp_link = false;\n \tint rc = -ENOSPC;\n@@ -268,11 +337,14 @@ roc_nix_mac_max_rx_len_set(struct roc_nix *roc_nix, uint16_t maxlen)\n \n \treq = mbox_alloc_msg_nix_set_hw_frs(mbox);\n \tif (req == NULL)\n-\t\treturn rc;\n+\t\tgoto exit;\n \treq->sdp_link = sdp_link;\n \treq->maxlen = maxlen;\n \n-\treturn mbox_process(mbox);\n+\trc = mbox_process(mbox);\n+exit:\n+\tmbox_put(mbox);\n+\treturn rc;\n }\n \n int\ndiff --git a/drivers/common/cnxk/roc_nix_mcast.c b/drivers/common/cnxk/roc_nix_mcast.c\nindex 87d083ebb3..3d74111274 100644\n--- a/drivers/common/cnxk/roc_nix_mcast.c\n+++ b/drivers/common/cnxk/roc_nix_mcast.c\n@@ -5,53 +5,54 @@\n #include \"roc_api.h\"\n #include \"roc_priv.h\"\n \n-static inline struct mbox *\n-get_mbox(struct roc_nix *roc_nix)\n-{\n-\tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n-\tstruct dev *dev = &nix->dev;\n-\n-\treturn dev->mbox;\n-}\n-\n int\n roc_nix_mcast_mcam_entry_alloc(struct roc_nix *roc_nix, uint16_t nb_entries,\n \t\t\t       uint8_t priority, uint16_t index[])\n {\n-\tstruct mbox *mbox = get_mbox(roc_nix);\n+\tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n+\tstruct dev *dev = &nix->dev;\n+\tstruct mbox *mbox = mbox_get(dev->mbox);\n \tstruct npc_mcam_alloc_entry_req *req;\n \tstruct npc_mcam_alloc_entry_rsp *rsp;\n \tint rc = -ENOSPC, i;\n \n \treq = mbox_alloc_msg_npc_mcam_alloc_entry(mbox);\n \tif (req == NULL)\n-\t\treturn rc;\n+\t\tgoto exit;\n \treq->priority = priority;\n \treq->count = nb_entries;\n \n \trc = mbox_process_msg(mbox, (void *)&rsp);\n \tif (rc)\n-\t\treturn rc;\n+\t\tgoto exit;\n \n \tfor (i = 0; i < rsp->count; i++)\n \t\tindex[i] = rsp->entry_list[i];\n \n-\treturn rsp->count;\n+\trc = rsp->count;\n+exit:\n+\tmbox_put(mbox);\n+\treturn rc;\n }\n \n int\n roc_nix_mcast_mcam_entry_free(struct roc_nix *roc_nix, uint32_t index)\n {\n-\tstruct mbox *mbox = get_mbox(roc_nix);\n+\tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n+\tstruct dev *dev = &nix->dev;\n+\tstruct mbox *mbox = mbox_get(dev->mbox);\n \tstruct npc_mcam_free_entry_req *req;\n \tint rc = -ENOSPC;\n \n \treq = mbox_alloc_msg_npc_mcam_free_entry(mbox);\n \tif (req == NULL)\n-\t\treturn rc;\n+\t\tgoto exit;\n \treq->entry = index;\n \n-\treturn mbox_process_msg(mbox, NULL);\n+\trc = mbox_process_msg(mbox, NULL);\n+exit:\n+\tmbox_put(mbox);\n+\treturn rc;\n }\n \n int\n@@ -59,20 +60,25 @@ roc_nix_mcast_mcam_entry_write(struct roc_nix *roc_nix,\n \t\t\t       struct mcam_entry *entry, uint32_t index,\n \t\t\t       uint8_t intf, uint64_t action)\n {\n-\tstruct mbox *mbox = get_mbox(roc_nix);\n+\tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n+\tstruct dev *dev = &nix->dev;\n+\tstruct mbox *mbox = mbox_get(dev->mbox);\n \tstruct npc_mcam_write_entry_req *req;\n \tint rc = -ENOSPC;\n \n \treq = mbox_alloc_msg_npc_mcam_write_entry(mbox);\n \tif (req == NULL)\n-\t\treturn rc;\n+\t\tgoto exit;\n \treq->entry = index;\n \treq->intf = intf;\n \treq->enable_entry = true;\n \tmbox_memcpy(&req->entry_data, entry, sizeof(struct mcam_entry));\n \treq->entry_data.action = action;\n \n-\treturn mbox_process(mbox);\n+\trc = mbox_process(mbox);\n+exit:\n+\tmbox_put(mbox);\n+\treturn rc;\n }\n \n int\n@@ -80,19 +86,24 @@ roc_nix_mcast_mcam_entry_ena_dis(struct roc_nix *roc_nix, uint32_t index,\n \t\t\t\t bool enable)\n {\n \tstruct npc_mcam_ena_dis_entry_req *req;\n-\tstruct mbox *mbox = get_mbox(roc_nix);\n+\tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n+\tstruct dev *dev = &nix->dev;\n+\tstruct mbox *mbox = mbox_get(dev->mbox);\n \tint rc = -ENOSPC;\n \n \tif (enable) {\n \t\treq = mbox_alloc_msg_npc_mcam_ena_entry(mbox);\n \t\tif (req == NULL)\n-\t\t\treturn rc;\n+\t\t\tgoto exit;\n \t} else {\n \t\treq = mbox_alloc_msg_npc_mcam_dis_entry(mbox);\n \t\tif (req == NULL)\n-\t\t\treturn rc;\n+\t\t\tgoto exit;\n \t}\n \n \treq->entry = index;\n-\treturn mbox_process(mbox);\n+\trc = mbox_process(mbox);\n+exit:\n+\tmbox_put(mbox);\n+\treturn rc;\n }\ndiff --git a/drivers/common/cnxk/roc_nix_npc.c b/drivers/common/cnxk/roc_nix_npc.c\nindex ad8839dde8..8c4a5753ee 100644\n--- a/drivers/common/cnxk/roc_nix_npc.c\n+++ b/drivers/common/cnxk/roc_nix_npc.c\n@@ -5,66 +5,76 @@\n #include \"roc_api.h\"\n #include \"roc_priv.h\"\n \n-static inline struct mbox *\n-get_mbox(struct roc_nix *roc_nix)\n-{\n-\tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n-\tstruct dev *dev = &nix->dev;\n-\n-\treturn dev->mbox;\n-}\n-\n int\n roc_nix_npc_promisc_ena_dis(struct roc_nix *roc_nix, int enable)\n {\n-\tstruct mbox *mbox = get_mbox(roc_nix);\n+\tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n+\tstruct dev *dev = &nix->dev;\n+\tstruct mbox *mbox = mbox_get(dev->mbox);\n \tstruct nix_rx_mode *req;\n \tint rc = -ENOSPC;\n \n-\tif (roc_nix_is_vf_or_sdp(roc_nix))\n-\t\treturn NIX_ERR_PARAM;\n+\tif (roc_nix_is_vf_or_sdp(roc_nix)) {\n+\t\trc = NIX_ERR_PARAM;\n+\t\tgoto exit;\n+\t}\n \n \treq = mbox_alloc_msg_nix_set_rx_mode(mbox);\n \tif (req == NULL)\n-\t\treturn rc;\n+\t\tgoto exit;\n \n \tif (enable)\n \t\treq->mode = NIX_RX_MODE_UCAST | NIX_RX_MODE_PROMISC;\n \n-\treturn mbox_process(mbox);\n+\trc = mbox_process(mbox);\n+exit:\n+\tmbox_put(mbox);\n+\treturn rc;\n }\n \n int\n roc_nix_npc_mac_addr_set(struct roc_nix *roc_nix, uint8_t addr[])\n {\n-\tstruct mbox *mbox = get_mbox(roc_nix);\n+\tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n+\tstruct dev *dev = &nix->dev;\n+\tstruct mbox *mbox = mbox_get(dev->mbox);\n \tstruct nix_set_mac_addr *req;\n+\tint rc;\n \n \treq = mbox_alloc_msg_nix_set_mac_addr(mbox);\n \tmbox_memcpy(req->mac_addr, addr, PLT_ETHER_ADDR_LEN);\n-\treturn mbox_process(mbox);\n+\trc = mbox_process(mbox);\n+\tmbox_put(mbox);\n+\treturn rc;\n }\n \n int\n roc_nix_npc_mac_addr_get(struct roc_nix *roc_nix, uint8_t *addr)\n {\n-\tstruct mbox *mbox = get_mbox(roc_nix);\n+\tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n+\tstruct dev *dev = &nix->dev;\n+\tstruct mbox *mbox = mbox_get(dev->mbox);\n \tstruct nix_get_mac_addr_rsp *rsp;\n \tint rc;\n \n \tmbox_alloc_msg_nix_get_mac_addr(mbox);\n \trc = mbox_process_msg(mbox, (void *)&rsp);\n \tif (rc)\n-\t\treturn rc;\n+\t\tgoto exit;\n \n \tmbox_memcpy(addr, rsp->mac_addr, PLT_ETHER_ADDR_LEN);\n-\treturn 0;\n+\trc = 0;\n+exit:\n+\tmbox_put(mbox);\n+\treturn rc;\n }\n \n int\n roc_nix_npc_rx_ena_dis(struct roc_nix *roc_nix, bool enable)\n {\n-\tstruct mbox *mbox = get_mbox(roc_nix);\n+\tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n+\tstruct dev *dev = &nix->dev;\n+\tstruct mbox *mbox = mbox_get(dev->mbox);\n \tint rc;\n \n \tif (enable)\n@@ -75,6 +85,8 @@ roc_nix_npc_rx_ena_dis(struct roc_nix *roc_nix, bool enable)\n \trc = mbox_process(mbox);\n \tif (!rc)\n \t\troc_nix->io_enabled = enable;\n+\n+\tmbox_put(mbox);\n \treturn rc;\n }\n \n@@ -83,21 +95,28 @@ roc_nix_npc_mcast_config(struct roc_nix *roc_nix, bool mcast_enable,\n \t\t\t bool prom_enable)\n \n {\n-\tstruct mbox *mbox = get_mbox(roc_nix);\n+\tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n+\tstruct dev *dev = &nix->dev;\n+\tstruct mbox *mbox = mbox_get(dev->mbox);\n \tstruct nix_rx_mode *req;\n \tint rc = -ENOSPC;\n \n-\tif (roc_nix_is_vf_or_sdp(roc_nix))\n-\t\treturn 0;\n+\tif (roc_nix_is_vf_or_sdp(roc_nix)) {\n+\t\trc = 0;\n+\t\tgoto exit;\n+\t}\n \n \treq = mbox_alloc_msg_nix_set_rx_mode(mbox);\n \tif (req == NULL)\n-\t\treturn rc;\n+\t\tgoto exit;\n \n \tif (mcast_enable)\n \t\treq->mode = NIX_RX_MODE_ALLMULTI;\n \tif (prom_enable)\n \t\treq->mode = NIX_RX_MODE_PROMISC;\n \n-\treturn mbox_process(mbox);\n+\trc = mbox_process(mbox);\n+exit:\n+\tmbox_put(mbox);\n+\treturn rc;\n }\ndiff --git a/drivers/common/cnxk/roc_nix_ops.c b/drivers/common/cnxk/roc_nix_ops.c\nindex 8d3cddf2a6..fc7a955fc1 100644\n--- a/drivers/common/cnxk/roc_nix_ops.c\n+++ b/drivers/common/cnxk/roc_nix_ops.c\n@@ -5,15 +5,6 @@\n #include \"roc_api.h\"\n #include \"roc_priv.h\"\n \n-static inline struct mbox *\n-get_mbox(struct roc_nix *roc_nix)\n-{\n-\tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n-\tstruct dev *dev = &nix->dev;\n-\n-\treturn dev->mbox;\n-}\n-\n static void\n nix_lso_tcp(struct nix_lso_format_cfg *req, bool v4)\n {\n@@ -172,17 +163,21 @@ int\n roc_nix_lso_custom_fmt_setup(struct roc_nix *roc_nix,\n \t\t\t     struct nix_lso_format *fields, uint16_t nb_fields)\n {\n-\tstruct mbox *mbox = get_mbox(roc_nix);\n+\tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n+\tstruct dev *dev = &nix->dev;\n+\tstruct mbox *mbox = mbox_get(dev->mbox);\n \tstruct nix_lso_format_cfg_rsp *rsp;\n \tstruct nix_lso_format_cfg *req;\n \tint rc = -ENOSPC;\n \n-\tif (nb_fields > NIX_LSO_FIELD_MAX)\n-\t\treturn -EINVAL;\n+\tif (nb_fields > NIX_LSO_FIELD_MAX) {\n+\t\trc = -EINVAL;\n+\t\tgoto exit;\n+\t}\n \n \treq = mbox_alloc_msg_nix_lso_format_cfg(mbox);\n \tif (req == NULL)\n-\t\treturn rc;\n+\t\tgoto exit;\n \n \treq->field_mask = NIX_LSO_FIELD_MASK;\n \tmbox_memcpy(req->fields, fields,\n@@ -190,17 +185,21 @@ roc_nix_lso_custom_fmt_setup(struct roc_nix *roc_nix,\n \n \trc = mbox_process_msg(mbox, (void *)&rsp);\n \tif (rc)\n-\t\treturn rc;\n+\t\tgoto exit;\n \n \tplt_nix_dbg(\"Setup custom format %u\", rsp->lso_format_idx);\n-\treturn rsp->lso_format_idx;\n+\trc = rsp->lso_format_idx;\n+exit:\n+\tmbox_put(mbox);\n+\treturn rc;\n }\n \n int\n roc_nix_lso_fmt_setup(struct roc_nix *roc_nix)\n {\n \tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n-\tstruct mbox *mbox = get_mbox(roc_nix);\n+\tstruct dev *dev = &nix->dev;\n+\tstruct mbox *mbox = mbox_get(dev->mbox);\n \tstruct nix_lso_format_cfg_rsp *rsp;\n \tstruct nix_lso_format_cfg *req;\n \tint rc = -ENOSPC;\n@@ -210,14 +209,16 @@ roc_nix_lso_fmt_setup(struct roc_nix *roc_nix)\n \t */\n \treq = mbox_alloc_msg_nix_lso_format_cfg(mbox);\n \tif (req == NULL)\n-\t\treturn rc;\n+\t\tgoto exit;\n \tnix_lso_tcp(req, true);\n \trc = mbox_process_msg(mbox, (void *)&rsp);\n \tif (rc)\n-\t\treturn rc;\n+\t\tgoto exit;\n \n-\tif (rsp->lso_format_idx != NIX_LSO_FORMAT_IDX_TSOV4)\n-\t\treturn NIX_ERR_INTERNAL;\n+\tif (rsp->lso_format_idx != NIX_LSO_FORMAT_IDX_TSOV4) {\n+\t\trc = NIX_ERR_INTERNAL;\n+\t\tgoto exit;\n+\t}\n \n \tplt_nix_dbg(\"tcpv4 lso fmt=%u\\n\", rsp->lso_format_idx);\n \n@@ -225,15 +226,19 @@ roc_nix_lso_fmt_setup(struct roc_nix *roc_nix)\n \t * IPv6/TCP LSO\n \t */\n \treq = mbox_alloc_msg_nix_lso_format_cfg(mbox);\n-\tif (req == NULL)\n-\t\treturn -ENOSPC;\n+\tif (req == NULL) {\n+\t\trc =  -ENOSPC;\n+\t\tgoto exit;\n+\t}\n \tnix_lso_tcp(req, false);\n \trc = mbox_process_msg(mbox, (void *)&rsp);\n \tif (rc)\n-\t\treturn rc;\n+\t\tgoto exit;\n \n-\tif (rsp->lso_format_idx != NIX_LSO_FORMAT_IDX_TSOV6)\n-\t\treturn NIX_ERR_INTERNAL;\n+\tif (rsp->lso_format_idx != NIX_LSO_FORMAT_IDX_TSOV6) {\n+\t\trc = NIX_ERR_INTERNAL;\n+\t\tgoto exit;\n+\t}\n \n \tplt_nix_dbg(\"tcpv6 lso fmt=%u\\n\", rsp->lso_format_idx);\n \n@@ -241,12 +246,14 @@ roc_nix_lso_fmt_setup(struct roc_nix *roc_nix)\n \t * IPv4/UDP/TUN HDR/IPv4/TCP LSO\n \t */\n \treq = mbox_alloc_msg_nix_lso_format_cfg(mbox);\n-\tif (req == NULL)\n-\t\treturn -ENOSPC;\n+\tif (req == NULL) {\n+\t\trc =  -ENOSPC;\n+\t\tgoto exit;\n+\t}\n \tnix_lso_udp_tun_tcp(req, true, true);\n \trc = mbox_process_msg(mbox, (void *)&rsp);\n \tif (rc)\n-\t\treturn rc;\n+\t\tgoto exit;\n \n \tnix->lso_udp_tun_idx[ROC_NIX_LSO_TUN_V4V4] = rsp->lso_format_idx;\n \tplt_nix_dbg(\"udp tun v4v4 fmt=%u\\n\", rsp->lso_format_idx);\n@@ -255,12 +262,14 @@ roc_nix_lso_fmt_setup(struct roc_nix *roc_nix)\n \t * IPv4/UDP/TUN HDR/IPv6/TCP LSO\n \t */\n \treq = mbox_alloc_msg_nix_lso_format_cfg(mbox);\n-\tif (req == NULL)\n-\t\treturn -ENOSPC;\n+\tif (req == NULL) {\n+\t\trc =  -ENOSPC;\n+\t\tgoto exit;\n+\t}\n \tnix_lso_udp_tun_tcp(req, true, false);\n \trc = mbox_process_msg(mbox, (void *)&rsp);\n \tif (rc)\n-\t\treturn rc;\n+\t\tgoto exit;\n \n \tnix->lso_udp_tun_idx[ROC_NIX_LSO_TUN_V4V6] = rsp->lso_format_idx;\n \tplt_nix_dbg(\"udp tun v4v6 fmt=%u\\n\", rsp->lso_format_idx);\n@@ -269,12 +278,14 @@ roc_nix_lso_fmt_setup(struct roc_nix *roc_nix)\n \t * IPv6/UDP/TUN HDR/IPv4/TCP LSO\n \t */\n \treq = mbox_alloc_msg_nix_lso_format_cfg(mbox);\n-\tif (req == NULL)\n-\t\treturn -ENOSPC;\n+\tif (req == NULL) {\n+\t\trc =  -ENOSPC;\n+\t\tgoto exit;\n+\t}\n \tnix_lso_udp_tun_tcp(req, false, true);\n \trc = mbox_process_msg(mbox, (void *)&rsp);\n \tif (rc)\n-\t\treturn rc;\n+\t\tgoto exit;\n \n \tnix->lso_udp_tun_idx[ROC_NIX_LSO_TUN_V6V4] = rsp->lso_format_idx;\n \tplt_nix_dbg(\"udp tun v6v4 fmt=%u\\n\", rsp->lso_format_idx);\n@@ -283,12 +294,14 @@ roc_nix_lso_fmt_setup(struct roc_nix *roc_nix)\n \t * IPv6/UDP/TUN HDR/IPv6/TCP LSO\n \t */\n \treq = mbox_alloc_msg_nix_lso_format_cfg(mbox);\n-\tif (req == NULL)\n-\t\treturn -ENOSPC;\n+\tif (req == NULL) {\n+\t\trc =  -ENOSPC;\n+\t\tgoto exit;\n+\t}\n \tnix_lso_udp_tun_tcp(req, false, false);\n \trc = mbox_process_msg(mbox, (void *)&rsp);\n \tif (rc)\n-\t\treturn rc;\n+\t\tgoto exit;\n \n \tnix->lso_udp_tun_idx[ROC_NIX_LSO_TUN_V6V6] = rsp->lso_format_idx;\n \tplt_nix_dbg(\"udp tun v6v6 fmt=%u\\n\", rsp->lso_format_idx);\n@@ -297,12 +310,14 @@ roc_nix_lso_fmt_setup(struct roc_nix *roc_nix)\n \t * IPv4/TUN HDR/IPv4/TCP LSO\n \t */\n \treq = mbox_alloc_msg_nix_lso_format_cfg(mbox);\n-\tif (req == NULL)\n-\t\treturn -ENOSPC;\n+\tif (req == NULL) {\n+\t\trc =  -ENOSPC;\n+\t\tgoto exit;\n+\t}\n \tnix_lso_tun_tcp(req, true, true);\n \trc = mbox_process_msg(mbox, (void *)&rsp);\n \tif (rc)\n-\t\treturn rc;\n+\t\tgoto exit;\n \n \tnix->lso_tun_idx[ROC_NIX_LSO_TUN_V4V4] = rsp->lso_format_idx;\n \tplt_nix_dbg(\"tun v4v4 fmt=%u\\n\", rsp->lso_format_idx);\n@@ -311,12 +326,14 @@ roc_nix_lso_fmt_setup(struct roc_nix *roc_nix)\n \t * IPv4/TUN HDR/IPv6/TCP LSO\n \t */\n \treq = mbox_alloc_msg_nix_lso_format_cfg(mbox);\n-\tif (req == NULL)\n-\t\treturn -ENOSPC;\n+\tif (req == NULL) {\n+\t\trc =  -ENOSPC;\n+\t\tgoto exit;\n+\t}\n \tnix_lso_tun_tcp(req, true, false);\n \trc = mbox_process_msg(mbox, (void *)&rsp);\n \tif (rc)\n-\t\treturn rc;\n+\t\tgoto exit;\n \n \tnix->lso_tun_idx[ROC_NIX_LSO_TUN_V4V6] = rsp->lso_format_idx;\n \tplt_nix_dbg(\"tun v4v6 fmt=%u\\n\", rsp->lso_format_idx);\n@@ -325,12 +342,14 @@ roc_nix_lso_fmt_setup(struct roc_nix *roc_nix)\n \t * IPv6/TUN HDR/IPv4/TCP LSO\n \t */\n \treq = mbox_alloc_msg_nix_lso_format_cfg(mbox);\n-\tif (req == NULL)\n-\t\treturn -ENOSPC;\n+\tif (req == NULL) {\n+\t\trc =  -ENOSPC;\n+\t\tgoto exit;\n+\t}\n \tnix_lso_tun_tcp(req, false, true);\n \trc = mbox_process_msg(mbox, (void *)&rsp);\n \tif (rc)\n-\t\treturn rc;\n+\t\tgoto exit;\n \n \tnix->lso_tun_idx[ROC_NIX_LSO_TUN_V6V4] = rsp->lso_format_idx;\n \tplt_nix_dbg(\"tun v6v4 fmt=%u\\n\", rsp->lso_format_idx);\n@@ -339,16 +358,22 @@ roc_nix_lso_fmt_setup(struct roc_nix *roc_nix)\n \t * IPv6/TUN HDR/IPv6/TCP LSO\n \t */\n \treq = mbox_alloc_msg_nix_lso_format_cfg(mbox);\n-\tif (req == NULL)\n-\t\treturn -ENOSPC;\n+\tif (req == NULL) {\n+\t\trc =  -ENOSPC;\n+\t\tgoto exit;\n+\t}\n+\t\tgoto exit;\n \tnix_lso_tun_tcp(req, false, false);\n \trc = mbox_process_msg(mbox, (void *)&rsp);\n \tif (rc)\n-\t\treturn rc;\n+\t\tgoto exit;\n \n \tnix->lso_tun_idx[ROC_NIX_LSO_TUN_V6V6] = rsp->lso_format_idx;\n \tplt_nix_dbg(\"tun v6v6 fmt=%u\\n\", rsp->lso_format_idx);\n-\treturn 0;\n+\trc = 0;\n+exit:\n+\tmbox_put(mbox);\n+\treturn rc;\n }\n \n int\n@@ -369,7 +394,9 @@ roc_nix_switch_hdr_set(struct roc_nix *roc_nix, uint64_t switch_header_type,\n \t\t       uint8_t pre_l2_size_offset_mask,\n \t\t       uint8_t pre_l2_size_shift_dir)\n {\n-\tstruct mbox *mbox = get_mbox(roc_nix);\n+\tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n+\tstruct dev *dev = &nix->dev;\n+\tstruct mbox *mbox = mbox_get(dev->mbox);\n \tstruct npc_set_pkind *req;\n \tstruct msg_resp *rsp;\n \tint rc = -ENOSPC;\n@@ -386,24 +413,27 @@ roc_nix_switch_hdr_set(struct roc_nix *roc_nix, uint64_t switch_header_type,\n \t    switch_header_type != ROC_PRIV_FLAGS_PRE_L2 &&\n \t    switch_header_type != ROC_PRIV_FLAGS_CUSTOM) {\n \t\tplt_err(\"switch header type is not supported\");\n-\t\treturn NIX_ERR_PARAM;\n+\t\trc = NIX_ERR_PARAM;\n+\t\tgoto exit;\n \t}\n \n \tif (switch_header_type == ROC_PRIV_FLAGS_LEN_90B &&\n \t    !roc_nix_is_sdp(roc_nix)) {\n \t\tplt_err(\"chlen90b is not supported on non-SDP device\");\n-\t\treturn NIX_ERR_PARAM;\n+\t\trc = NIX_ERR_PARAM;\n+\t\tgoto exit;\n \t}\n \n \tif (switch_header_type == ROC_PRIV_FLAGS_HIGIG &&\n \t    roc_nix_is_vf_or_sdp(roc_nix)) {\n \t\tplt_err(\"higig2 is supported on PF devices only\");\n-\t\treturn NIX_ERR_PARAM;\n+\t\trc = NIX_ERR_PARAM;\n+\t\tgoto exit;\n \t}\n \n \treq = mbox_alloc_msg_npc_set_pkind(mbox);\n \tif (req == NULL)\n-\t\treturn rc;\n+\t\tgoto exit;\n \treq->mode = switch_header_type;\n \n \tif (switch_header_type == ROC_PRIV_FLAGS_LEN_90B) {\n@@ -426,56 +456,70 @@ roc_nix_switch_hdr_set(struct roc_nix *roc_nix, uint64_t switch_header_type,\n \treq->dir = PKIND_RX;\n \trc = mbox_process_msg(mbox, (void *)&rsp);\n \tif (rc)\n-\t\treturn rc;\n+\t\tgoto exit;\n \n \treq = mbox_alloc_msg_npc_set_pkind(mbox);\n-\tif (req == NULL)\n-\t\treturn -ENOSPC;\n+\tif (req == NULL) {\n+\t\trc = -ENOSPC;\n+\t\tgoto exit;\n+\t}\n \treq->mode = switch_header_type;\n \treq->dir = PKIND_TX;\n-\treturn mbox_process_msg(mbox, (void *)&rsp);\n+\trc = mbox_process_msg(mbox, (void *)&rsp);\n+exit:\n+\tmbox_put(mbox);\n+\treturn rc;\n }\n \n int\n roc_nix_eeprom_info_get(struct roc_nix *roc_nix,\n \t\t\tstruct roc_nix_eeprom_info *info)\n {\n-\tstruct mbox *mbox = get_mbox(roc_nix);\n+\tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n+\tstruct dev *dev = &nix->dev;\n+\tstruct mbox *mbox = mbox_get(dev->mbox);\n \tstruct cgx_fw_data *rsp = NULL;\n \tint rc;\n \n \tif (!info) {\n \t\tplt_err(\"Input buffer is NULL\");\n-\t\treturn NIX_ERR_PARAM;\n+\t\trc = NIX_ERR_PARAM;\n+\t\tgoto exit;\n \t}\n \n \tmbox_alloc_msg_cgx_get_aux_link_info(mbox);\n \trc = mbox_process_msg(mbox, (void *)&rsp);\n \tif (rc) {\n \t\tplt_err(\"Failed to get fw data: %d\", rc);\n-\t\treturn rc;\n+\t\tgoto exit;\n \t}\n \n \tinfo->sff_id = rsp->fwdata.sfp_eeprom.sff_id;\n \tmbox_memcpy(info->buf, rsp->fwdata.sfp_eeprom.buf, SFP_EEPROM_SIZE);\n-\treturn 0;\n+\trc = 0;\n+exit:\n+\tmbox_put(mbox);\n+\treturn rc;\n }\n \n int\n roc_nix_rx_drop_re_set(struct roc_nix *roc_nix, bool ena)\n {\n \tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n-\tstruct mbox *mbox = get_mbox(roc_nix);\n+\tstruct dev *dev = &nix->dev;\n+\tstruct mbox *mbox = mbox_get(dev->mbox);\n \tstruct nix_rx_cfg *req;\n \tint rc = -EIO;\n \n \t/* No-op if no change */\n-\tif (ena == !!(nix->rx_cfg & ROC_NIX_LF_RX_CFG_DROP_RE))\n-\t\treturn 0;\n+\tif (ena == !!(nix->rx_cfg & ROC_NIX_LF_RX_CFG_DROP_RE)) {\n+\t\trc = 0;\n+\t\tgoto exit;\n+\t}\n \n \treq = mbox_alloc_msg_nix_set_rx_cfg(mbox);\n \tif (req == NULL)\n-\t\treturn rc;\n+\t\tgoto exit;\n \n \tif (ena)\n \t\treq->len_verify |= NIX_RX_DROP_RE;\n@@ -491,11 +535,14 @@ roc_nix_rx_drop_re_set(struct roc_nix *roc_nix, bool ena)\n \n \trc = mbox_process(mbox);\n \tif (rc)\n-\t\treturn rc;\n+\t\tgoto exit;\n \n \tif (ena)\n \t\tnix->rx_cfg |= ROC_NIX_LF_RX_CFG_DROP_RE;\n \telse\n \t\tnix->rx_cfg &= ~ROC_NIX_LF_RX_CFG_DROP_RE;\n-\treturn 0;\n+\trc = 0;\n+exit:\n+\tmbox_put(mbox);\n+\treturn rc;\n }\ndiff --git a/drivers/common/cnxk/roc_nix_ptp.c b/drivers/common/cnxk/roc_nix_ptp.c\nindex 05e4211de9..187e6c8d4f 100644\n--- a/drivers/common/cnxk/roc_nix_ptp.c\n+++ b/drivers/common/cnxk/roc_nix_ptp.c\n@@ -7,64 +7,73 @@\n \n #define PTP_FREQ_ADJUST (1 << 9)\n \n-static inline struct mbox *\n-get_mbox(struct roc_nix *roc_nix)\n-{\n-\tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n-\tstruct dev *dev = &nix->dev;\n-\n-\treturn dev->mbox;\n-}\n-\n int\n roc_nix_ptp_rx_ena_dis(struct roc_nix *roc_nix, int enable)\n {\n-\tstruct mbox *mbox = get_mbox(roc_nix);\n+\tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n+\tstruct dev *dev = &nix->dev;\n+\tstruct mbox *mbox = mbox_get(dev->mbox);\n+\tint rc;\n \n-\tif (roc_nix_is_vf_or_sdp(roc_nix) || roc_nix_is_lbk(roc_nix))\n-\t\treturn NIX_ERR_PARAM;\n+\tif (roc_nix_is_vf_or_sdp(roc_nix) || roc_nix_is_lbk(roc_nix)) {\n+\t\trc = NIX_ERR_PARAM;\n+\t\tgoto exit;\n+\t}\n \n \tif (enable)\n \t\tmbox_alloc_msg_cgx_ptp_rx_enable(mbox);\n \telse\n \t\tmbox_alloc_msg_cgx_ptp_rx_disable(mbox);\n \n-\treturn mbox_process(mbox);\n+\trc = mbox_process(mbox);\n+exit:\n+\tmbox_put(mbox);\n+\treturn rc;\n }\n \n int\n roc_nix_ptp_tx_ena_dis(struct roc_nix *roc_nix, int enable)\n {\n-\tstruct mbox *mbox = get_mbox(roc_nix);\n+\tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n+\tstruct dev *dev = &nix->dev;\n+\tstruct mbox *mbox = mbox_get(dev->mbox);\n+\tint rc;\n \n-\tif (roc_nix_is_vf_or_sdp(roc_nix) || roc_nix_is_lbk(roc_nix))\n-\t\treturn NIX_ERR_PARAM;\n+\tif (roc_nix_is_vf_or_sdp(roc_nix) || roc_nix_is_lbk(roc_nix)) {\n+\t\trc = NIX_ERR_PARAM;\n+\t\tgoto exit;\n+\t}\n \n \tif (enable)\n \t\tmbox_alloc_msg_nix_lf_ptp_tx_enable(mbox);\n \telse\n \t\tmbox_alloc_msg_nix_lf_ptp_tx_disable(mbox);\n \n-\treturn mbox_process(mbox);\n+\trc = mbox_process(mbox);\n+exit:\n+\tmbox_put(mbox);\n+\treturn rc;\n }\n \n int\n roc_nix_ptp_clock_read(struct roc_nix *roc_nix, uint64_t *clock, uint64_t *tsc,\n \t\t       uint8_t is_pmu)\n {\n-\tstruct mbox *mbox = get_mbox(roc_nix);\n+\tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n+\tstruct dev *dev = &nix->dev;\n+\tstruct mbox *mbox = mbox_get(dev->mbox);\n \tstruct ptp_req *req;\n \tstruct ptp_rsp *rsp;\n \tint rc = -ENOSPC;\n \n \treq = mbox_alloc_msg_ptp_op(mbox);\n \tif (req == NULL)\n-\t\treturn rc;\n+\t\tgoto exit;\n \treq->op = PTP_OP_GET_CLOCK;\n \treq->is_pmu = is_pmu;\n \trc = mbox_process_msg(mbox, (void *)&rsp);\n \tif (rc)\n-\t\treturn rc;\n+\t\tgoto exit;\n \n \tif (clock)\n \t\t*clock = rsp->clk;\n@@ -72,30 +81,42 @@ roc_nix_ptp_clock_read(struct roc_nix *roc_nix, uint64_t *clock, uint64_t *tsc,\n \tif (tsc)\n \t\t*tsc = rsp->tsc;\n \n-\treturn 0;\n+\trc = 0;\n+exit:\n+\tmbox_put(mbox);\n+\treturn rc;\n }\n \n int\n roc_nix_ptp_sync_time_adjust(struct roc_nix *roc_nix, int64_t delta)\n {\n-\tstruct mbox *mbox = get_mbox(roc_nix);\n+\tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n+\tstruct dev *dev = &nix->dev;\n+\tstruct mbox *mbox = mbox_get(dev->mbox);\n \tstruct ptp_req *req;\n \tstruct ptp_rsp *rsp;\n \tint rc = -ENOSPC;\n \n-\tif (roc_nix_is_vf_or_sdp(roc_nix) || roc_nix_is_lbk(roc_nix))\n-\t\treturn NIX_ERR_PARAM;\n+\tif (roc_nix_is_vf_or_sdp(roc_nix) || roc_nix_is_lbk(roc_nix)) {\n+\t\trc = NIX_ERR_PARAM;\n+\t\tgoto exit;\n+\t}\n \n-\tif ((delta <= -PTP_FREQ_ADJUST) || (delta >= PTP_FREQ_ADJUST))\n-\t\treturn NIX_ERR_INVALID_RANGE;\n+\tif ((delta <= -PTP_FREQ_ADJUST) || (delta >= PTP_FREQ_ADJUST)) {\n+\t\trc = NIX_ERR_INVALID_RANGE;\n+\t\tgoto exit;\n+\t}\n \n \treq = mbox_alloc_msg_ptp_op(mbox);\n \tif (req == NULL)\n-\t\treturn rc;\n+\t\tgoto exit;\n \treq->op = PTP_OP_ADJFINE;\n \treq->scaled_ppm = delta;\n \n-\treturn mbox_process_msg(mbox, (void *)&rsp);\n+\trc = mbox_process_msg(mbox, (void *)&rsp);\n+exit:\n+\tmbox_put(mbox);\n+\treturn rc;\n }\n \n int\ndiff --git a/drivers/common/cnxk/roc_nix_queue.c b/drivers/common/cnxk/roc_nix_queue.c\nindex 1cb1fd2101..9dbda54871 100644\n--- a/drivers/common/cnxk/roc_nix_queue.c\n+++ b/drivers/common/cnxk/roc_nix_queue.c\n@@ -47,15 +47,18 @@ nix_rq_vwqe_flush(struct roc_nix_rq *rq, uint16_t vwqe_interval)\n int\n nix_rq_ena_dis(struct dev *dev, struct roc_nix_rq *rq, bool enable)\n {\n-\tstruct mbox *mbox = dev->mbox;\n+\tstruct mbox *mbox = mbox_get(dev->mbox);\n+\tint rc;\n \n \t/* Pkts will be dropped silently if RQ is disabled */\n \tif (roc_model_is_cn9k()) {\n \t\tstruct nix_aq_enq_req *aq;\n \n \t\taq = mbox_alloc_msg_nix_aq_enq(mbox);\n-\t\tif (!aq)\n-\t\t\treturn -ENOSPC;\n+\t\tif (!aq) {\n+\t\t\trc = -ENOSPC;\n+\t\t\tgoto exit;\n+\t\t}\n \n \t\taq->qidx = rq->qid;\n \t\taq->ctype = NIX_AQ_CTYPE_RQ;\n@@ -67,8 +70,10 @@ nix_rq_ena_dis(struct dev *dev, struct roc_nix_rq *rq, bool enable)\n \t\tstruct nix_cn10k_aq_enq_req *aq;\n \n \t\taq = mbox_alloc_msg_nix_cn10k_aq_enq(mbox);\n-\t\tif (!aq)\n-\t\t\treturn -ENOSPC;\n+\t\tif (!aq) {\n+\t\t\trc = -ENOSPC;\n+\t\t\tgoto exit;\n+\t\t}\n \n \t\taq->qidx = rq->qid;\n \t\taq->ctype = NIX_AQ_CTYPE_RQ;\n@@ -78,7 +83,10 @@ nix_rq_ena_dis(struct dev *dev, struct roc_nix_rq *rq, bool enable)\n \t\taq->rq_mask.ena = ~(aq->rq_mask.ena);\n \t}\n \n-\treturn mbox_process(mbox);\n+\trc = mbox_process(mbox);\n+exit:\n+\tmbox_put(mbox);\n+\treturn rc;\n }\n \n int\n@@ -103,7 +111,7 @@ roc_nix_rq_is_sso_enable(struct roc_nix *roc_nix, uint32_t qid)\n {\n \tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n \tstruct dev *dev = &nix->dev;\n-\tstruct mbox *mbox = dev->mbox;\n+\tstruct mbox *mbox = mbox_get(dev->mbox);\n \tbool sso_enable;\n \tint rc;\n \n@@ -112,15 +120,17 @@ roc_nix_rq_is_sso_enable(struct roc_nix *roc_nix, uint32_t qid)\n \t\tstruct nix_aq_enq_req *aq;\n \n \t\taq = mbox_alloc_msg_nix_aq_enq(mbox);\n-\t\tif (!aq)\n-\t\t\treturn -ENOSPC;\n+\t\tif (!aq) {\n+\t\t\trc = -ENOSPC;\n+\t\t\tgoto exit;\n+\t\t}\n \n \t\taq->qidx = qid;\n \t\taq->ctype = NIX_AQ_CTYPE_RQ;\n \t\taq->op = NIX_AQ_INSTOP_READ;\n \t\trc = mbox_process_msg(mbox, (void *)&rsp);\n \t\tif (rc)\n-\t\t\treturn rc;\n+\t\t\tgoto exit;\n \n \t\tsso_enable = rsp->rq.sso_ena;\n \t} else {\n@@ -128,8 +138,10 @@ roc_nix_rq_is_sso_enable(struct roc_nix *roc_nix, uint32_t qid)\n \t\tstruct nix_cn10k_aq_enq_req *aq;\n \n \t\taq = mbox_alloc_msg_nix_cn10k_aq_enq(mbox);\n-\t\tif (!aq)\n-\t\t\treturn -ENOSPC;\n+\t\tif (!aq) {\n+\t\t\trc = -ENOSPC;\n+\t\t\tgoto exit;\n+\t\t}\n \n \t\taq->qidx = qid;\n \t\taq->ctype = NIX_AQ_CTYPE_RQ;\n@@ -137,12 +149,15 @@ roc_nix_rq_is_sso_enable(struct roc_nix *roc_nix, uint32_t qid)\n \n \t\trc = mbox_process_msg(mbox, (void *)&rsp);\n \t\tif (rc)\n-\t\t\treturn rc;\n+\t\t\tgoto exit;\n \n \t\tsso_enable = rsp->rq.sso_ena;\n \t}\n \n-\treturn sso_enable ? true : false;\n+\trc = sso_enable ? true : false;\n+exit:\n+\tmbox_put(mbox);\n+\treturn rc;\n }\n \n static int\n@@ -170,36 +185,45 @@ nix_rq_aura_buf_type_update(struct roc_nix_rq *rq, bool set)\n \t\tstruct nix_aq_enq_rsp *rsp;\n \t\tstruct nix_aq_enq_req *aq;\n \n-\t\taq = mbox_alloc_msg_nix_aq_enq(mbox);\n-\t\tif (!aq)\n+\t\taq = mbox_alloc_msg_nix_aq_enq(mbox_get(mbox));\n+\t\tif (!aq) {\n+\t\t\tmbox_put(mbox);\n \t\t\treturn -ENOSPC;\n+\t\t}\n \n \t\taq->qidx = rq->qid;\n \t\taq->ctype = NIX_AQ_CTYPE_RQ;\n \t\taq->op = NIX_AQ_INSTOP_READ;\n \t\trc = mbox_process_msg(mbox, (void *)&rsp);\n-\t\tif (rc)\n+\t\tif (rc) {\n+\t\t\tmbox_put(mbox);\n \t\t\treturn rc;\n+\t\t}\n \n \t\t/* Get aura handle from aura */\n \t\tlpb_aura = roc_npa_aura_handle_gen(rsp->rq.lpb_aura, aura_base);\n \t\tif (rsp->rq.spb_ena)\n \t\t\tspb_aura = roc_npa_aura_handle_gen(rsp->rq.spb_aura, aura_base);\n+\t\tmbox_put(mbox);\n \t} else {\n \t\tstruct nix_cn10k_aq_enq_rsp *rsp;\n \t\tstruct nix_cn10k_aq_enq_req *aq;\n \n-\t\taq = mbox_alloc_msg_nix_cn10k_aq_enq(mbox);\n-\t\tif (!aq)\n+\t\taq = mbox_alloc_msg_nix_cn10k_aq_enq(mbox_get(mbox));\n+\t\tif (!aq) {\n+\t\t\tmbox_put(mbox);\n \t\t\treturn -ENOSPC;\n+\t\t}\n \n \t\taq->qidx = rq->qid;\n \t\taq->ctype = NIX_AQ_CTYPE_RQ;\n \t\taq->op = NIX_AQ_INSTOP_READ;\n \n \t\trc = mbox_process_msg(mbox, (void *)&rsp);\n-\t\tif (rc)\n+\t\tif (rc) {\n+\t\t\tmbox_put(mbox);\n \t\t\treturn rc;\n+\t\t}\n \n \t\t/* Get aura handle from aura */\n \t\tlpb_aura = roc_npa_aura_handle_gen(rsp->rq.lpb_aura, aura_base);\n@@ -207,6 +231,8 @@ nix_rq_aura_buf_type_update(struct roc_nix_rq *rq, bool set)\n \t\t\tspb_aura = roc_npa_aura_handle_gen(rsp->rq.spb_aura, aura_base);\n \t\tif (rsp->rq.vwqe_ena)\n \t\t\tvwqe_aura = roc_npa_aura_handle_gen(rsp->rq.wqe_aura, aura_base);\n+\n+\t\tmbox_put(mbox);\n \t}\n \n skip_ctx_read:\n@@ -238,12 +264,15 @@ nix_rq_aura_buf_type_update(struct roc_nix_rq *rq, bool set)\n static int\n nix_rq_cn9k_cman_cfg(struct dev *dev, struct roc_nix_rq *rq)\n {\n-\tstruct mbox *mbox = dev->mbox;\n+\tstruct mbox *mbox = mbox_get(dev->mbox);\n \tstruct nix_aq_enq_req *aq;\n+\tint rc;\n \n \taq = mbox_alloc_msg_nix_aq_enq(mbox);\n-\tif (!aq)\n-\t\treturn -ENOSPC;\n+\tif (!aq) {\n+\t\trc = -ENOSPC;\n+\t\tgoto exit;\n+\t}\n \n \taq->qidx = rq->qid;\n \taq->ctype = NIX_AQ_CTYPE_RQ;\n@@ -272,7 +301,10 @@ nix_rq_cn9k_cman_cfg(struct dev *dev, struct roc_nix_rq *rq)\n \t\taq->rq_mask.xqe_pass = ~(aq->rq_mask.xqe_pass);\n \t}\n \n-\treturn mbox_process(mbox);\n+\trc = mbox_process(mbox);\n+exit:\n+\tmbox_put(mbox);\n+\treturn rc;\n }\n \n int\n@@ -573,11 +605,14 @@ static int\n nix_rq_cman_cfg(struct dev *dev, struct roc_nix_rq *rq)\n {\n \tstruct nix_cn10k_aq_enq_req *aq;\n-\tstruct mbox *mbox = dev->mbox;\n+\tstruct mbox *mbox = mbox_get(dev->mbox);\n+\tint rc;\n \n \taq = mbox_alloc_msg_nix_cn10k_aq_enq(mbox);\n-\tif (!aq)\n-\t\treturn -ENOSPC;\n+\tif (!aq) {\n+\t\trc = -ENOSPC;\n+\t\tgoto exit;\n+\t}\n \n \taq->qidx = rq->qid;\n \taq->ctype = NIX_AQ_CTYPE_RQ;\n@@ -606,23 +641,30 @@ nix_rq_cman_cfg(struct dev *dev, struct roc_nix_rq *rq)\n \t\taq->rq_mask.xqe_pass = ~(aq->rq_mask.xqe_pass);\n \t}\n \n-\treturn mbox_process(mbox);\n+\trc = mbox_process(mbox);\n+exit:\n+\tmbox_put(mbox);\n+\treturn rc;\n }\n \n int\n roc_nix_rq_init(struct roc_nix *roc_nix, struct roc_nix_rq *rq, bool ena)\n {\n \tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n-\tstruct mbox *mbox = (&nix->dev)->mbox;\n+\tstruct mbox *mbox = mbox_get((&nix->dev)->mbox);\n \tbool is_cn9k = roc_model_is_cn9k();\n \tstruct dev *dev = &nix->dev;\n \tint rc;\n \n-\tif (roc_nix == NULL || rq == NULL)\n+\tif (roc_nix == NULL || rq == NULL) {\n+\t\tmbox_put(mbox);\n \t\treturn NIX_ERR_PARAM;\n+\t}\n \n-\tif (rq->qid >= nix->nb_rx_queues)\n+\tif (rq->qid >= nix->nb_rx_queues) {\n+\t\tmbox_put(mbox);\n \t\treturn NIX_ERR_QUEUE_INVALID_RANGE;\n+\t}\n \n \trq->roc_nix = roc_nix;\n \n@@ -631,12 +673,17 @@ roc_nix_rq_init(struct roc_nix *roc_nix, struct roc_nix_rq *rq, bool ena)\n \telse\n \t\trc = nix_rq_cfg(dev, rq, nix->qints, false, ena);\n \n-\tif (rc)\n+\tif (rc) {\n+\t\tmbox_put(mbox);\n \t\treturn rc;\n+\t}\n \n \trc = mbox_process(mbox);\n-\tif (rc)\n+\tif (rc) {\n+\t\tmbox_put(mbox);\n \t\treturn rc;\n+\t}\n+\tmbox_put(mbox);\n \n \t/* Update aura buf type to indicate its use */\n \tnix_rq_aura_buf_type_update(rq, true);\n@@ -655,9 +702,10 @@ int\n roc_nix_rq_modify(struct roc_nix *roc_nix, struct roc_nix_rq *rq, bool ena)\n {\n \tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n-\tstruct mbox *mbox = (&nix->dev)->mbox;\n+\tstruct mbox *m_box = (&nix->dev)->mbox;\n \tbool is_cn9k = roc_model_is_cn9k();\n \tstruct dev *dev = &nix->dev;\n+\tstruct mbox *mbox;\n \tint rc;\n \n \tif (roc_nix == NULL || rq == NULL)\n@@ -671,17 +719,23 @@ roc_nix_rq_modify(struct roc_nix *roc_nix, struct roc_nix_rq *rq, bool ena)\n \n \trq->roc_nix = roc_nix;\n \n+\tmbox = mbox_get(m_box);\n \tif (is_cn9k)\n \t\trc = nix_rq_cn9k_cfg(dev, rq, nix->qints, true, ena);\n \telse\n \t\trc = nix_rq_cfg(dev, rq, nix->qints, true, ena);\n \n-\tif (rc)\n+\tif (rc) {\n+\t\tmbox_put(mbox);\n \t\treturn rc;\n+\t}\n \n \trc = mbox_process(mbox);\n-\tif (rc)\n+\tif (rc) {\n+\t\tmbox_put(mbox);\n \t\treturn rc;\n+\t}\n+\tmbox_put(mbox);\n \n \t/* Update aura attribute to indicate its use */\n \tnix_rq_aura_buf_type_update(rq, true);\n@@ -769,9 +823,11 @@ roc_nix_cq_init(struct roc_nix *roc_nix, struct roc_nix_cq *cq)\n \tif (roc_model_is_cn9k()) {\n \t\tstruct nix_aq_enq_req *aq;\n \n-\t\taq = mbox_alloc_msg_nix_aq_enq(mbox);\n-\t\tif (!aq)\n+\t\taq = mbox_alloc_msg_nix_aq_enq(mbox_get(mbox));\n+\t\tif (!aq) {\n+\t\t\tmbox_put(mbox);\n \t\t\treturn -ENOSPC;\n+\t\t}\n \n \t\taq->qidx = cq->qid;\n \t\taq->ctype = NIX_AQ_CTYPE_CQ;\n@@ -780,9 +836,11 @@ roc_nix_cq_init(struct roc_nix *roc_nix, struct roc_nix_cq *cq)\n \t} else {\n \t\tstruct nix_cn10k_aq_enq_req *aq;\n \n-\t\taq = mbox_alloc_msg_nix_cn10k_aq_enq(mbox);\n-\t\tif (!aq)\n+\t\taq = mbox_alloc_msg_nix_cn10k_aq_enq(mbox_get(mbox));\n+\t\tif (!aq) {\n+\t\t\tmbox_put(mbox);\n \t\t\treturn -ENOSPC;\n+\t\t}\n \n \t\taq->qidx = cq->qid;\n \t\taq->ctype = NIX_AQ_CTYPE_CQ;\n@@ -831,6 +889,7 @@ roc_nix_cq_init(struct roc_nix *roc_nix, struct roc_nix_cq *cq)\n \t}\n \n \trc = mbox_process(mbox);\n+\tmbox_put(mbox);\n \tif (rc)\n \t\tgoto free_mem;\n \n@@ -853,15 +912,17 @@ roc_nix_cq_fini(struct roc_nix_cq *cq)\n \t\treturn NIX_ERR_PARAM;\n \n \tnix = roc_nix_to_nix_priv(cq->roc_nix);\n-\tmbox = (&nix->dev)->mbox;\n+\tmbox = mbox_get((&nix->dev)->mbox);\n \n \t/* Disable CQ */\n \tif (roc_model_is_cn9k()) {\n \t\tstruct nix_aq_enq_req *aq;\n \n \t\taq = mbox_alloc_msg_nix_aq_enq(mbox);\n-\t\tif (!aq)\n+\t\tif (!aq) {\n+\t\t\tmbox_put(mbox);\n \t\t\treturn -ENOSPC;\n+\t\t}\n \n \t\taq->qidx = cq->qid;\n \t\taq->ctype = NIX_AQ_CTYPE_CQ;\n@@ -874,8 +935,10 @@ roc_nix_cq_fini(struct roc_nix_cq *cq)\n \t\tstruct nix_cn10k_aq_enq_req *aq;\n \n \t\taq = mbox_alloc_msg_nix_cn10k_aq_enq(mbox);\n-\t\tif (!aq)\n+\t\tif (!aq) {\n+\t\t\tmbox_put(mbox);\n \t\t\treturn -ENOSPC;\n+\t\t}\n \n \t\taq->qidx = cq->qid;\n \t\taq->ctype = NIX_AQ_CTYPE_CQ;\n@@ -887,9 +950,12 @@ roc_nix_cq_fini(struct roc_nix_cq *cq)\n \t}\n \n \trc = mbox_process(mbox);\n-\tif (rc)\n+\tif (rc) {\n+\t\tmbox_put(mbox);\n \t\treturn rc;\n+\t}\n \n+\tmbox_put(mbox);\n \tplt_free(cq->desc_base);\n \treturn 0;\n }\n@@ -1031,7 +1097,7 @@ sq_cn9k_init(struct nix *nix, struct roc_nix_sq *sq, uint32_t rr_quantum,\n static int\n sq_cn9k_fini(struct nix *nix, struct roc_nix_sq *sq)\n {\n-\tstruct mbox *mbox = (&nix->dev)->mbox;\n+\tstruct mbox *mbox = mbox_get((&nix->dev)->mbox);\n \tstruct nix_aq_enq_rsp *rsp;\n \tstruct nix_aq_enq_req *aq;\n \tuint16_t sqes_per_sqb;\n@@ -1039,24 +1105,32 @@ sq_cn9k_fini(struct nix *nix, struct roc_nix_sq *sq)\n \tint rc, count;\n \n \taq = mbox_alloc_msg_nix_aq_enq(mbox);\n-\tif (!aq)\n+\tif (!aq) {\n+\t\tmbox_put(mbox);\n \t\treturn -ENOSPC;\n+\t}\n \n \taq->qidx = sq->qid;\n \taq->ctype = NIX_AQ_CTYPE_SQ;\n \taq->op = NIX_AQ_INSTOP_READ;\n \trc = mbox_process_msg(mbox, (void *)&rsp);\n-\tif (rc)\n+\tif (rc) {\n+\t\tmbox_put(mbox);\n \t\treturn rc;\n+\t}\n \n \t/* Check if sq is already cleaned up */\n-\tif (!rsp->sq.ena)\n+\tif (!rsp->sq.ena) {\n+\t\tmbox_put(mbox);\n \t\treturn 0;\n+\t}\n \n \t/* Disable sq */\n \taq = mbox_alloc_msg_nix_aq_enq(mbox);\n-\tif (!aq)\n+\tif (!aq) {\n+\t\tmbox_put(mbox);\n \t\treturn -ENOSPC;\n+\t}\n \n \taq->qidx = sq->qid;\n \taq->ctype = NIX_AQ_CTYPE_SQ;\n@@ -1064,20 +1138,26 @@ sq_cn9k_fini(struct nix *nix, struct roc_nix_sq *sq)\n \taq->sq_mask.ena = ~aq->sq_mask.ena;\n \taq->sq.ena = 0;\n \trc = mbox_process(mbox);\n-\tif (rc)\n+\tif (rc) {\n+\t\tmbox_put(mbox);\n \t\treturn rc;\n+\t}\n \n \t/* Read SQ and free sqb's */\n \taq = mbox_alloc_msg_nix_aq_enq(mbox);\n-\tif (!aq)\n+\tif (!aq) {\n+\t\tmbox_put(mbox);\n \t\treturn -ENOSPC;\n+\t}\n \n \taq->qidx = sq->qid;\n \taq->ctype = NIX_AQ_CTYPE_SQ;\n \taq->op = NIX_AQ_INSTOP_READ;\n \trc = mbox_process_msg(mbox, (void *)&rsp);\n-\tif (rc)\n+\tif (rc) {\n+\t\tmbox_put(mbox);\n \t\treturn rc;\n+\t}\n \n \tif (aq->sq.smq_pend)\n \t\tplt_err(\"SQ has pending SQE's\");\n@@ -1100,6 +1180,7 @@ sq_cn9k_fini(struct nix *nix, struct roc_nix_sq *sq)\n \t/* Free next to use sqb */\n \tif (rsp->sq.next_sqb)\n \t\troc_npa_aura_op_free(sq->aura_handle, 1, rsp->sq.next_sqb);\n+\tmbox_put(mbox);\n \treturn 0;\n }\n \n@@ -1148,7 +1229,7 @@ sq_init(struct nix *nix, struct roc_nix_sq *sq, uint32_t rr_quantum,\n static int\n sq_fini(struct nix *nix, struct roc_nix_sq *sq)\n {\n-\tstruct mbox *mbox = (&nix->dev)->mbox;\n+\tstruct mbox *mbox = mbox_get((&nix->dev)->mbox);\n \tstruct nix_cn10k_aq_enq_rsp *rsp;\n \tstruct nix_cn10k_aq_enq_req *aq;\n \tuint16_t sqes_per_sqb;\n@@ -1156,24 +1237,32 @@ sq_fini(struct nix *nix, struct roc_nix_sq *sq)\n \tint rc, count;\n \n \taq = mbox_alloc_msg_nix_cn10k_aq_enq(mbox);\n-\tif (!aq)\n+\tif (!aq) {\n+\t\tmbox_put(mbox);\n \t\treturn -ENOSPC;\n+\t}\n \n \taq->qidx = sq->qid;\n \taq->ctype = NIX_AQ_CTYPE_SQ;\n \taq->op = NIX_AQ_INSTOP_READ;\n \trc = mbox_process_msg(mbox, (void *)&rsp);\n-\tif (rc)\n+\tif (rc) {\n+\t\tmbox_put(mbox);\n \t\treturn rc;\n+\t}\n \n \t/* Check if sq is already cleaned up */\n-\tif (!rsp->sq.ena)\n+\tif (!rsp->sq.ena) {\n+\t\tmbox_put(mbox);\n \t\treturn 0;\n+\t}\n \n \t/* Disable sq */\n \taq = mbox_alloc_msg_nix_cn10k_aq_enq(mbox);\n-\tif (!aq)\n+\tif (!aq) {\n+\t\tmbox_put(mbox);\n \t\treturn -ENOSPC;\n+\t}\n \n \taq->qidx = sq->qid;\n \taq->ctype = NIX_AQ_CTYPE_SQ;\n@@ -1181,20 +1270,26 @@ sq_fini(struct nix *nix, struct roc_nix_sq *sq)\n \taq->sq_mask.ena = ~aq->sq_mask.ena;\n \taq->sq.ena = 0;\n \trc = mbox_process(mbox);\n-\tif (rc)\n+\tif (rc) {\n+\t\tmbox_put(mbox);\n \t\treturn rc;\n+\t}\n \n \t/* Read SQ and free sqb's */\n \taq = mbox_alloc_msg_nix_cn10k_aq_enq(mbox);\n-\tif (!aq)\n+\tif (!aq) {\n+\t\tmbox_put(mbox);\n \t\treturn -ENOSPC;\n+\t}\n \n \taq->qidx = sq->qid;\n \taq->ctype = NIX_AQ_CTYPE_SQ;\n \taq->op = NIX_AQ_INSTOP_READ;\n \trc = mbox_process_msg(mbox, (void *)&rsp);\n-\tif (rc)\n+\tif (rc) {\n+\t\tmbox_put(mbox);\n \t\treturn rc;\n+\t}\n \n \tif (aq->sq.smq_pend)\n \t\tplt_err(\"SQ has pending SQE's\");\n@@ -1217,6 +1312,7 @@ sq_fini(struct nix *nix, struct roc_nix_sq *sq)\n \t/* Free next to use sqb */\n \tif (rsp->sq.next_sqb)\n \t\troc_npa_aura_op_free(sq->aura_handle, 1, rsp->sq.next_sqb);\n+\tmbox_put(mbox);\n \treturn 0;\n }\n \n@@ -1224,9 +1320,10 @@ int\n roc_nix_sq_init(struct roc_nix *roc_nix, struct roc_nix_sq *sq)\n {\n \tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n-\tstruct mbox *mbox = (&nix->dev)->mbox;\n+\tstruct mbox *m_box = (&nix->dev)->mbox;\n \tuint16_t qid, smq = UINT16_MAX;\n \tuint32_t rr_quantum = 0;\n+\tstruct mbox *mbox;\n \tint rc;\n \n \tif (sq == NULL)\n@@ -1257,18 +1354,25 @@ roc_nix_sq_init(struct roc_nix *roc_nix, struct roc_nix_sq *sq)\n \t\tgoto nomem;\n \t}\n \n+\tmbox = mbox_get(m_box);\n \t/* Init SQ context */\n \tif (roc_model_is_cn9k())\n \t\trc = sq_cn9k_init(nix, sq, rr_quantum, smq);\n \telse\n \t\trc = sq_init(nix, sq, rr_quantum, smq);\n \n-\tif (rc)\n+\tif (rc) {\n+\t\tmbox_put(mbox);\n \t\tgoto nomem;\n+\t}\n+\n \n \trc = mbox_process(mbox);\n-\tif (rc)\n+\tif (rc) {\n+\t\tmbox_put(mbox);\n \t\tgoto nomem;\n+\t}\n+\tmbox_put(mbox);\n \n \tnix->sqs[qid] = sq;\n \tsq->io_addr = nix->base + NIX_LF_OP_SENDX(0);\n@@ -1313,12 +1417,15 @@ roc_nix_sq_fini(struct roc_nix_sq *sq)\n \t\trc |= sq_fini(roc_nix_to_nix_priv(sq->roc_nix), sq);\n \n \t/* Sync NDC-NIX-TX for LF */\n-\tndc_req = mbox_alloc_msg_ndc_sync_op(mbox);\n-\tif (ndc_req == NULL)\n+\tndc_req = mbox_alloc_msg_ndc_sync_op(mbox_get(mbox));\n+\tif (ndc_req == NULL) {\n+\t\tmbox_put(mbox);\n \t\treturn -ENOSPC;\n+\t}\n \tndc_req->nix_lf_tx_sync = 1;\n \tif (mbox_process(mbox))\n \t\trc |= NIX_ERR_NDC_SYNC;\n+\tmbox_put(mbox);\n \n \trc |= nix_tm_sq_flush_post(sq);\n \ndiff --git a/drivers/common/cnxk/roc_nix_rss.c b/drivers/common/cnxk/roc_nix_rss.c\nindex 7de69aabeb..3599eb9bae 100644\n--- a/drivers/common/cnxk/roc_nix_rss.c\n+++ b/drivers/common/cnxk/roc_nix_rss.c\n@@ -54,7 +54,7 @@ static int\n nix_cn9k_rss_reta_set(struct nix *nix, uint8_t group,\n \t\t      uint16_t reta[ROC_NIX_RSS_RETA_MAX], uint8_t lock_rx_ctx)\n {\n-\tstruct mbox *mbox = (&nix->dev)->mbox;\n+\tstruct mbox *mbox = mbox_get((&nix->dev)->mbox);\n \tstruct nix_aq_enq_req *req;\n \tuint16_t idx;\n \tint rc;\n@@ -67,10 +67,12 @@ nix_cn9k_rss_reta_set(struct nix *nix, uint8_t group,\n \t\t\t */\n \t\t\trc = mbox_process(mbox);\n \t\t\tif (rc < 0)\n-\t\t\t\treturn rc;\n+\t\t\t\tgoto exit;\n \t\t\treq = mbox_alloc_msg_nix_aq_enq(mbox);\n-\t\t\tif (!req)\n-\t\t\t\treturn NIX_ERR_NO_MEM;\n+\t\t\tif (!req) {\n+\t\t\t\trc =  NIX_ERR_NO_MEM;\n+\t\t\t\tgoto exit;\n+\t\t\t}\n \t\t}\n \t\treq->rss.rq = reta[idx];\n \t\t/* Fill AQ info */\n@@ -88,10 +90,12 @@ nix_cn9k_rss_reta_set(struct nix *nix, uint8_t group,\n \t\t\t */\n \t\t\trc = mbox_process(mbox);\n \t\t\tif (rc < 0)\n-\t\t\t\treturn rc;\n+\t\t\t\tgoto exit;\n \t\t\treq = mbox_alloc_msg_nix_aq_enq(mbox);\n-\t\t\tif (!req)\n-\t\t\t\treturn NIX_ERR_NO_MEM;\n+\t\t\tif (!req) {\n+\t\t\t\trc =  NIX_ERR_NO_MEM;\n+\t\t\t\tgoto exit;\n+\t\t\t}\n \t\t}\n \t\treq->rss.rq = reta[idx];\n \t\t/* Fill AQ info */\n@@ -102,16 +106,19 @@ nix_cn9k_rss_reta_set(struct nix *nix, uint8_t group,\n \n \trc = mbox_process(mbox);\n \tif (rc < 0)\n-\t\treturn rc;\n+\t\tgoto exit;\n \n-\treturn 0;\n+\trc = 0;\n+exit:\n+\tmbox_put(mbox);\n+\treturn rc;\n }\n \n static int\n nix_rss_reta_set(struct nix *nix, uint8_t group,\n \t\t uint16_t reta[ROC_NIX_RSS_RETA_MAX], uint8_t lock_rx_ctx)\n {\n-\tstruct mbox *mbox = (&nix->dev)->mbox;\n+\tstruct mbox *mbox = mbox_get((&nix->dev)->mbox);\n \tstruct nix_cn10k_aq_enq_req *req;\n \tuint16_t idx;\n \tint rc;\n@@ -124,10 +131,12 @@ nix_rss_reta_set(struct nix *nix, uint8_t group,\n \t\t\t */\n \t\t\trc = mbox_process(mbox);\n \t\t\tif (rc < 0)\n-\t\t\t\treturn rc;\n+\t\t\t\tgoto exit;\n \t\t\treq = mbox_alloc_msg_nix_cn10k_aq_enq(mbox);\n-\t\t\tif (!req)\n-\t\t\t\treturn NIX_ERR_NO_MEM;\n+\t\t\tif (!req) {\n+\t\t\t\trc =  NIX_ERR_NO_MEM;\n+\t\t\t\tgoto exit;\n+\t\t\t}\n \t\t}\n \t\treq->rss.rq = reta[idx];\n \t\t/* Fill AQ info */\n@@ -145,10 +154,12 @@ nix_rss_reta_set(struct nix *nix, uint8_t group,\n \t\t\t */\n \t\t\trc = mbox_process(mbox);\n \t\t\tif (rc < 0)\n-\t\t\t\treturn rc;\n+\t\t\t\tgoto exit;\n \t\t\treq = mbox_alloc_msg_nix_cn10k_aq_enq(mbox);\n-\t\t\tif (!req)\n-\t\t\t\treturn NIX_ERR_NO_MEM;\n+\t\t\tif (!req) {\n+\t\t\t\trc =  NIX_ERR_NO_MEM;\n+\t\t\t\tgoto exit;\n+\t\t\t}\n \t\t}\n \t\treq->rss.rq = reta[idx];\n \t\t/* Fill AQ info */\n@@ -159,9 +170,12 @@ nix_rss_reta_set(struct nix *nix, uint8_t group,\n \n \trc = mbox_process(mbox);\n \tif (rc < 0)\n-\t\treturn rc;\n+\t\tgoto exit;\n \n-\treturn 0;\n+\trc = 0;\n+exit:\n+\tmbox_put(mbox);\n+\treturn rc;\n }\n \n int\n@@ -205,25 +219,29 @@ roc_nix_rss_flowkey_set(struct roc_nix *roc_nix, uint8_t *alg_idx,\n {\n \tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n \tstruct nix_rss_flowkey_cfg_rsp *rss_rsp;\n-\tstruct mbox *mbox = (&nix->dev)->mbox;\n+\tstruct mbox *mbox = mbox_get((&nix->dev)->mbox);\n \tstruct nix_rss_flowkey_cfg *cfg;\n \tint rc = -ENOSPC;\n \n-\tif (group >= ROC_NIX_RSS_GRPS)\n-\t\treturn NIX_ERR_PARAM;\n+\tif (group >= ROC_NIX_RSS_GRPS) {\n+\t\trc = NIX_ERR_PARAM;\n+\t\tgoto exit;\n+\t}\n \n \tcfg = mbox_alloc_msg_nix_rss_flowkey_cfg(mbox);\n \tif (cfg == NULL)\n-\t\treturn rc;\n+\t\tgoto exit;\n \tcfg->flowkey_cfg = flowkey;\n \tcfg->mcam_index = mcam_index; /* -1 indicates default group */\n \tcfg->group = group;\t      /* 0 is default group */\n \trc = mbox_process_msg(mbox, (void *)&rss_rsp);\n \tif (rc)\n-\t\treturn rc;\n+\t\tgoto exit;\n \tif (alg_idx)\n \t\t*alg_idx = rss_rsp->alg_idx;\n \n+exit:\n+\tmbox_put(mbox);\n \treturn rc;\n }\n \ndiff --git a/drivers/common/cnxk/roc_nix_stats.c b/drivers/common/cnxk/roc_nix_stats.c\nindex 2e5071e1bb..6b5803af84 100644\n--- a/drivers/common/cnxk/roc_nix_stats.c\n+++ b/drivers/common/cnxk/roc_nix_stats.c\n@@ -65,12 +65,18 @@ int\n roc_nix_stats_reset(struct roc_nix *roc_nix)\n {\n \tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n-\tstruct mbox *mbox = (&nix->dev)->mbox;\n+\tstruct mbox *mbox = mbox_get((&nix->dev)->mbox);\n+\tint rc;\n \n-\tif (mbox_alloc_msg_nix_stats_rst(mbox) == NULL)\n-\t\treturn -ENOMEM;\n+\tif (mbox_alloc_msg_nix_stats_rst(mbox) == NULL) {\n+\t\trc = -ENOMEM;\n+\t\tgoto exit;\n+\t}\n \n-\treturn mbox_process(mbox);\n+\trc = mbox_process(mbox);\n+exit:\n+\tmbox_put(mbox);\n+\treturn rc;\n }\n \n static int\n@@ -141,15 +147,17 @@ nix_stat_tx_queue_get(struct nix *nix, uint16_t qid,\n static int\n nix_stat_rx_queue_reset(struct nix *nix, uint16_t qid)\n {\n-\tstruct mbox *mbox = (&nix->dev)->mbox;\n+\tstruct mbox *mbox = mbox_get((&nix->dev)->mbox);\n \tint rc;\n \n \tif (roc_model_is_cn9k()) {\n \t\tstruct nix_aq_enq_req *aq;\n \n \t\taq = mbox_alloc_msg_nix_aq_enq(mbox);\n-\t\tif (!aq)\n-\t\t\treturn -ENOSPC;\n+\t\tif (!aq) {\n+\t\t\trc = -ENOSPC;\n+\t\t\tgoto exit;\n+\t\t}\n \n \t\taq->qidx = qid;\n \t\taq->ctype = NIX_AQ_CTYPE_RQ;\n@@ -170,8 +178,10 @@ nix_stat_rx_queue_reset(struct nix *nix, uint16_t qid)\n \t\tstruct nix_cn10k_aq_enq_req *aq;\n \n \t\taq = mbox_alloc_msg_nix_cn10k_aq_enq(mbox);\n-\t\tif (!aq)\n-\t\t\treturn -ENOSPC;\n+\t\tif (!aq) {\n+\t\t\trc = -ENOSPC;\n+\t\t\tgoto exit;\n+\t\t}\n \n \t\taq->qidx = qid;\n \t\taq->ctype = NIX_AQ_CTYPE_RQ;\n@@ -191,21 +201,26 @@ nix_stat_rx_queue_reset(struct nix *nix, uint16_t qid)\n \t}\n \n \trc = mbox_process(mbox);\n-\treturn rc ? NIX_ERR_AQ_WRITE_FAILED : 0;\n+\trc = rc ? NIX_ERR_AQ_WRITE_FAILED : 0;\n+exit:\n+\tmbox_put(mbox);\n+\treturn rc;\n }\n \n static int\n nix_stat_tx_queue_reset(struct nix *nix, uint16_t qid)\n {\n-\tstruct mbox *mbox = (&nix->dev)->mbox;\n+\tstruct mbox *mbox = mbox_get((&nix->dev)->mbox);\n \tint rc;\n \n \tif (roc_model_is_cn9k()) {\n \t\tstruct nix_aq_enq_req *aq;\n \n \t\taq = mbox_alloc_msg_nix_aq_enq(mbox);\n-\t\tif (!aq)\n-\t\t\treturn -ENOSPC;\n+\t\tif (!aq) {\n+\t\t\trc = -ENOSPC;\n+\t\t\tgoto exit;\n+\t\t}\n \n \t\taq->qidx = qid;\n \t\taq->ctype = NIX_AQ_CTYPE_SQ;\n@@ -223,8 +238,10 @@ nix_stat_tx_queue_reset(struct nix *nix, uint16_t qid)\n \t\tstruct nix_cn10k_aq_enq_req *aq;\n \n \t\taq = mbox_alloc_msg_nix_cn10k_aq_enq(mbox);\n-\t\tif (!aq)\n-\t\t\treturn -ENOSPC;\n+\t\tif (!aq) {\n+\t\t\trc = -ENOSPC;\n+\t\t\tgoto exit;\n+\t\t}\n \n \t\taq->qidx = qid;\n \t\taq->ctype = NIX_AQ_CTYPE_SQ;\n@@ -243,7 +260,10 @@ nix_stat_tx_queue_reset(struct nix *nix, uint16_t qid)\n \t}\n \n \trc = mbox_process(mbox);\n-\treturn rc ? NIX_ERR_AQ_WRITE_FAILED : 0;\n+\trc = rc ? NIX_ERR_AQ_WRITE_FAILED : 0;\n+exit:\n+\tmbox_put(mbox);\n+\treturn rc;\n }\n \n int\n@@ -363,15 +383,17 @@ roc_nix_xstats_get(struct roc_nix *roc_nix, struct roc_nix_xstat *xstats,\n \t\treturn count;\n \n \tif (roc_model_is_cn9k()) {\n-\t\treq = mbox_alloc_msg_cgx_stats(mbox);\n-\t\tif (!req)\n-\t\t\treturn -ENOSPC;\n+\t\treq = mbox_alloc_msg_cgx_stats(mbox_get(mbox));\n+\t\tif (!req) {\n+\t\t\trc = -ENOSPC;\n+\t\t\tgoto exit;\n+\t\t}\n \n \t\treq->hdr.pcifunc = roc_nix_get_pf_func(roc_nix);\n \n \t\trc = mbox_process_msg(mbox, (void *)&cgx_resp);\n \t\tif (rc)\n-\t\t\treturn rc;\n+\t\t\tgoto exit;\n \n \t\tfor (i = 0; i < roc_nix_num_rx_xstats(); i++) {\n \t\t\txstats[count].value =\n@@ -387,15 +409,17 @@ roc_nix_xstats_get(struct roc_nix *roc_nix, struct roc_nix_xstat *xstats,\n \t\t\tcount++;\n \t\t}\n \t} else {\n-\t\treq = mbox_alloc_msg_rpm_stats(mbox);\n-\t\tif (!req)\n-\t\t\treturn -ENOSPC;\n+\t\treq = mbox_alloc_msg_rpm_stats(mbox_get(mbox));\n+\t\tif (!req) {\n+\t\t\trc = -ENOSPC;\n+\t\t\tgoto exit;\n+\t\t}\n \n \t\treq->hdr.pcifunc = roc_nix_get_pf_func(roc_nix);\n \n \t\trc = mbox_process_msg(mbox, (void *)&rpm_resp);\n \t\tif (rc)\n-\t\t\treturn rc;\n+\t\t\tgoto exit;\n \n \t\tfor (i = 0; i < roc_nix_num_rx_xstats(); i++) {\n \t\t\txstats[count].value =\n@@ -412,7 +436,10 @@ roc_nix_xstats_get(struct roc_nix *roc_nix, struct roc_nix_xstat *xstats,\n \t\t}\n \t}\n \n-\treturn count;\n+\trc = count;\n+exit:\n+\tmbox_put(mbox);\n+\treturn rc;\n }\n \n int\ndiff --git a/drivers/common/cnxk/roc_nix_tm.c b/drivers/common/cnxk/roc_nix_tm.c\nindex be8da714cd..eecaf3e070 100644\n--- a/drivers/common/cnxk/roc_nix_tm.c\n+++ b/drivers/common/cnxk/roc_nix_tm.c\n@@ -52,13 +52,14 @@ nix_tm_node_reg_conf(struct nix *nix, struct nix_tm_node *node)\n \t/* Need this trigger to configure TL1 */\n \tif (!nix_tm_have_tl1_access(nix) && hw_lvl == NIX_TXSCH_LVL_TL2) {\n \t\t/* Prepare default conf for TL1 */\n-\t\treq = mbox_alloc_msg_nix_txschq_cfg(mbox);\n+\t\treq = mbox_alloc_msg_nix_txschq_cfg(mbox_get(mbox));\n \t\treq->lvl = NIX_TXSCH_LVL_TL1;\n \n \t\tk = nix_tm_tl1_default_prep(nix, node->parent_hw_id, req->reg,\n \t\t\t\t\t    req->regval);\n \t\treq->num_regs = k;\n \t\trc = mbox_process(mbox);\n+\t\tmbox_put(mbox);\n \t\tif (rc)\n \t\t\tgoto error;\n \t}\n@@ -76,7 +77,7 @@ nix_tm_node_reg_conf(struct nix *nix, struct nix_tm_node *node)\n \t\treturn 0;\n \n \t/* Copy and send config mbox */\n-\treq = mbox_alloc_msg_nix_txschq_cfg(mbox);\n+\treq = mbox_alloc_msg_nix_txschq_cfg(mbox_get(mbox));\n \treq->lvl = hw_lvl;\n \treq->num_regs = k;\n \n@@ -85,6 +86,7 @@ nix_tm_node_reg_conf(struct nix *nix, struct nix_tm_node *node)\n \tmbox_memcpy(req->regval_mask, regval_mask, sizeof(uint64_t) * k);\n \n \trc = mbox_process(mbox);\n+\tmbox_put(mbox);\n \tif (rc)\n \t\tgoto error;\n \n@@ -279,7 +281,7 @@ nix_tm_node_add(struct roc_nix *roc_nix, struct nix_tm_node *node)\n int\n nix_tm_clear_path_xoff(struct nix *nix, struct nix_tm_node *node)\n {\n-\tstruct mbox *mbox = (&nix->dev)->mbox;\n+\tstruct mbox *mbox = mbox_get((&nix->dev)->mbox);\n \tstruct nix_txschq_config *req;\n \tstruct nix_tm_node *p;\n \tint rc;\n@@ -298,14 +300,17 @@ nix_tm_clear_path_xoff(struct nix *nix, struct nix_tm_node *node)\n \t\t\t\t\t\t\t    req->regval);\n \t\t\trc = mbox_process(mbox);\n \t\t\tif (rc)\n-\t\t\t\treturn rc;\n+\t\t\t\tgoto exit;\n \n \t\t\tp->flags |= NIX_TM_NODE_ENABLED;\n \t\t}\n \t\tp = p->parent;\n \t}\n \n-\treturn 0;\n+\trc = 0;\n+exit:\n+\tmbox_put(mbox);\n+\treturn rc;\n }\n \n int\n@@ -395,7 +400,7 @@ nix_tm_bp_config_set(struct roc_nix *roc_nix, uint16_t sq, uint16_t tc,\n \n \t/* Allocating TL3 resources */\n \tif (!req) {\n-\t\treq = mbox_alloc_msg_nix_txschq_cfg(mbox);\n+\t\treq = mbox_alloc_msg_nix_txschq_cfg(mbox_get(mbox));\n \t\treq->lvl = nix->tm_link_cfg_lvl;\n \t\tk = 0;\n \t}\n@@ -417,10 +422,13 @@ nix_tm_bp_config_set(struct roc_nix *roc_nix, uint16_t sq, uint16_t tc,\n \tif (enable && sq_s->tc == ROC_NIX_PFC_CLASS_INVALID)\n \t\tparent->tc_refcnt++;\n \n-\treturn 0;\n+\trc = 0;\n+\tgoto exit;\n err:\n \tplt_err(\"Failed to %s bp on link %u, rc=%d(%s)\",\n \t\tenable ? \"enable\" : \"disable\", link, rc, roc_error_msg_get(rc));\n+exit:\n+\tmbox_put(mbox);\n \treturn rc;\n }\n \n@@ -430,7 +438,7 @@ nix_tm_bp_config_get(struct roc_nix *roc_nix, bool *is_enabled)\n \tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n \tstruct nix_txschq_config *req = NULL, *rsp;\n \tenum roc_nix_tm_tree tree = nix->tm_tree;\n-\tstruct mbox *mbox = (&nix->dev)->mbox;\n+\tstruct mbox *mbox = mbox_get((&nix->dev)->mbox);\n \tstruct nix_tm_node_list *list;\n \tstruct nix_tm_node *node;\n \tbool found = false;\n@@ -484,10 +492,13 @@ nix_tm_bp_config_get(struct roc_nix *roc_nix, bool *is_enabled)\n \t}\n \n \t*is_enabled = found ? !!enable : false;\n-\treturn 0;\n+\trc = 0;\n+\tgoto exit;\n err:\n \tplt_err(\"Failed to get bp status on link %u, rc=%d(%s)\", link, rc,\n \t\troc_error_msg_get(rc));\n+exit:\n+\tmbox_put(mbox);\n \treturn rc;\n }\n \n@@ -507,7 +518,7 @@ nix_tm_smq_xoff(struct nix *nix, struct nix_tm_node *node, bool enable)\n \tif (rc)\n \t\treturn rc;\n \n-\treq = mbox_alloc_msg_nix_txschq_cfg(mbox);\n+\treq = mbox_alloc_msg_nix_txschq_cfg(mbox_get(mbox));\n \treq->lvl = NIX_TXSCH_LVL_SMQ;\n \treq->num_regs = 1;\n \n@@ -516,7 +527,9 @@ nix_tm_smq_xoff(struct nix *nix, struct nix_tm_node *node, bool enable)\n \treq->regval_mask[0] =\n \t\tenable ? ~(BIT_ULL(50) | BIT_ULL(49)) : ~BIT_ULL(50);\n \n-\treturn mbox_process(mbox);\n+\trc = mbox_process(mbox);\n+\tmbox_put(mbox);\n+\treturn rc;\n }\n \n int\n@@ -645,12 +658,14 @@ nix_tm_sq_flush_pre(struct roc_nix_sq *sq)\n \t\t/* Though it enables both RX MCAM Entries and CGX Link\n \t\t * we assume all the rx queues are stopped way back.\n \t\t */\n-\t\tmbox_alloc_msg_nix_lf_start_rx(mbox);\n+\t\tmbox_alloc_msg_nix_lf_start_rx(mbox_get(mbox));\n \t\trc = mbox_process(mbox);\n \t\tif (rc) {\n+\t\t\tmbox_put(mbox);\n \t\t\tplt_err(\"cgx start failed, rc=%d\", rc);\n \t\t\treturn rc;\n \t\t}\n+\t\tmbox_put(mbox);\n \t}\n \n \t/* Disable backpressure */\n@@ -706,16 +721,20 @@ nix_tm_sq_flush_pre(struct roc_nix_sq *sq)\n \t\tgoto cleanup;\n \t}\n \n-\treq = mbox_alloc_msg_nix_rx_sw_sync(mbox);\n-\tif (!req)\n+\treq = mbox_alloc_msg_nix_rx_sw_sync(mbox_get(mbox));\n+\tif (!req) {\n+\t\tmbox_put(mbox);\n \t\treturn -ENOSPC;\n+\t}\n \n \trc = mbox_process(mbox);\n+\tmbox_put(mbox);\n cleanup:\n \t/* Restore cgx state */\n \tif (!roc_nix->io_enabled) {\n-\t\tmbox_alloc_msg_nix_lf_stop_rx(mbox);\n+\t\tmbox_alloc_msg_nix_lf_stop_rx(mbox_get(mbox));\n \t\trc |= mbox_process(mbox);\n+\t\tmbox_put(mbox);\n \t}\n \n \treturn rc;\n@@ -802,7 +821,7 @@ int\n nix_tm_sq_sched_conf(struct nix *nix, struct nix_tm_node *node,\n \t\t     bool rr_quantum_only)\n {\n-\tstruct mbox *mbox = (&nix->dev)->mbox;\n+\tstruct mbox *mbox = mbox_get((&nix->dev)->mbox);\n \tuint16_t qid = node->id, smq;\n \tuint64_t rr_quantum;\n \tint rc;\n@@ -817,15 +836,19 @@ nix_tm_sq_sched_conf(struct nix *nix, struct nix_tm_node *node,\n \t\tplt_tm_dbg(\"Enabling sq(%u)->smq(%u), rr_quantum 0x%\" PRIx64,\n \t\t\t   qid, smq, rr_quantum);\n \n-\tif (qid > nix->nb_tx_queues)\n-\t\treturn -EFAULT;\n+\tif (qid > nix->nb_tx_queues) {\n+\t\trc = -EFAULT;\n+\t\tgoto exit;\n+\t}\n \n \tif (roc_model_is_cn9k()) {\n \t\tstruct nix_aq_enq_req *aq;\n \n \t\taq = mbox_alloc_msg_nix_aq_enq(mbox);\n-\t\tif (!aq)\n-\t\t\treturn -ENOSPC;\n+\t\tif (!aq) {\n+\t\t\trc = -ENOSPC;\n+\t\t\tgoto exit;\n+\t\t}\n \n \t\taq->qidx = qid;\n \t\taq->ctype = NIX_AQ_CTYPE_SQ;\n@@ -842,8 +865,10 @@ nix_tm_sq_sched_conf(struct nix *nix, struct nix_tm_node *node,\n \t\tstruct nix_cn10k_aq_enq_req *aq;\n \n \t\taq = mbox_alloc_msg_nix_cn10k_aq_enq(mbox);\n-\t\tif (!aq)\n-\t\t\treturn -ENOSPC;\n+\t\tif (!aq) {\n+\t\t\trc = -ENOSPC;\n+\t\t\tgoto exit;\n+\t\t}\n \n \t\taq->qidx = qid;\n \t\taq->ctype = NIX_AQ_CTYPE_SQ;\n@@ -861,6 +886,8 @@ nix_tm_sq_sched_conf(struct nix *nix, struct nix_tm_node *node,\n \trc = mbox_process(mbox);\n \tif (rc)\n \t\tplt_err(\"Failed to set smq, rc=%d\", rc);\n+exit:\n+\tmbox_put(mbox);\n \treturn rc;\n }\n \n@@ -902,9 +929,11 @@ nix_tm_release_resources(struct nix *nix, uint8_t hw_lvl, bool contig,\n \t\tschq += pos;\n \n \t\t/* Free to AF */\n-\t\treq = mbox_alloc_msg_nix_txsch_free(mbox);\n-\t\tif (req == NULL)\n+\t\treq = mbox_alloc_msg_nix_txsch_free(mbox_get(mbox));\n+\t\tif (req == NULL) {\n+\t\t\tmbox_put(mbox);\n \t\t\treturn rc;\n+\t\t}\n \t\treq->flags = 0;\n \t\treq->schq_lvl = hw_lvl;\n \t\treq->schq = schq;\n@@ -912,9 +941,10 @@ nix_tm_release_resources(struct nix *nix, uint8_t hw_lvl, bool contig,\n \t\tif (rc) {\n \t\t\tplt_err(\"failed to release hwres %s(%u) rc %d\",\n \t\t\t\tnix_tm_hwlvl2str(hw_lvl), schq, rc);\n+\t\t\tmbox_put(mbox);\n \t\t\treturn rc;\n \t\t}\n-\n+\t\tmbox_put(mbox);\n \t\tplt_tm_dbg(\"Released hwres %s(%u)\", nix_tm_hwlvl2str(hw_lvl),\n \t\t\t   schq);\n \t\tplt_bitmap_clear(bmp, schq);\n@@ -932,7 +962,7 @@ nix_tm_release_resources(struct nix *nix, uint8_t hw_lvl, bool contig,\n int\n nix_tm_free_node_resource(struct nix *nix, struct nix_tm_node *node)\n {\n-\tstruct mbox *mbox = (&nix->dev)->mbox;\n+\tstruct mbox *mbox = mbox_get((&nix->dev)->mbox);\n \tstruct nix_txsch_free_req *req;\n \tstruct plt_bitmap *bmp;\n \tuint16_t avail, hw_id;\n@@ -958,13 +988,14 @@ nix_tm_free_node_resource(struct nix *nix, struct nix_tm_node *node)\n \t\tplt_bitmap_set(bmp, hw_id);\n \t\tnode->hw_id = NIX_TM_HW_ID_INVALID;\n \t\tnode->flags &= ~NIX_TM_NODE_HWRES;\n-\t\treturn 0;\n+\t\trc = 0;\n+\t\tgoto exit;\n \t}\n \n \t/* Free to AF */\n \treq = mbox_alloc_msg_nix_txsch_free(mbox);\n \tif (req == NULL)\n-\t\treturn rc;\n+\t\tgoto exit;\n \treq->flags = 0;\n \treq->schq_lvl = node->hw_lvl;\n \treq->schq = hw_id;\n@@ -972,7 +1003,7 @@ nix_tm_free_node_resource(struct nix *nix, struct nix_tm_node *node)\n \tif (rc) {\n \t\tplt_err(\"failed to release hwres %s(%u) rc %d\",\n \t\t\tnix_tm_hwlvl2str(node->hw_lvl), hw_id, rc);\n-\t\treturn rc;\n+\t\tgoto exit;\n \t}\n \n \t/* Mark parent as dirty for reallocing it's children */\n@@ -983,7 +1014,10 @@ nix_tm_free_node_resource(struct nix *nix, struct nix_tm_node *node)\n \tnode->flags &= ~NIX_TM_NODE_HWRES;\n \tplt_tm_dbg(\"Released hwres %s(%u) to af\",\n \t\t   nix_tm_hwlvl2str(node->hw_lvl), hw_id);\n-\treturn 0;\n+\trc = 0;\n+exit:\n+\tmbox_put(mbox);\n+\treturn rc;\n }\n \n int\n@@ -1280,8 +1314,9 @@ nix_tm_alloc_txschq(struct nix *nix, enum roc_nix_tm_tree tree)\n \t/* Alloc as needed */\n \tdo {\n \t\tpend = false;\n-\t\treq = mbox_alloc_msg_nix_txsch_alloc(mbox);\n+\t\treq = mbox_alloc_msg_nix_txsch_alloc(mbox_get(mbox));\n \t\tif (!req) {\n+\t\t\tmbox_put(mbox);\n \t\t\trc = -ENOMEM;\n \t\t\tgoto alloc_err;\n \t\t}\n@@ -1306,9 +1341,11 @@ nix_tm_alloc_txschq(struct nix *nix, enum roc_nix_tm_tree tree)\n \t\t}\n \n \t\trc = mbox_process_msg(mbox, (void *)&rsp);\n-\t\tif (rc)\n+\t\tif (rc) {\n+\t\t\tmbox_put(mbox);\n \t\t\tgoto alloc_err;\n-\n+\t\t}\n+\t\tmbox_put(mbox);\n \t\tnix_tm_copy_rsp_to_nix(nix, rsp);\n \t} while (pend);\n \ndiff --git a/drivers/common/cnxk/roc_nix_tm_mark.c b/drivers/common/cnxk/roc_nix_tm_mark.c\nindex d37292e8b9..e9a7604e79 100644\n--- a/drivers/common/cnxk/roc_nix_tm_mark.c\n+++ b/drivers/common/cnxk/roc_nix_tm_mark.c\n@@ -109,9 +109,11 @@ nix_tm_update_red_algo(struct nix *nix, bool red_send)\n \t\t\ttm_node->red_algo = NIX_REDALG_STD;\n \n \t\t/* Update txschq config  */\n-\t\treq = mbox_alloc_msg_nix_txschq_cfg(mbox);\n-\t\tif (req == NULL)\n+\t\treq = mbox_alloc_msg_nix_txschq_cfg(mbox_get(mbox));\n+\t\tif (req == NULL) {\n+\t\t\tmbox_put(mbox);\n \t\t\treturn -ENOSPC;\n+\t\t}\n \n \t\treq->lvl = tm_node->hw_lvl;\n \t\tk = prepare_tm_shaper_red_algo(tm_node, req->reg, req->regval,\n@@ -119,8 +121,11 @@ nix_tm_update_red_algo(struct nix *nix, bool red_send)\n \t\treq->num_regs = k;\n \n \t\trc = mbox_process(mbox);\n-\t\tif (rc)\n+\t\tif (rc) {\n+\t\t\tmbox_put(mbox);\n \t\t\treturn rc;\n+\t\t}\n+\t\tmbox_put(mbox);\n \t}\n \treturn 0;\n }\n@@ -200,19 +205,23 @@ nix_tm_update_markfmt(struct nix *nix, enum roc_nix_tm_mark type,\n int\n nix_tm_mark_init(struct nix *nix)\n {\n-\tstruct mbox *mbox = (&nix->dev)->mbox;\n+\tstruct mbox *mbox = mbox_get((&nix->dev)->mbox);\n \tstruct nix_mark_format_cfg_rsp *rsp;\n \tstruct nix_mark_format_cfg *req;\n \tint rc, i, j;\n \n \t/* Check for supported revisions */\n-\tif (roc_model_is_cn96_ax() || roc_model_is_cn95_a0())\n-\t\treturn 0;\n+\tif (roc_model_is_cn96_ax() || roc_model_is_cn95_a0()) {\n+\t\trc = 0;\n+\t\tgoto exit;\n+\t}\n \n \t/* Null mark format */\n \treq = mbox_alloc_msg_nix_mark_format_cfg(mbox);\n-\tif (req == NULL)\n-\t\treturn -ENOSPC;\n+\tif (req == NULL) {\n+\t\trc =  -ENOSPC;\n+\t\tgoto exit;\n+\t}\n \n \trc = mbox_process_msg(mbox, (void *)&rsp);\n \tif (rc) {\n@@ -268,6 +277,7 @@ nix_tm_mark_init(struct nix *nix)\n \tnix_tm_update_markfmt(nix, ROC_NIX_TM_MARK_IPV6_DSCP, 0, 0);\n \tnix_tm_update_markfmt(nix, ROC_NIX_TM_MARK_IPV6_ECN, 0, 0);\n exit:\n+\tmbox_put(mbox);\n \treturn rc;\n }\n \ndiff --git a/drivers/common/cnxk/roc_nix_tm_ops.c b/drivers/common/cnxk/roc_nix_tm_ops.c\nindex 4bf7b1e104..f31e6d02bf 100644\n--- a/drivers/common/cnxk/roc_nix_tm_ops.c\n+++ b/drivers/common/cnxk/roc_nix_tm_ops.c\n@@ -22,12 +22,12 @@ roc_nix_tm_sq_aura_fc(struct roc_nix_sq *sq, bool enable)\n \tif (!lf)\n \t\treturn NPA_ERR_DEVICE_NOT_BOUNDED;\n \n-\tmbox = lf->mbox;\n+\tmbox = mbox_get(lf->mbox);\n \t/* Set/clear sqb aura fc_ena */\n \taura_handle = sq->aura_handle;\n \treq = mbox_alloc_msg_npa_aq_enq(mbox);\n \tif (req == NULL)\n-\t\treturn rc;\n+\t\tgoto exit;\n \n \treq->aura_id = roc_npa_aura_handle_to_aura(aura_handle);\n \treq->ctype = NPA_AQ_CTYPE_AURA;\n@@ -48,12 +48,14 @@ roc_nix_tm_sq_aura_fc(struct roc_nix_sq *sq, bool enable)\n \n \trc = mbox_process(mbox);\n \tif (rc)\n-\t\treturn rc;\n+\t\tgoto exit;\n \n \t/* Read back npa aura ctx */\n \treq = mbox_alloc_msg_npa_aq_enq(mbox);\n-\tif (req == NULL)\n-\t\treturn -ENOSPC;\n+\tif (req == NULL) {\n+\t\trc = -ENOSPC;\n+\t\tgoto exit;\n+\t}\n \n \treq->aura_id = roc_npa_aura_handle_to_aura(aura_handle);\n \treq->ctype = NPA_AQ_CTYPE_AURA;\n@@ -61,7 +63,7 @@ roc_nix_tm_sq_aura_fc(struct roc_nix_sq *sq, bool enable)\n \n \trc = mbox_process_msg(mbox, (void *)&rsp);\n \tif (rc)\n-\t\treturn rc;\n+\t\tgoto exit;\n \n \t/* Init when enabled as there might be no triggers */\n \tif (enable)\n@@ -70,7 +72,10 @@ roc_nix_tm_sq_aura_fc(struct roc_nix_sq *sq, bool enable)\n \t\t*(volatile uint64_t *)sq->fc = sq->aura_sqb_bufs;\n \t/* Sync write barrier */\n \tplt_wmb();\n-\treturn 0;\n+\trc = 0;\n+exit:\n+\tmbox_put(mbox);\n+\treturn rc;\n }\n \n int\n@@ -443,12 +448,14 @@ roc_nix_tm_hierarchy_disable(struct roc_nix *roc_nix)\n \t\t/* Though it enables both RX MCAM Entries and CGX Link\n \t\t * we assume all the rx queues are stopped way back.\n \t\t */\n-\t\tmbox_alloc_msg_nix_lf_start_rx(mbox);\n+\t\tmbox_alloc_msg_nix_lf_start_rx(mbox_get(mbox));\n \t\trc = mbox_process(mbox);\n \t\tif (rc) {\n+\t\t\tmbox_put(mbox);\n \t\t\tplt_err(\"cgx start failed, rc=%d\", rc);\n \t\t\treturn rc;\n \t\t}\n+\t\tmbox_put(mbox);\n \t}\n \n \t/* XON all SMQ's */\n@@ -543,8 +550,9 @@ roc_nix_tm_hierarchy_disable(struct roc_nix *roc_nix)\n cleanup:\n \t/* Restore cgx state */\n \tif (!roc_nix->io_enabled) {\n-\t\tmbox_alloc_msg_nix_lf_stop_rx(mbox);\n+\t\tmbox_alloc_msg_nix_lf_stop_rx(mbox_get(mbox));\n \t\trc |= mbox_process(mbox);\n+\t\tmbox_put(mbox);\n \t}\n \treturn rc;\n }\n@@ -687,12 +695,13 @@ roc_nix_tm_node_suspend_resume(struct roc_nix *roc_nix, uint32_t node_id,\n \t\treturn 0;\n \n \t/* send mbox for state change */\n-\treq = mbox_alloc_msg_nix_txschq_cfg(mbox);\n+\treq = mbox_alloc_msg_nix_txschq_cfg(mbox_get(mbox));\n \n \treq->lvl = node->hw_lvl;\n \treq->num_regs =\n \t\tnix_tm_sw_xoff_prep(node, suspend, req->reg, req->regval);\n \trc = mbox_process(mbox);\n+\tmbox_put(mbox);\n \tif (!rc)\n \t\tnode->flags = flags;\n \treturn rc;\n@@ -715,30 +724,40 @@ roc_nix_tm_prealloc_res(struct roc_nix *roc_nix, uint8_t lvl,\n \n \t/* Preallocate contiguous */\n \tif (nix->contig_rsvd[hw_lvl] < contig) {\n-\t\treq = mbox_alloc_msg_nix_txsch_alloc(mbox);\n-\t\tif (req == NULL)\n+\t\treq = mbox_alloc_msg_nix_txsch_alloc(mbox_get(mbox));\n+\t\tif (req == NULL) {\n+\t\t\tmbox_put(mbox);\n \t\t\treturn rc;\n+\t\t}\n \t\treq->schq_contig[hw_lvl] = contig - nix->contig_rsvd[hw_lvl];\n \n \t\trc = mbox_process_msg(mbox, (void *)&rsp);\n-\t\tif (rc)\n+\t\tif (rc) {\n+\t\t\tmbox_put(mbox);\n \t\t\treturn rc;\n+\t\t}\n \n \t\tnix_tm_copy_rsp_to_nix(nix, rsp);\n+\t\tmbox_put(mbox);\n \t}\n \n \t/* Preallocate contiguous */\n \tif (nix->discontig_rsvd[hw_lvl] < discontig) {\n-\t\treq = mbox_alloc_msg_nix_txsch_alloc(mbox);\n-\t\tif (req == NULL)\n+\t\treq = mbox_alloc_msg_nix_txsch_alloc(mbox_get(mbox));\n+\t\tif (req == NULL) {\n+\t\t\tmbox_put(mbox);\n \t\t\treturn -ENOSPC;\n+\t\t}\n \t\treq->schq[hw_lvl] = discontig - nix->discontig_rsvd[hw_lvl];\n \n \t\trc = mbox_process_msg(mbox, (void *)&rsp);\n-\t\tif (rc)\n+\t\tif (rc) {\n+\t\t\tmbox_put(mbox);\n \t\t\treturn rc;\n+\t\t}\n \n \t\tnix_tm_copy_rsp_to_nix(nix, rsp);\n+\t\tmbox_put(mbox);\n \t}\n \n \t/* Save thresholds */\n@@ -802,17 +821,20 @@ roc_nix_tm_node_shaper_update(struct roc_nix *roc_nix, uint32_t node_id,\n \tnode->flags &= ~NIX_TM_NODE_ENABLED;\n \n \t/* Flush the specific node with SW_XOFF */\n-\treq = mbox_alloc_msg_nix_txschq_cfg(mbox);\n+\treq = mbox_alloc_msg_nix_txschq_cfg(mbox_get(mbox));\n \treq->lvl = node->hw_lvl;\n \tk = nix_tm_sw_xoff_prep(node, true, req->reg, req->regval);\n \treq->num_regs = k;\n \n \trc = mbox_process(mbox);\n-\tif (rc)\n+\tif (rc) {\n+\t\tmbox_put(mbox);\n \t\treturn rc;\n+\t}\n+\tmbox_put(mbox);\n \n \t/* Update the PIR/CIR and clear SW XOFF */\n-\treq = mbox_alloc_msg_nix_txschq_cfg(mbox);\n+\treq = mbox_alloc_msg_nix_txschq_cfg(mbox_get(mbox));\n \treq->lvl = node->hw_lvl;\n \n \tk = nix_tm_shaper_reg_prep(node, profile, req->reg, req->regval);\n@@ -821,6 +843,7 @@ roc_nix_tm_node_shaper_update(struct roc_nix *roc_nix, uint32_t node_id,\n \n \treq->num_regs = k;\n \trc = mbox_process(mbox);\n+\tmbox_put(mbox);\n \tif (!rc)\n \t\tnode->flags |= NIX_TM_NODE_ENABLED;\n \treturn rc;\n@@ -875,16 +898,17 @@ roc_nix_tm_node_parent_update(struct roc_nix *roc_nix, uint32_t node_id,\n \t\t\treturn NIX_ERR_TM_SQ_UPDATE_FAIL;\n \t} else {\n \t\t/* XOFF Parent node */\n-\t\treq = mbox_alloc_msg_nix_txschq_cfg(mbox);\n+\t\treq = mbox_alloc_msg_nix_txschq_cfg(mbox_get(mbox));\n \t\treq->lvl = node->parent->hw_lvl;\n \t\treq->num_regs = nix_tm_sw_xoff_prep(node->parent, true,\n \t\t\t\t\t\t    req->reg, req->regval);\n \t\trc = mbox_process(mbox);\n+\t\tmbox_put(mbox);\n \t\tif (rc)\n \t\t\treturn rc;\n \n \t\t/* XOFF this node and all other siblings */\n-\t\treq = mbox_alloc_msg_nix_txschq_cfg(mbox);\n+\t\treq = mbox_alloc_msg_nix_txschq_cfg(mbox_get(mbox));\n \t\treq->lvl = node->hw_lvl;\n \n \t\tk = 0;\n@@ -895,10 +919,11 @@ roc_nix_tm_node_parent_update(struct roc_nix *roc_nix, uint32_t node_id,\n \t\t\tif (k >= MAX_REGS_PER_MBOX_MSG) {\n \t\t\t\treq->num_regs = k;\n \t\t\t\trc = mbox_process(mbox);\n+\t\t\t\tmbox_put(mbox);\n \t\t\t\tif (rc)\n \t\t\t\t\treturn rc;\n \t\t\t\tk = 0;\n-\t\t\t\treq = mbox_alloc_msg_nix_txschq_cfg(mbox);\n+\t\t\t\treq = mbox_alloc_msg_nix_txschq_cfg(mbox_get(mbox));\n \t\t\t\treq->lvl = node->hw_lvl;\n \t\t\t}\n \t\t}\n@@ -906,20 +931,22 @@ roc_nix_tm_node_parent_update(struct roc_nix *roc_nix, uint32_t node_id,\n \t\tif (k) {\n \t\t\treq->num_regs = k;\n \t\t\trc = mbox_process(mbox);\n+\t\t\tmbox_put(mbox);\n \t\t\tif (rc)\n \t\t\t\treturn rc;\n \t\t\t/* Update new weight for current node */\n-\t\t\treq = mbox_alloc_msg_nix_txschq_cfg(mbox);\n+\t\t\treq = mbox_alloc_msg_nix_txschq_cfg(mbox_get(mbox));\n \t\t}\n \n \t\treq->lvl = node->hw_lvl;\n \t\treq->num_regs = nix_tm_sched_reg_prep(nix, node, req->reg, req->regval);\n \t\trc = mbox_process(mbox);\n+\t\tmbox_put(mbox);\n \t\tif (rc)\n \t\t\treturn rc;\n \n \t\t/* XON this node and all other siblings */\n-\t\treq = mbox_alloc_msg_nix_txschq_cfg(mbox);\n+\t\treq = mbox_alloc_msg_nix_txschq_cfg(mbox_get(mbox));\n \t\treq->lvl = node->hw_lvl;\n \n \t\tk = 0;\n@@ -930,10 +957,11 @@ roc_nix_tm_node_parent_update(struct roc_nix *roc_nix, uint32_t node_id,\n \t\t\tif (k >= MAX_REGS_PER_MBOX_MSG) {\n \t\t\t\treq->num_regs = k;\n \t\t\t\trc = mbox_process(mbox);\n+\t\t\t\tmbox_put(mbox);\n \t\t\t\tif (rc)\n \t\t\t\t\treturn rc;\n \t\t\t\tk = 0;\n-\t\t\t\treq = mbox_alloc_msg_nix_txschq_cfg(mbox);\n+\t\t\t\treq = mbox_alloc_msg_nix_txschq_cfg(mbox_get(mbox));\n \t\t\t\treq->lvl = node->hw_lvl;\n \t\t\t}\n \t\t}\n@@ -941,15 +969,17 @@ roc_nix_tm_node_parent_update(struct roc_nix *roc_nix, uint32_t node_id,\n \t\tif (k) {\n \t\t\treq->num_regs = k;\n \t\t\trc = mbox_process(mbox);\n+\t\t\tmbox_put(mbox);\n \t\t\tif (rc)\n \t\t\t\treturn rc;\n \t\t\t/* XON Parent node */\n-\t\t\treq = mbox_alloc_msg_nix_txschq_cfg(mbox);\n+\t\t\treq = mbox_alloc_msg_nix_txschq_cfg(mbox_get(mbox));\n \t\t}\n \n \t\treq->lvl = node->parent->hw_lvl;\n \t\treq->num_regs = nix_tm_sw_xoff_prep(node->parent, false, req->reg, req->regval);\n \t\trc = mbox_process(mbox);\n+\t\tmbox_put(mbox);\n \t\tif (rc)\n \t\t\treturn rc;\n \t}\n@@ -1001,20 +1031,22 @@ roc_nix_tm_rlimit_sq(struct roc_nix *roc_nix, uint16_t qid, uint64_t rate)\n \tint rc;\n \n \tif ((nix->tm_tree == ROC_NIX_TM_USER) ||\n-\t    !(nix->tm_flags & NIX_TM_HIERARCHY_ENA))\n+\t    !(nix->tm_flags & NIX_TM_HIERARCHY_ENA)) {\n \t\treturn NIX_ERR_TM_INVALID_TREE;\n+\t}\n \n \tnode = nix_tm_node_search(nix, qid, nix->tm_tree);\n \n \t/* check if we found a valid leaf node */\n \tif (!node || !nix_tm_is_leaf(nix, node->lvl) || !node->parent ||\n-\t    node->parent->hw_id == NIX_TM_HW_ID_INVALID)\n+\t    node->parent->hw_id == NIX_TM_HW_ID_INVALID) {\n \t\treturn NIX_ERR_TM_INVALID_NODE;\n+\t}\n \n \tparent = node->parent;\n \tflags = parent->flags;\n \n-\treq = mbox_alloc_msg_nix_txschq_cfg(mbox);\n+\treq = mbox_alloc_msg_nix_txschq_cfg(mbox_get(mbox));\n \treq->lvl = NIX_TXSCH_LVL_MDQ;\n \treg = req->reg;\n \tregval = req->regval;\n@@ -1043,6 +1075,7 @@ roc_nix_tm_rlimit_sq(struct roc_nix *roc_nix, uint16_t qid, uint64_t rate)\n exit:\n \treq->num_regs = k;\n \trc = mbox_process(mbox);\n+\tmbox_put(mbox);\n \tif (rc)\n \t\treturn rc;\n \n@@ -1068,14 +1101,17 @@ roc_nix_tm_fini(struct roc_nix *roc_nix)\n \t\tplt_err(\"Failed to freeup existing nodes or rsrcs, rc=%d\", rc);\n \n \t/* Free all other hw resources */\n-\treq = mbox_alloc_msg_nix_txsch_free(mbox);\n-\tif (req == NULL)\n+\treq = mbox_alloc_msg_nix_txsch_free(mbox_get(mbox));\n+\tif (req == NULL) {\n+\t\tmbox_put(mbox);\n \t\treturn;\n+\t}\n \n \treq->flags = TXSCHQ_FREE_ALL;\n \trc = mbox_process(mbox);\n \tif (rc)\n \t\tplt_err(\"Failed to freeup all res, rc=%d\", rc);\n+\tmbox_put(mbox);\n \n \tfor (hw_lvl = 0; hw_lvl < NIX_TXSCH_LVL_CNT; hw_lvl++) {\n \t\tplt_bitmap_reset(nix->schq_bmp[hw_lvl]);\n@@ -1094,7 +1130,7 @@ int\n roc_nix_tm_rsrc_count(struct roc_nix *roc_nix, uint16_t schq[ROC_TM_LVL_MAX])\n {\n \tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n-\tstruct mbox *mbox = (&nix->dev)->mbox;\n+\tstruct mbox *mbox = mbox_get((&nix->dev)->mbox);\n \tstruct free_rsrcs_rsp *rsp;\n \tuint8_t hw_lvl;\n \tint rc, i;\n@@ -1103,7 +1139,7 @@ roc_nix_tm_rsrc_count(struct roc_nix *roc_nix, uint16_t schq[ROC_TM_LVL_MAX])\n \tmbox_alloc_msg_free_rsrc_cnt(mbox);\n \trc = mbox_process_msg(mbox, (void *)&rsp);\n \tif (rc)\n-\t\treturn rc;\n+\t\tgoto exit;\n \n \tfor (i = 0; i < ROC_TM_LVL_MAX; i++) {\n \t\thw_lvl = nix_tm_lvl2nix(nix, i);\n@@ -1114,7 +1150,10 @@ roc_nix_tm_rsrc_count(struct roc_nix *roc_nix, uint16_t schq[ROC_TM_LVL_MAX])\n \t\t\t\t\t\trsp->schq[hw_lvl]);\n \t}\n \n-\treturn 0;\n+\trc = 0;\n+exit:\n+\tmbox_put(mbox);\n+\treturn rc;\n }\n \n void\ndiff --git a/drivers/common/cnxk/roc_nix_tm_utils.c b/drivers/common/cnxk/roc_nix_tm_utils.c\nindex d33e793664..a52b897713 100644\n--- a/drivers/common/cnxk/roc_nix_tm_utils.c\n+++ b/drivers/common/cnxk/roc_nix_tm_utils.c\n@@ -1166,7 +1166,7 @@ roc_nix_tm_node_stats_get(struct roc_nix *roc_nix, uint32_t node_id, bool clear,\n \n \tmemset(n_stats, 0, sizeof(struct roc_nix_tm_node_stats));\n \n-\treq = mbox_alloc_msg_nix_txschq_cfg(mbox);\n+\treq = mbox_alloc_msg_nix_txschq_cfg(mbox_get(mbox));\n \treq->read = 1;\n \treq->lvl = NIX_TXSCH_LVL_TL1;\n \n@@ -1182,8 +1182,10 @@ roc_nix_tm_node_stats_get(struct roc_nix *roc_nix, uint32_t node_id, bool clear,\n \treq->num_regs = i;\n \n \trc = mbox_process_msg(mbox, (void **)&rsp);\n-\tif (rc)\n+\tif (rc) {\n+\t\tmbox_put(mbox);\n \t\treturn rc;\n+\t}\n \n \t/* Return stats */\n \tn_stats->stats[ROC_NIX_TM_NODE_PKTS_DROPPED] = rsp->regval[0];\n@@ -1194,13 +1196,14 @@ roc_nix_tm_node_stats_get(struct roc_nix *roc_nix, uint32_t node_id, bool clear,\n \tn_stats->stats[ROC_NIX_TM_NODE_YELLOW_BYTES] = rsp->regval[5];\n \tn_stats->stats[ROC_NIX_TM_NODE_RED_PKTS] = rsp->regval[6];\n \tn_stats->stats[ROC_NIX_TM_NODE_RED_BYTES] = rsp->regval[7];\n+\tmbox_put(mbox);\n \n clear_stats:\n \tif (!clear)\n \t\treturn 0;\n \n \t/* Clear all the stats */\n-\treq = mbox_alloc_msg_nix_txschq_cfg(mbox);\n+\treq = mbox_alloc_msg_nix_txschq_cfg(mbox_get(mbox));\n \treq->lvl = NIX_TXSCH_LVL_TL1;\n \ti = 0;\n \treq->reg[i++] = NIX_AF_TL1X_DROPPED_PACKETS(schq);\n@@ -1213,7 +1216,9 @@ roc_nix_tm_node_stats_get(struct roc_nix *roc_nix, uint32_t node_id, bool clear,\n \treq->reg[i++] = NIX_AF_TL1X_RED_BYTES(schq);\n \treq->num_regs = i;\n \n-\treturn mbox_process_msg(mbox, (void **)&rsp);\n+\trc = mbox_process_msg(mbox, (void **)&rsp);\n+\tmbox_put(mbox);\n+\treturn rc;\n }\n \n bool\ndiff --git a/drivers/common/cnxk/roc_nix_vlan.c b/drivers/common/cnxk/roc_nix_vlan.c\nindex 66bf8adbb3..abd2eb0571 100644\n--- a/drivers/common/cnxk/roc_nix_vlan.c\n+++ b/drivers/common/cnxk/roc_nix_vlan.c\n@@ -5,29 +5,25 @@\n #include \"roc_api.h\"\n #include \"roc_priv.h\"\n \n-static inline struct mbox *\n-get_mbox(struct roc_nix *roc_nix)\n-{\n-\tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n-\tstruct dev *dev = &nix->dev;\n-\n-\treturn dev->mbox;\n-}\n-\n int\n roc_nix_vlan_mcam_entry_read(struct roc_nix *roc_nix, uint32_t index,\n \t\t\t     struct npc_mcam_read_entry_rsp **rsp)\n {\n-\tstruct mbox *mbox = get_mbox(roc_nix);\n+\tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n+\tstruct dev *dev = &nix->dev;\n+\tstruct mbox *mbox = mbox_get(dev->mbox);\n \tstruct npc_mcam_read_entry_req *req;\n \tint rc = -ENOSPC;\n \n \treq = mbox_alloc_msg_npc_mcam_read_entry(mbox);\n \tif (req == NULL)\n-\t\treturn rc;\n+\t\tgoto exit;\n \treq->entry = index;\n \n-\treturn mbox_process_msg(mbox, (void **)rsp);\n+\trc = mbox_process_msg(mbox, (void **)rsp);\n+exit:\n+\tmbox_put(mbox);\n+\treturn rc;\n }\n \n int\n@@ -35,20 +31,25 @@ roc_nix_vlan_mcam_entry_write(struct roc_nix *roc_nix, uint32_t index,\n \t\t\t      struct mcam_entry *entry, uint8_t intf,\n \t\t\t      uint8_t enable)\n {\n-\tstruct mbox *mbox = get_mbox(roc_nix);\n+\tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n+\tstruct dev *dev = &nix->dev;\n+\tstruct mbox *mbox = mbox_get(dev->mbox);\n \tstruct npc_mcam_write_entry_req *req;\n \tstruct msghdr *rsp;\n \tint rc = -ENOSPC;\n \n \treq = mbox_alloc_msg_npc_mcam_write_entry(mbox);\n \tif (req == NULL)\n-\t\treturn rc;\n+\t\tgoto exit;\n \treq->entry = index;\n \treq->intf = intf;\n \treq->enable_entry = enable;\n \tmbox_memcpy(&req->entry_data, entry, sizeof(struct mcam_entry));\n \n-\treturn mbox_process_msg(mbox, (void *)&rsp);\n+\trc = mbox_process_msg(mbox, (void *)&rsp);\n+exit:\n+\tmbox_put(mbox);\n+\treturn rc;\n }\n \n int\n@@ -58,12 +59,14 @@ roc_nix_vlan_mcam_entry_alloc_and_write(struct roc_nix *roc_nix,\n {\n \tstruct npc_mcam_alloc_and_write_entry_req *req;\n \tstruct npc_mcam_alloc_and_write_entry_rsp *rsp;\n-\tstruct mbox *mbox = get_mbox(roc_nix);\n+\tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n+\tstruct dev *dev = &nix->dev;\n+\tstruct mbox *mbox = mbox_get(dev->mbox);\n \tint rc = -ENOSPC;\n \n \treq = mbox_alloc_msg_npc_mcam_alloc_and_write_entry(mbox);\n \tif (req == NULL)\n-\t\treturn rc;\n+\t\tgoto exit;\n \treq->priority = priority;\n \treq->ref_entry = ref_entry;\n \treq->intf = intf;\n@@ -72,24 +75,32 @@ roc_nix_vlan_mcam_entry_alloc_and_write(struct roc_nix *roc_nix,\n \n \trc = mbox_process_msg(mbox, (void *)&rsp);\n \tif (rc)\n-\t\treturn rc;\n+\t\tgoto exit;\n \n-\treturn rsp->entry;\n+\trc = rsp->entry;\n+exit:\n+\tmbox_put(mbox);\n+\treturn rc;\n }\n \n int\n roc_nix_vlan_mcam_entry_free(struct roc_nix *roc_nix, uint32_t index)\n {\n-\tstruct mbox *mbox = get_mbox(roc_nix);\n+\tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n+\tstruct dev *dev = &nix->dev;\n+\tstruct mbox *mbox = mbox_get(dev->mbox);\n \tstruct npc_mcam_free_entry_req *req;\n \tint rc = -ENOSPC;\n \n \treq = mbox_alloc_msg_npc_mcam_free_entry(mbox);\n \tif (req == NULL)\n-\t\treturn rc;\n+\t\tgoto exit;\n \treq->entry = index;\n \n-\treturn mbox_process_msg(mbox, NULL);\n+\trc = mbox_process_msg(mbox, NULL);\n+exit:\n+\tmbox_put(mbox);\n+\treturn rc;\n }\n \n int\n@@ -97,33 +108,40 @@ roc_nix_vlan_mcam_entry_ena_dis(struct roc_nix *roc_nix, uint32_t index,\n \t\t\t\tconst int enable)\n {\n \tstruct npc_mcam_ena_dis_entry_req *req;\n-\tstruct mbox *mbox = get_mbox(roc_nix);\n+\tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n+\tstruct dev *dev = &nix->dev;\n+\tstruct mbox *mbox = mbox_get(dev->mbox);\n \tint rc = -ENOSPC;\n \n \tif (enable) {\n \t\treq = mbox_alloc_msg_npc_mcam_ena_entry(mbox);\n \t\tif (req == NULL)\n-\t\t\treturn rc;\n+\t\t\tgoto exit;\n \t} else {\n \t\treq = mbox_alloc_msg_npc_mcam_dis_entry(mbox);\n \t\tif (req == NULL)\n-\t\t\treturn rc;\n+\t\t\tgoto exit;\n \t}\n \n \treq->entry = index;\n-\treturn mbox_process_msg(mbox, NULL);\n+\trc =  mbox_process_msg(mbox, NULL);\n+exit:\n+\tmbox_put(mbox);\n+\treturn rc;\n }\n \n int\n roc_nix_vlan_strip_vtag_ena_dis(struct roc_nix *roc_nix, bool enable)\n {\n-\tstruct mbox *mbox = get_mbox(roc_nix);\n+\tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n+\tstruct dev *dev = &nix->dev;\n+\tstruct mbox *mbox = mbox_get(dev->mbox);\n \tstruct nix_vtag_config *vtag_cfg;\n \tint rc = -ENOSPC;\n \n \tvtag_cfg = mbox_alloc_msg_nix_vtag_cfg(mbox);\n \tif (vtag_cfg == NULL)\n-\t\treturn rc;\n+\t\tgoto exit;\n \tvtag_cfg->vtag_size = NIX_VTAGSIZE_T4;\n \tvtag_cfg->cfg_type = 1;\t       /* Rx VLAN configuration */\n \tvtag_cfg->rx.capture_vtag = 1; /* Always capture */\n@@ -134,7 +152,10 @@ roc_nix_vlan_strip_vtag_ena_dis(struct roc_nix *roc_nix, bool enable)\n \telse\n \t\tvtag_cfg->rx.strip_vtag = 0;\n \n-\treturn mbox_process(mbox);\n+\trc = mbox_process(mbox);\n+exit:\n+\tmbox_put(mbox);\n+\treturn rc;\n }\n \n int\n@@ -142,14 +163,16 @@ roc_nix_vlan_insert_ena_dis(struct roc_nix *roc_nix,\n \t\t\t    struct roc_nix_vlan_config *vlan_cfg,\n \t\t\t    uint64_t *mcam_index, bool enable)\n {\n-\tstruct mbox *mbox = get_mbox(roc_nix);\n+\tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n+\tstruct dev *dev = &nix->dev;\n+\tstruct mbox *mbox = mbox_get(dev->mbox);\n \tstruct nix_vtag_config *vtag_cfg;\n \tstruct nix_vtag_config_rsp *rsp;\n \tint rc = -ENOSPC;\n \n \tvtag_cfg = mbox_alloc_msg_nix_vtag_cfg(mbox);\n \tif (vtag_cfg == NULL)\n-\t\treturn rc;\n+\t\tgoto exit;\n \tvtag_cfg->cfg_type = 0; /* Tx VLAN configuration */\n \tvtag_cfg->vtag_size = NIX_VTAGSIZE_T4;\n \n@@ -175,25 +198,30 @@ roc_nix_vlan_insert_ena_dis(struct roc_nix *roc_nix,\n \n \trc = mbox_process_msg(mbox, (void *)&rsp);\n \tif (rc)\n-\t\treturn rc;\n+\t\tgoto exit;\n \n \tif (enable)\n \t\t*mcam_index =\n \t\t\t(((uint64_t)rsp->vtag1_idx << 32) | rsp->vtag0_idx);\n \n-\treturn 0;\n+\trc = 0;\n+exit:\n+\tmbox_put(mbox);\n+\treturn rc;\n }\n \n int\n roc_nix_vlan_tpid_set(struct roc_nix *roc_nix, uint32_t type, uint16_t tpid)\n {\n-\tstruct mbox *mbox = get_mbox(roc_nix);\n+\tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n+\tstruct dev *dev = &nix->dev;\n+\tstruct mbox *mbox = mbox_get(dev->mbox);\n \tstruct nix_set_vlan_tpid *tpid_cfg;\n \tint rc = -ENOSPC;\n \n \ttpid_cfg = mbox_alloc_msg_nix_set_vlan_tpid(mbox);\n \tif (tpid_cfg == NULL)\n-\t\treturn rc;\n+\t\tgoto exit;\n \ttpid_cfg->tpid = tpid;\n \n \tif (type & ROC_NIX_VLAN_TYPE_OUTER)\n@@ -201,5 +229,8 @@ roc_nix_vlan_tpid_set(struct roc_nix *roc_nix, uint32_t type, uint16_t tpid)\n \telse\n \t\ttpid_cfg->vlan_type = NIX_VLAN_TYPE_INNER;\n \n-\treturn mbox_process(mbox);\n+\trc = mbox_process(mbox);\n+exit:\n+\tmbox_put(mbox);\n+\treturn rc;\n }\ndiff --git a/drivers/common/cnxk/roc_npa.c b/drivers/common/cnxk/roc_npa.c\nindex ee42434c38..9644477728 100644\n--- a/drivers/common/cnxk/roc_npa.c\n+++ b/drivers/common/cnxk/roc_npa.c\n@@ -40,17 +40,19 @@ roc_npa_aura_op_range_set(uint64_t aura_handle, uint64_t start_iova,\n }\n \n static int\n-npa_aura_pool_init(struct mbox *mbox, uint32_t aura_id, struct npa_aura_s *aura,\n+npa_aura_pool_init(struct mbox *m_box, uint32_t aura_id, struct npa_aura_s *aura,\n \t\t   struct npa_pool_s *pool)\n {\n \tstruct npa_aq_enq_req *aura_init_req, *pool_init_req;\n \tstruct npa_aq_enq_rsp *aura_init_rsp, *pool_init_rsp;\n-\tstruct mbox_dev *mdev = &mbox->dev[0];\n+\tstruct mbox_dev *mdev = &m_box->dev[0];\n \tint rc = -ENOSPC, off;\n+\tstruct mbox *mbox;\n \n+\tmbox = mbox_get(m_box);\n \taura_init_req = mbox_alloc_msg_npa_aq_enq(mbox);\n \tif (aura_init_req == NULL)\n-\t\treturn rc;\n+\t\tgoto exit;\n \taura_init_req->aura_id = aura_id;\n \taura_init_req->ctype = NPA_AQ_CTYPE_AURA;\n \taura_init_req->op = NPA_AQ_INSTOP_INIT;\n@@ -58,7 +60,7 @@ npa_aura_pool_init(struct mbox *mbox, uint32_t aura_id, struct npa_aura_s *aura,\n \n \tpool_init_req = mbox_alloc_msg_npa_aq_enq(mbox);\n \tif (pool_init_req == NULL)\n-\t\treturn rc;\n+\t\tgoto exit;\n \tpool_init_req->aura_id = aura_id;\n \tpool_init_req->ctype = NPA_AQ_CTYPE_POOL;\n \tpool_init_req->op = NPA_AQ_INSTOP_INIT;\n@@ -66,7 +68,7 @@ npa_aura_pool_init(struct mbox *mbox, uint32_t aura_id, struct npa_aura_s *aura,\n \n \trc = mbox_process(mbox);\n \tif (rc < 0)\n-\t\treturn rc;\n+\t\tgoto exit;\n \n \toff = mbox->rx_start +\n \t      PLT_ALIGN(sizeof(struct mbox_hdr), MBOX_MSG_ALIGN);\n@@ -75,19 +77,23 @@ npa_aura_pool_init(struct mbox *mbox, uint32_t aura_id, struct npa_aura_s *aura,\n \tpool_init_rsp = (struct npa_aq_enq_rsp *)((uintptr_t)mdev->mbase + off);\n \n \tif (aura_init_rsp->hdr.rc == 0 && pool_init_rsp->hdr.rc == 0)\n-\t\treturn 0;\n+\t\trc = 0;\n \telse\n-\t\treturn NPA_ERR_AURA_POOL_INIT;\n+\t\trc = NPA_ERR_AURA_POOL_INIT;\n+exit:\n+\tmbox_put(mbox);\n+\treturn rc;\n }\n \n static int\n-npa_aura_pool_fini(struct mbox *mbox, uint32_t aura_id, uint64_t aura_handle)\n+npa_aura_pool_fini(struct mbox *m_box, uint32_t aura_id, uint64_t aura_handle)\n {\n \tstruct npa_aq_enq_req *aura_req, *pool_req;\n \tstruct npa_aq_enq_rsp *aura_rsp, *pool_rsp;\n-\tstruct mbox_dev *mdev = &mbox->dev[0];\n+\tstruct mbox_dev *mdev = &m_box->dev[0];\n \tstruct ndc_sync_op *ndc_req;\n \tint rc = -ENOSPC, off;\n+\tstruct mbox *mbox;\n \tuint64_t ptr;\n \n \t/* Procedure for disabling an aura/pool */\n@@ -98,9 +104,10 @@ npa_aura_pool_fini(struct mbox *mbox, uint32_t aura_id, uint64_t aura_handle)\n \t\tptr = roc_npa_aura_op_alloc(aura_handle, 0);\n \t} while (ptr);\n \n+\tmbox = mbox_get(m_box);\n \tpool_req = mbox_alloc_msg_npa_aq_enq(mbox);\n \tif (pool_req == NULL)\n-\t\treturn rc;\n+\t\tgoto exit;\n \tpool_req->aura_id = aura_id;\n \tpool_req->ctype = NPA_AQ_CTYPE_POOL;\n \tpool_req->op = NPA_AQ_INSTOP_WRITE;\n@@ -109,7 +116,7 @@ npa_aura_pool_fini(struct mbox *mbox, uint32_t aura_id, uint64_t aura_handle)\n \n \taura_req = mbox_alloc_msg_npa_aq_enq(mbox);\n \tif (aura_req == NULL)\n-\t\treturn rc;\n+\t\tgoto exit;\n \taura_req->aura_id = aura_id;\n \taura_req->ctype = NPA_AQ_CTYPE_AURA;\n \taura_req->op = NPA_AQ_INSTOP_WRITE;\n@@ -118,7 +125,7 @@ npa_aura_pool_fini(struct mbox *mbox, uint32_t aura_id, uint64_t aura_handle)\n \n \trc = mbox_process(mbox);\n \tif (rc < 0)\n-\t\treturn rc;\n+\t\tgoto exit;\n \n \toff = mbox->rx_start +\n \t      PLT_ALIGN(sizeof(struct mbox_hdr), MBOX_MSG_ALIGN);\n@@ -132,15 +139,21 @@ npa_aura_pool_fini(struct mbox *mbox, uint32_t aura_id, uint64_t aura_handle)\n \n \t/* Sync NDC-NPA for LF */\n \tndc_req = mbox_alloc_msg_ndc_sync_op(mbox);\n-\tif (ndc_req == NULL)\n-\t\treturn -ENOSPC;\n+\tif (ndc_req == NULL) {\n+\t\trc = -ENOSPC;\n+\t\tgoto exit;\n+\t}\n \tndc_req->npa_lf_sync = 1;\n \trc = mbox_process(mbox);\n \tif (rc) {\n \t\tplt_err(\"Error on NDC-NPA LF sync, rc %d\", rc);\n-\t\treturn NPA_ERR_AURA_POOL_FINI;\n+\t\trc = NPA_ERR_AURA_POOL_FINI;\n+\t\tgoto exit;\n \t}\n-\treturn 0;\n+\trc = 0;\n+exit:\n+\tmbox_put(mbox);\n+\treturn rc;\n }\n \n int\n@@ -157,13 +170,13 @@ roc_npa_pool_op_pc_reset(uint64_t aura_handle)\n \tif (lf == NULL)\n \t\treturn NPA_ERR_PARAM;\n \n-\tmbox = lf->mbox;\n+\tmbox = mbox_get(lf->mbox);\n \tmdev = &mbox->dev[0];\n \tplt_npa_dbg(\"lf=%p aura_handle=0x%\" PRIx64, lf, aura_handle);\n \n \tpool_req = mbox_alloc_msg_npa_aq_enq(mbox);\n \tif (pool_req == NULL)\n-\t\treturn rc;\n+\t\tgoto exit;\n \tpool_req->aura_id = roc_npa_aura_handle_to_aura(aura_handle);\n \tpool_req->ctype = NPA_AQ_CTYPE_POOL;\n \tpool_req->op = NPA_AQ_INSTOP_WRITE;\n@@ -172,26 +185,34 @@ roc_npa_pool_op_pc_reset(uint64_t aura_handle)\n \n \trc = mbox_process(mbox);\n \tif (rc < 0)\n-\t\treturn rc;\n+\t\tgoto exit;\n \n \toff = mbox->rx_start +\n \t      PLT_ALIGN(sizeof(struct mbox_hdr), MBOX_MSG_ALIGN);\n \tpool_rsp = (struct npa_aq_enq_rsp *)((uintptr_t)mdev->mbase + off);\n \n-\tif (pool_rsp->hdr.rc != 0)\n-\t\treturn NPA_ERR_AURA_POOL_FINI;\n+\tif (pool_rsp->hdr.rc != 0) {\n+\t\trc = NPA_ERR_AURA_POOL_FINI;\n+\t\tgoto exit;\n+\t}\n \n \t/* Sync NDC-NPA for LF */\n \tndc_req = mbox_alloc_msg_ndc_sync_op(mbox);\n-\tif (ndc_req == NULL)\n-\t\treturn -ENOSPC;\n+\tif (ndc_req == NULL) {\n+\t\trc = -ENOSPC;\n+\t\tgoto exit;\n+\t}\n \tndc_req->npa_lf_sync = 1;\n \trc = mbox_process(mbox);\n \tif (rc) {\n \t\tplt_err(\"Error on NDC-NPA LF sync, rc %d\", rc);\n-\t\treturn NPA_ERR_AURA_POOL_FINI;\n+\t\trc = NPA_ERR_AURA_POOL_FINI;\n+\t\tgoto exit;\n \t}\n-\treturn 0;\n+\trc = 0;\n+exit:\n+\tmbox_put(mbox);\n+\treturn rc;\n }\n \n int\n@@ -199,15 +220,18 @@ roc_npa_aura_drop_set(uint64_t aura_handle, uint64_t limit, bool ena)\n {\n \tstruct npa_aq_enq_req *aura_req;\n \tstruct npa_lf *lf;\n+\tstruct mbox *mbox;\n \tint rc;\n \n \tlf = idev_npa_obj_get();\n \tif (lf == NULL)\n \t\treturn NPA_ERR_DEVICE_NOT_BOUNDED;\n-\n-\taura_req = mbox_alloc_msg_npa_aq_enq(lf->mbox);\n-\tif (aura_req == NULL)\n-\t\treturn -ENOMEM;\n+\tmbox = mbox_get(lf->mbox);\n+\taura_req = mbox_alloc_msg_npa_aq_enq(mbox);\n+\tif (aura_req == NULL) {\n+\t\trc = -ENOMEM;\n+\t\tgoto exit;\n+\t}\n \taura_req->aura_id = roc_npa_aura_handle_to_aura(aura_handle);\n \taura_req->ctype = NPA_AQ_CTYPE_AURA;\n \taura_req->op = NPA_AQ_INSTOP_WRITE;\n@@ -217,8 +241,10 @@ roc_npa_aura_drop_set(uint64_t aura_handle, uint64_t limit, bool ena)\n \taura_req->aura_mask.aura_drop_ena =\n \t\t~(aura_req->aura_mask.aura_drop_ena);\n \taura_req->aura_mask.aura_drop = ~(aura_req->aura_mask.aura_drop);\n-\trc = mbox_process(lf->mbox);\n+\trc = mbox_process(mbox);\n \n+exit:\n+\tmbox_put(mbox);\n \treturn rc;\n }\n \n@@ -326,12 +352,16 @@ npa_aura_pool_pair_alloc(struct npa_lf *lf, const uint32_t block_size,\n \t\treturn NPA_ERR_INVALID_BLOCK_SZ;\n \n \t/* Get aura_id from resource bitmap */\n+\troc_npa_dev_lock();\n \taura_id = find_free_aura(lf, flags);\n-\tif (aura_id < 0)\n+\tif (aura_id < 0) {\n+\t\troc_npa_dev_unlock();\n \t\treturn NPA_ERR_AURA_ID_ALLOC;\n+\t}\n \n \t/* Mark pool as reserved */\n \tplt_bitmap_clear(lf->npa_bmp, aura_id);\n+\troc_npa_dev_unlock();\n \n \t/* Configuration based on each aura has separate pool(aura-pool pair) */\n \tpool_id = aura_id;\n@@ -401,7 +431,9 @@ npa_aura_pool_pair_alloc(struct npa_lf *lf, const uint32_t block_size,\n stack_mem_free:\n \tplt_memzone_free(mz);\n aura_res_put:\n+\troc_npa_dev_lock();\n \tplt_bitmap_set(lf->npa_bmp, aura_id);\n+\troc_npa_dev_unlock();\n exit:\n \treturn rc;\n }\n@@ -466,23 +498,28 @@ roc_npa_aura_limit_modify(uint64_t aura_handle, uint16_t aura_limit)\n {\n \tstruct npa_aq_enq_req *aura_req;\n \tstruct npa_lf *lf;\n+\tstruct mbox *mbox;\n \tint rc;\n \n \tlf = idev_npa_obj_get();\n \tif (lf == NULL)\n \t\treturn NPA_ERR_DEVICE_NOT_BOUNDED;\n \n-\taura_req = mbox_alloc_msg_npa_aq_enq(lf->mbox);\n-\tif (aura_req == NULL)\n-\t\treturn -ENOMEM;\n+\tmbox = mbox_get(lf->mbox);\n+\taura_req = mbox_alloc_msg_npa_aq_enq(mbox);\n+\tif (aura_req == NULL) {\n+\t\trc = -ENOMEM;\n+\t\tgoto exit;\n+\t}\n \taura_req->aura_id = roc_npa_aura_handle_to_aura(aura_handle);\n \taura_req->ctype = NPA_AQ_CTYPE_AURA;\n \taura_req->op = NPA_AQ_INSTOP_WRITE;\n \n \taura_req->aura.limit = aura_limit;\n \taura_req->aura_mask.limit = ~(aura_req->aura_mask.limit);\n-\trc = mbox_process(lf->mbox);\n-\n+\trc = mbox_process(mbox);\n+exit:\n+\tmbox_put(mbox);\n \treturn rc;\n }\n \n@@ -501,7 +538,9 @@ npa_aura_pool_pair_free(struct npa_lf *lf, uint64_t aura_handle)\n \trc |= npa_stack_dma_free(lf, name, pool_id);\n \tmemset(&lf->aura_attr[aura_id], 0, sizeof(struct npa_aura_attr));\n \n+\troc_npa_dev_lock();\n \tplt_bitmap_set(lf->npa_bmp, aura_id);\n+\troc_npa_dev_unlock();\n \n \treturn rc;\n }\n@@ -531,6 +570,7 @@ roc_npa_pool_range_update_check(uint64_t aura_handle)\n \t__io struct npa_pool_s *pool;\n \tstruct npa_aq_enq_req *req;\n \tstruct npa_aq_enq_rsp *rsp;\n+\tstruct mbox *mbox;\n \tint rc;\n \n \tlf = idev_npa_obj_get();\n@@ -539,28 +579,35 @@ roc_npa_pool_range_update_check(uint64_t aura_handle)\n \n \tlim = lf->aura_lim;\n \n-\treq = mbox_alloc_msg_npa_aq_enq(lf->mbox);\n-\tif (req == NULL)\n-\t\treturn -ENOSPC;\n+\tmbox = mbox_get(lf->mbox);\n+\treq = mbox_alloc_msg_npa_aq_enq(mbox);\n+\tif (req == NULL) {\n+\t\trc = -ENOSPC;\n+\t\tgoto exit;\n+\t}\n \n \treq->aura_id = aura_id;\n \treq->ctype = NPA_AQ_CTYPE_POOL;\n \treq->op = NPA_AQ_INSTOP_READ;\n \n-\trc = mbox_process_msg(lf->mbox, (void *)&rsp);\n+\trc = mbox_process_msg(mbox, (void *)&rsp);\n \tif (rc) {\n \t\tplt_err(\"Failed to get pool(0x%\" PRIx64 \") context\", aura_id);\n-\t\treturn rc;\n+\t\tgoto exit;\n \t}\n \n \tpool = &rsp->pool;\n \tif (lim[aura_id].ptr_start != pool->ptr_start ||\n \t    lim[aura_id].ptr_end != pool->ptr_end) {\n \t\tplt_err(\"Range update failed on pool(0x%\" PRIx64 \")\", aura_id);\n-\t\treturn NPA_ERR_PARAM;\n+\t\trc = NPA_ERR_PARAM;\n+\t\tgoto exit;\n \t}\n \n-\treturn 0;\n+\trc = 0;\n+exit:\n+\tmbox_put(mbox);\n+\treturn rc;\n }\n \n uint64_t\n@@ -584,36 +631,51 @@ roc_npa_zero_aura_handle(void)\n }\n \n static inline int\n-npa_attach(struct mbox *mbox)\n+npa_attach(struct mbox *m_box)\n {\n+\tstruct mbox *mbox = mbox_get(m_box);\n \tstruct rsrc_attach_req *req;\n+\tint rc;\n \n \treq = mbox_alloc_msg_attach_resources(mbox);\n-\tif (req == NULL)\n-\t\treturn -ENOSPC;\n+\tif (req == NULL) {\n+\t\trc = -ENOSPC;\n+\t\tgoto exit;\n+\t}\n \treq->modify = true;\n \treq->npalf = true;\n \n-\treturn mbox_process(mbox);\n+\trc = mbox_process(mbox);\n+exit:\n+\tmbox_put(mbox);\n+\treturn rc;\n }\n \n static inline int\n-npa_detach(struct mbox *mbox)\n+npa_detach(struct mbox *m_box)\n {\n+\tstruct mbox *mbox = mbox_get(m_box);\n \tstruct rsrc_detach_req *req;\n+\tint rc;\n \n \treq = mbox_alloc_msg_detach_resources(mbox);\n-\tif (req == NULL)\n-\t\treturn -ENOSPC;\n+\tif (req == NULL) {\n+\t\trc = -ENOSPC;\n+\t\tgoto exit;\n+\t}\n \treq->partial = true;\n \treq->npalf = true;\n \n-\treturn mbox_process(mbox);\n+\trc = mbox_process(mbox);\n+exit:\n+\tmbox_put(mbox);\n+\treturn rc;\n }\n \n static inline int\n-npa_get_msix_offset(struct mbox *mbox, uint16_t *npa_msixoff)\n+npa_get_msix_offset(struct mbox *m_box, uint16_t *npa_msixoff)\n {\n+\tstruct mbox *mbox = mbox_get(m_box);\n \tstruct msix_offset_rsp *msix_rsp;\n \tint rc;\n \n@@ -623,39 +685,52 @@ npa_get_msix_offset(struct mbox *mbox, uint16_t *npa_msixoff)\n \tif (rc == 0)\n \t\t*npa_msixoff = msix_rsp->npa_msixoff;\n \n+\tmbox_put(mbox);\n \treturn rc;\n }\n \n static inline int\n npa_lf_alloc(struct npa_lf *lf)\n {\n-\tstruct mbox *mbox = lf->mbox;\n+\tstruct mbox *mbox = mbox_get(lf->mbox);\n \tstruct npa_lf_alloc_req *req;\n \tstruct npa_lf_alloc_rsp *rsp;\n \tint rc;\n \n \treq = mbox_alloc_msg_npa_lf_alloc(mbox);\n-\tif (req == NULL)\n-\t\treturn -ENOSPC;\n+\tif (req == NULL) {\n+\t\trc =  -ENOSPC;\n+\t\tgoto exit;\n+\t}\n \treq->aura_sz = lf->aura_sz;\n \treq->nr_pools = lf->nr_pools;\n \n \trc = mbox_process_msg(mbox, (void *)&rsp);\n-\tif (rc)\n-\t\treturn NPA_ERR_ALLOC;\n+\tif (rc) {\n+\t\trc = NPA_ERR_ALLOC;\n+\t\tgoto exit;\n+\t}\n \n \tlf->stack_pg_ptrs = rsp->stack_pg_ptrs;\n \tlf->stack_pg_bytes = rsp->stack_pg_bytes;\n \tlf->qints = rsp->qints;\n \n-\treturn 0;\n+\trc = 0;\n+exit:\n+\tmbox_put(mbox);\n+\treturn rc;\n }\n \n static int\n-npa_lf_free(struct mbox *mbox)\n+npa_lf_free(struct mbox *mail_box)\n {\n+\tstruct mbox *mbox = mbox_get(mail_box);\n+\tint rc;\n+\n \tmbox_alloc_msg_npa_lf_free(mbox);\n-\treturn mbox_process(mbox);\n+\trc = mbox_process(mbox);\n+\tmbox_put(mbox);\n+\treturn rc;\n }\n \n static inline uint32_t\n@@ -921,3 +996,21 @@ roc_npa_dev_fini(struct roc_npa *roc_npa)\n \tnpa->dev.drv_inited = false;\n \treturn dev_fini(&npa->dev, npa->pci_dev);\n }\n+\n+void\n+roc_npa_dev_lock(void)\n+{\n+\tstruct idev_cfg *idev = idev_get_cfg();\n+\n+\tif (idev != NULL)\n+\t\tplt_spinlock_lock(&idev->npa_dev_lock);\n+}\n+\n+void\n+roc_npa_dev_unlock(void)\n+{\n+\tstruct idev_cfg *idev = idev_get_cfg();\n+\n+\tif (idev != NULL)\n+\t\tplt_spinlock_unlock(&idev->npa_dev_lock);\n+}\ndiff --git a/drivers/common/cnxk/roc_npa.h b/drivers/common/cnxk/roc_npa.h\nindex fed1942404..82596876f0 100644\n--- a/drivers/common/cnxk/roc_npa.h\n+++ b/drivers/common/cnxk/roc_npa.h\n@@ -763,4 +763,7 @@ int __roc_api roc_npa_pool_op_pc_reset(uint64_t aura_handle);\n int __roc_api roc_npa_aura_drop_set(uint64_t aura_handle, uint64_t limit,\n \t\t\t\t    bool ena);\n \n+void __roc_api roc_npa_dev_lock(void);\n+void __roc_api roc_npa_dev_unlock(void);\n+\n #endif /* _ROC_NPA_H_ */\ndiff --git a/drivers/common/cnxk/roc_npa_debug.c b/drivers/common/cnxk/roc_npa_debug.c\nindex 798ace291c..173d32cd9b 100644\n--- a/drivers/common/cnxk/roc_npa_debug.c\n+++ b/drivers/common/cnxk/roc_npa_debug.c\n@@ -91,6 +91,7 @@ roc_npa_ctx_dump(void)\n {\n \tstruct npa_aq_enq_req *aq;\n \tstruct npa_aq_enq_rsp *rsp;\n+\tstruct mbox *mbox;\n \tstruct npa_lf *lf;\n \tuint32_t q;\n \tint rc = 0;\n@@ -98,23 +99,26 @@ roc_npa_ctx_dump(void)\n \tlf = idev_npa_obj_get();\n \tif (lf == NULL)\n \t\treturn NPA_ERR_DEVICE_NOT_BOUNDED;\n+\tmbox = mbox_get(lf->mbox);\n \n \tfor (q = 0; q < lf->nr_pools; q++) {\n \t\t/* Skip disabled POOL */\n \t\tif (plt_bitmap_get(lf->npa_bmp, q))\n \t\t\tcontinue;\n \n-\t\taq = mbox_alloc_msg_npa_aq_enq(lf->mbox);\n-\t\tif (aq == NULL)\n-\t\t\treturn -ENOSPC;\n+\t\taq = mbox_alloc_msg_npa_aq_enq(mbox);\n+\t\tif (aq == NULL) {\n+\t\t\trc = -ENOSPC;\n+\t\t\tgoto exit;\n+\t\t}\n \t\taq->aura_id = q;\n \t\taq->ctype = NPA_AQ_CTYPE_POOL;\n \t\taq->op = NPA_AQ_INSTOP_READ;\n \n-\t\trc = mbox_process_msg(lf->mbox, (void *)&rsp);\n+\t\trc = mbox_process_msg(mbox, (void *)&rsp);\n \t\tif (rc) {\n \t\t\tplt_err(\"Failed to get pool(%d) context\", q);\n-\t\t\treturn rc;\n+\t\t\tgoto exit;\n \t\t}\n \t\tnpa_dump(\"============== pool=%d ===============\\n\", q);\n \t\tnpa_pool_dump(&rsp->pool);\n@@ -125,22 +129,26 @@ roc_npa_ctx_dump(void)\n \t\tif (plt_bitmap_get(lf->npa_bmp, q))\n \t\t\tcontinue;\n \n-\t\taq = mbox_alloc_msg_npa_aq_enq(lf->mbox);\n-\t\tif (aq == NULL)\n-\t\t\treturn -ENOSPC;\n+\t\taq = mbox_alloc_msg_npa_aq_enq(mbox);\n+\t\tif (aq == NULL) {\n+\t\t\trc = -ENOSPC;\n+\t\t\tgoto exit;\n+\t\t}\n \t\taq->aura_id = q;\n \t\taq->ctype = NPA_AQ_CTYPE_AURA;\n \t\taq->op = NPA_AQ_INSTOP_READ;\n \n-\t\trc = mbox_process_msg(lf->mbox, (void *)&rsp);\n+\t\trc = mbox_process_msg(mbox, (void *)&rsp);\n \t\tif (rc) {\n \t\t\tplt_err(\"Failed to get aura(%d) context\", q);\n-\t\t\treturn rc;\n+\t\t\tgoto exit;\n \t\t}\n \t\tnpa_dump(\"============== aura=%d ===============\\n\", q);\n \t\tnpa_aura_dump(&rsp->aura);\n \t}\n \n+exit:\n+\tmbox_put(mbox);\n \treturn rc;\n }\n \ndiff --git a/drivers/common/cnxk/roc_npc.c b/drivers/common/cnxk/roc_npc.c\nindex b38389b18a..2a2363033b 100644\n--- a/drivers/common/cnxk/roc_npc.c\n+++ b/drivers/common/cnxk/roc_npc.c\n@@ -947,13 +947,15 @@ npc_vtag_cfg_delete(struct roc_npc *roc_npc, struct roc_npc_flow *flow)\n \t} tx_vtag_action;\n \n \tnix = roc_nix_to_nix_priv(roc_nix);\n-\tmbox = (&nix->dev)->mbox;\n+\tmbox = mbox_get((&nix->dev)->mbox);\n \n \ttx_vtag_action.reg = flow->vtag_action;\n \tvtag_cfg = mbox_alloc_msg_nix_vtag_cfg(mbox);\n \n-\tif (vtag_cfg == NULL)\n-\t\treturn -ENOSPC;\n+\tif (vtag_cfg == NULL) {\n+\t\trc = -ENOSPC;\n+\t\tgoto exit;\n+\t}\n \n \tvtag_cfg->cfg_type = VTAG_TX;\n \tvtag_cfg->vtag_size = NIX_VTAGSIZE_T4;\n@@ -967,9 +969,12 @@ npc_vtag_cfg_delete(struct roc_npc *roc_npc, struct roc_npc_flow *flow)\n \n \trc = mbox_process_msg(mbox, (void *)&rsp);\n \tif (rc)\n-\t\treturn rc;\n+\t\tgoto exit;\n \n-\treturn 0;\n+\trc =  0;\n+exit:\n+\tmbox_put(mbox);\n+\treturn rc;\n }\n \n static int\n@@ -1063,10 +1068,12 @@ npc_vtag_insert_action_configure(struct mbox *mbox, struct roc_npc_flow *flow,\n \t\tstruct nix_tx_vtag_action_s act;\n \t} tx_vtag_action;\n \n-\tvtag_cfg = mbox_alloc_msg_nix_vtag_cfg(mbox);\n+\tvtag_cfg = mbox_alloc_msg_nix_vtag_cfg(mbox_get(mbox));\n \n-\tif (vtag_cfg == NULL)\n-\t\treturn -ENOSPC;\n+\tif (vtag_cfg == NULL) {\n+\t\trc = -ENOSPC;\n+\t\tgoto exit;\n+\t}\n \n \tvtag_cfg->cfg_type = VTAG_TX;\n \tvtag_cfg->vtag_size = NIX_VTAGSIZE_T4;\n@@ -1086,12 +1093,13 @@ npc_vtag_insert_action_configure(struct mbox *mbox, struct roc_npc_flow *flow,\n \n \trc = mbox_process_msg(mbox, (void *)&rsp);\n \tif (rc)\n-\t\treturn rc;\n+\t\tgoto exit;\n \n \tif (rsp->vtag0_idx < 0 ||\n \t    ((flow->vtag_insert_count == 2) && (rsp->vtag1_idx < 0))) {\n \t\tplt_err(\"Failed to config TX VTAG action\");\n-\t\treturn -EINVAL;\n+\t\trc =  -EINVAL;\n+\t\tgoto exit;\n \t}\n \n \ttx_vtag_action.reg = 0;\n@@ -1116,7 +1124,10 @@ npc_vtag_insert_action_configure(struct mbox *mbox, struct roc_npc_flow *flow,\n \n \tflow->vtag_action = tx_vtag_action.reg;\n \n-\treturn 0;\n+\trc = 0;\n+exit:\n+\tmbox_put(mbox);\n+\treturn rc;\n }\n \n static int\n@@ -1135,10 +1146,12 @@ npc_vtag_strip_action_configure(struct mbox *mbox,\n \t\t\t(*strip_cnt)++;\n \t}\n \n-\tvtag_cfg = mbox_alloc_msg_nix_vtag_cfg(mbox);\n+\tvtag_cfg = mbox_alloc_msg_nix_vtag_cfg(mbox_get(mbox));\n \n-\tif (vtag_cfg == NULL)\n-\t\treturn -ENOSPC;\n+\tif (vtag_cfg == NULL) {\n+\t\trc = -ENOSPC;\n+\t\tgoto exit;\n+\t}\n \n \tvtag_cfg->cfg_type = VTAG_RX;\n \tvtag_cfg->rx.strip_vtag = 1;\n@@ -1149,7 +1162,7 @@ npc_vtag_strip_action_configure(struct mbox *mbox,\n \n \trc = mbox_process(mbox);\n \tif (rc)\n-\t\treturn rc;\n+\t\tgoto exit;\n \n \trx_vtag_action |= (NIX_RX_VTAGACTION_VTAG_VALID << 15);\n \trx_vtag_action |= ((uint64_t)NPC_LID_LB << 8);\n@@ -1162,7 +1175,10 @@ npc_vtag_strip_action_configure(struct mbox *mbox,\n \t}\n \tflow->vtag_action = rx_vtag_action;\n \n-\treturn 0;\n+\trc = 0;\n+exit:\n+\tmbox_put(mbox);\n+\treturn rc;\n }\n \n static int\n@@ -1400,16 +1416,19 @@ roc_npc_mcam_merge_base_steering_rule(struct roc_npc *roc_npc,\n \tstruct npc_mcam_read_base_rule_rsp *base_rule_rsp;\n \tstruct npc *npc = roc_npc_to_npc_priv(roc_npc);\n \tstruct mcam_entry *base_entry;\n+\tstruct mbox *mbox = mbox_get(npc->mbox);\n \tint idx, rc;\n \n-\tif (roc_nix_is_pf(roc_npc->roc_nix))\n-\t\treturn 0;\n+\tif (roc_nix_is_pf(roc_npc->roc_nix)) {\n+\t\trc = 0;\n+\t\tgoto exit;\n+\t}\n \n-\t(void)mbox_alloc_msg_npc_read_base_steer_rule(npc->mbox);\n-\trc = mbox_process_msg(npc->mbox, (void *)&base_rule_rsp);\n+\t(void)mbox_alloc_msg_npc_read_base_steer_rule(mbox);\n+\trc = mbox_process_msg(mbox, (void *)&base_rule_rsp);\n \tif (rc) {\n \t\tplt_err(\"Failed to fetch VF's base MCAM entry\");\n-\t\treturn rc;\n+\t\tgoto exit;\n \t}\n \tbase_entry = &base_rule_rsp->entry_data;\n \tfor (idx = 0; idx < ROC_NPC_MAX_MCAM_WIDTH_DWORDS; idx++) {\n@@ -1417,5 +1436,8 @@ roc_npc_mcam_merge_base_steering_rule(struct roc_npc *roc_npc,\n \t\tflow->mcam_mask[idx] |= base_entry->kw_mask[idx];\n \t}\n \n-\treturn 0;\n+\trc = 0;\n+exit:\n+\tmbox_put(mbox);\n+\treturn rc;\n }\ndiff --git a/drivers/common/cnxk/roc_npc_mcam.c b/drivers/common/cnxk/roc_npc_mcam.c\nindex a725cabc57..33380ede10 100644\n--- a/drivers/common/cnxk/roc_npc_mcam.c\n+++ b/drivers/common/cnxk/roc_npc_mcam.c\n@@ -12,14 +12,16 @@ npc_mcam_alloc_counter(struct npc *npc, uint16_t *ctr)\n \tstruct mbox *mbox = npc->mbox;\n \tint rc = -ENOSPC;\n \n-\treq = mbox_alloc_msg_npc_mcam_alloc_counter(mbox);\n+\treq = mbox_alloc_msg_npc_mcam_alloc_counter(mbox_get(mbox));\n \tif (req == NULL)\n-\t\treturn rc;\n+\t\tgoto exit;\n \treq->count = 1;\n \trc = mbox_process_msg(mbox, (void *)&rsp);\n \tif (rc)\n-\t\treturn rc;\n+\t\tgoto exit;\n \t*ctr = rsp->cntr_list[0];\n+exit:\n+\tmbox_put(mbox);\n \treturn rc;\n }\n \n@@ -30,11 +32,14 @@ npc_mcam_free_counter(struct npc *npc, uint16_t ctr_id)\n \tstruct mbox *mbox = npc->mbox;\n \tint rc = -ENOSPC;\n \n-\treq = mbox_alloc_msg_npc_mcam_free_counter(mbox);\n+\treq = mbox_alloc_msg_npc_mcam_free_counter(mbox_get(mbox));\n \tif (req == NULL)\n-\t\treturn rc;\n+\t\tgoto exit;\n \treq->cntr = ctr_id;\n-\treturn mbox_process(mbox);\n+\trc = mbox_process(mbox);\n+exit:\n+\tmbox_put(mbox);\n+\treturn rc;\n }\n \n int\n@@ -45,14 +50,16 @@ npc_mcam_read_counter(struct npc *npc, uint32_t ctr_id, uint64_t *count)\n \tstruct mbox *mbox = npc->mbox;\n \tint rc = -ENOSPC;\n \n-\treq = mbox_alloc_msg_npc_mcam_counter_stats(mbox);\n+\treq = mbox_alloc_msg_npc_mcam_counter_stats(mbox_get(mbox));\n \tif (req == NULL)\n-\t\treturn rc;\n+\t\tgoto exit;\n \treq->cntr = ctr_id;\n \trc = mbox_process_msg(mbox, (void *)&rsp);\n \tif (rc)\n-\t\treturn rc;\n+\t\tgoto exit;\n \t*count = rsp->stat;\n+exit:\n+\tmbox_put(mbox);\n \treturn rc;\n }\n \n@@ -63,11 +70,14 @@ npc_mcam_clear_counter(struct npc *npc, uint32_t ctr_id)\n \tstruct mbox *mbox = npc->mbox;\n \tint rc = -ENOSPC;\n \n-\treq = mbox_alloc_msg_npc_mcam_clear_counter(mbox);\n+\treq = mbox_alloc_msg_npc_mcam_clear_counter(mbox_get(mbox));\n \tif (req == NULL)\n-\t\treturn rc;\n+\t\tgoto exit;\n \treq->cntr = ctr_id;\n-\treturn mbox_process(mbox);\n+\trc = mbox_process(mbox);\n+exit:\n+\tmbox_put(mbox);\n+\treturn rc;\n }\n \n int\n@@ -77,11 +87,14 @@ npc_mcam_free_entry(struct npc *npc, uint32_t entry)\n \tstruct mbox *mbox = npc->mbox;\n \tint rc = -ENOSPC;\n \n-\treq = mbox_alloc_msg_npc_mcam_free_entry(mbox);\n+\treq = mbox_alloc_msg_npc_mcam_free_entry(mbox_get(mbox));\n \tif (req == NULL)\n-\t\treturn rc;\n+\t\tgoto exit;\n \treq->entry = entry;\n-\treturn mbox_process(mbox);\n+\trc = mbox_process(mbox);\n+exit:\n+\tmbox_put(mbox);\n+\treturn rc;\n }\n \n int\n@@ -91,11 +104,14 @@ npc_mcam_free_all_entries(struct npc *npc)\n \tstruct mbox *mbox = npc->mbox;\n \tint rc = -ENOSPC;\n \n-\treq = mbox_alloc_msg_npc_mcam_free_entry(mbox);\n+\treq = mbox_alloc_msg_npc_mcam_free_entry(mbox_get(mbox));\n \tif (req == NULL)\n-\t\treturn rc;\n+\t\tgoto exit;\n \treq->all = 1;\n-\treturn mbox_process(mbox);\n+\trc = mbox_process(mbox);\n+exit:\n+\tmbox_put(mbox);\n+\treturn rc;\n }\n \n static int\n@@ -315,9 +331,9 @@ npc_mcam_alloc_entries(struct npc *npc, int ref_mcam, int *alloc_entry,\n \tint rc = -ENOSPC;\n \tint i;\n \n-\treq = mbox_alloc_msg_npc_mcam_alloc_entry(mbox);\n+\treq = mbox_alloc_msg_npc_mcam_alloc_entry(mbox_get(mbox));\n \tif (req == NULL)\n-\t\treturn rc;\n+\t\tgoto exit;\n \treq->contig = 0;\n \treq->count = req_count;\n \treq->priority = prio;\n@@ -325,11 +341,14 @@ npc_mcam_alloc_entries(struct npc *npc, int ref_mcam, int *alloc_entry,\n \n \trc = mbox_process_msg(mbox, (void *)&rsp);\n \tif (rc)\n-\t\treturn rc;\n+\t\tgoto exit;\n \tfor (i = 0; i < rsp->count; i++)\n \t\talloc_entry[i] = rsp->entry_list[i];\n \t*resp_count = rsp->count;\n-\treturn 0;\n+\trc = 0;\n+exit:\n+\tmbox_put(mbox);\n+\treturn rc;\n }\n \n int\n@@ -341,9 +360,9 @@ npc_mcam_alloc_entry(struct npc *npc, struct roc_npc_flow *mcam,\n \tstruct mbox *mbox = npc->mbox;\n \tint rc = -ENOSPC;\n \n-\treq = mbox_alloc_msg_npc_mcam_alloc_entry(mbox);\n+\treq = mbox_alloc_msg_npc_mcam_alloc_entry(mbox_get(mbox));\n \tif (req == NULL)\n-\t\treturn rc;\n+\t\tgoto exit;\n \treq->contig = 1;\n \treq->count = 1;\n \treq->priority = prio;\n@@ -351,19 +370,22 @@ npc_mcam_alloc_entry(struct npc *npc, struct roc_npc_flow *mcam,\n \n \trc = mbox_process_msg(mbox, (void *)&rsp);\n \tif (rc)\n-\t\treturn rc;\n+\t\tgoto exit;\n \tmemset(mcam, 0, sizeof(struct roc_npc_flow));\n \tmcam->mcam_id = rsp->entry;\n \tmcam->nix_intf = ref_mcam->nix_intf;\n \t*resp_count = rsp->count;\n-\treturn 0;\n+\trc = 0;\n+exit:\n+\tmbox_put(mbox);\n+\treturn rc;\n }\n \n int\n npc_mcam_ena_dis_entry(struct npc *npc, struct roc_npc_flow *mcam, bool enable)\n {\n \tstruct npc_mcam_ena_dis_entry_req *req;\n-\tstruct mbox *mbox = npc->mbox;\n+\tstruct mbox *mbox = mbox_get(npc->mbox);\n \tint rc = -ENOSPC;\n \n \tif (enable)\n@@ -372,10 +394,13 @@ npc_mcam_ena_dis_entry(struct npc *npc, struct roc_npc_flow *mcam, bool enable)\n \t\treq = mbox_alloc_msg_npc_mcam_dis_entry(mbox);\n \n \tif (req == NULL)\n-\t\treturn rc;\n+\t\tgoto exit;\n \treq->entry = mcam->mcam_id;\n \tmcam->enable = enable;\n-\treturn mbox_process(mbox);\n+\trc = mbox_process(mbox);\n+exit:\n+\tmbox_put(mbox);\n+\treturn rc;\n }\n \n int\n@@ -399,8 +424,9 @@ npc_mcam_write_entry(struct npc *npc, struct roc_npc_flow *mcam)\n \t\t\treturn rc;\n \t}\n \n-\treq = mbox_alloc_msg_npc_mcam_write_entry(mbox);\n+\treq = mbox_alloc_msg_npc_mcam_write_entry(mbox_get(mbox));\n \tif (req == NULL) {\n+\t\tmbox_put(mbox);\n \t\tif (mcam->use_ctr)\n \t\t\tnpc_mcam_free_counter(npc, ctr);\n \n@@ -420,7 +446,9 @@ npc_mcam_write_entry(struct npc *npc, struct roc_npc_flow *mcam)\n \t\treq->entry_data.kw[i] = mcam->mcam_data[i];\n \t\treq->entry_data.kw_mask[i] = mcam->mcam_mask[i];\n \t}\n-\treturn mbox_process_msg(mbox, (void *)&rsp);\n+\trc = mbox_process_msg(mbox, (void *)&rsp);\n+\tmbox_put(mbox);\n+\treturn rc;\n }\n \n static void\n@@ -483,7 +511,7 @@ int\n npc_mcam_fetch_kex_cfg(struct npc *npc)\n {\n \tstruct npc_get_kex_cfg_rsp *kex_rsp;\n-\tstruct mbox *mbox = npc->mbox;\n+\tstruct mbox *mbox = mbox_get(npc->mbox);\n \tint rc = 0;\n \n \tmbox_alloc_msg_npc_get_kex_cfg(mbox);\n@@ -499,6 +527,7 @@ npc_mcam_fetch_kex_cfg(struct npc *npc)\n \tnpc_mcam_process_mkex_cfg(npc, kex_rsp);\n \n done:\n+\tmbox_put(mbox);\n \treturn rc;\n }\n \n@@ -574,9 +603,11 @@ npc_mcam_alloc_and_write(struct npc *npc, struct roc_npc_flow *flow,\n \t\treturn NPC_ERR_MCAM_ALLOC;\n \t}\n \n-\treq = mbox_alloc_msg_npc_mcam_write_entry(mbox);\n-\tif (req == NULL)\n-\t\treturn -ENOSPC;\n+\treq = mbox_alloc_msg_npc_mcam_write_entry(mbox_get(mbox));\n+\tif (req == NULL) {\n+\t\trc = -ENOSPC;\n+\t\tgoto exit;\n+\t}\n \treq->set_cntr = flow->use_ctr;\n \treq->cntr = flow->ctr_id;\n \treq->entry = entry;\n@@ -641,13 +672,16 @@ npc_mcam_alloc_and_write(struct npc *npc, struct roc_npc_flow *flow,\n \n \trc = mbox_process_msg(mbox, (void *)&rsp);\n \tif (rc != 0)\n-\t\treturn rc;\n+\t\tgoto exit;\n \n \tflow->mcam_id = entry;\n \n \tif (flow->use_ctr)\n \t\tflow->ctr_id = ctr;\n-\treturn 0;\n+\trc = 0;\n+exit:\n+\tmbox_put(mbox);\n+\treturn rc;\n }\n \n static void\n@@ -729,6 +763,7 @@ npc_program_mcam(struct npc *npc, struct npc_parse_state *pst, bool mcam_alloc)\n \tstruct idev_cfg *idev;\n \tuint16_t layer_info;\n \tuint64_t lt, flags;\n+\tstruct mbox *mbox;\n \n \t/* Skip till Layer A data start */\n \twhile (bit < NPC_PARSE_KEX_S_LA_OFFSET) {\n@@ -800,12 +835,15 @@ npc_program_mcam(struct npc *npc, struct npc_parse_state *pst, bool mcam_alloc)\n \t\tskip_base_rule = true;\n \n \tif (pst->is_vf && pst->flow->nix_intf == NIX_INTF_RX && !skip_base_rule) {\n-\t\t(void)mbox_alloc_msg_npc_read_base_steer_rule(npc->mbox);\n-\t\trc = mbox_process_msg(npc->mbox, (void *)&base_rule_rsp);\n+\t\tmbox = mbox_get(npc->mbox);\n+\t\t(void)mbox_alloc_msg_npc_read_base_steer_rule(mbox);\n+\t\trc = mbox_process_msg(mbox, (void *)&base_rule_rsp);\n \t\tif (rc) {\n+\t\t\tmbox_put(mbox);\n \t\t\tplt_err(\"Failed to fetch VF's base MCAM entry\");\n \t\t\treturn rc;\n \t\t}\n+\t\tmbox_put(mbox);\n \t\tbase_entry = &base_rule_rsp->entry_data;\n \t\tfor (idx = 0; idx < ROC_NPC_MAX_MCAM_WIDTH_DWORDS; idx++) {\n \t\t\tpst->flow->mcam_data[idx] |= base_entry->kw[idx];\ndiff --git a/drivers/common/cnxk/roc_npc_mcam_dump.c b/drivers/common/cnxk/roc_npc_mcam_dump.c\nindex fe57811a84..2aaa2ac671 100644\n--- a/drivers/common/cnxk/roc_npc_mcam_dump.c\n+++ b/drivers/common/cnxk/roc_npc_mcam_dump.c\n@@ -620,15 +620,17 @@ roc_npc_flow_mcam_dump(FILE *file, struct roc_npc *roc_npc,\n \t\tfprintf(file, \"\\tDW%d_Mask:%016lX\\n\", i, flow->mcam_mask[i]);\n \t}\n \n-\tmcam_read_req = mbox_alloc_msg_npc_mcam_read_entry(npc->mbox);\n+\tmcam_read_req = mbox_alloc_msg_npc_mcam_read_entry(mbox_get(npc->mbox));\n \tif (mcam_read_req == NULL) {\n \t\tplt_err(\"Failed to alloc msg\");\n+\t\tmbox_put(npc->mbox);\n \t\treturn;\n \t}\n \n \tmcam_read_req->entry = flow->mcam_id;\n \trc = mbox_process_msg(npc->mbox, (void *)&mcam_read_rsp);\n \tif (rc) {\n+\t\tmbox_put(npc->mbox);\n \t\tplt_err(\"Failed to fetch MCAM entry:%d\", flow->mcam_id);\n \t\treturn;\n \t}\n@@ -643,4 +645,5 @@ roc_npc_flow_mcam_dump(FILE *file, struct roc_npc *roc_npc,\n \t}\n \n \tfprintf(file, \"\\n\");\n+\tmbox_put(npc->mbox);\n }\ndiff --git a/drivers/common/cnxk/roc_npc_utils.c b/drivers/common/cnxk/roc_npc_utils.c\nindex 8bdabc116d..a9df62cee6 100644\n--- a/drivers/common/cnxk/roc_npc_utils.c\n+++ b/drivers/common/cnxk/roc_npc_utils.c\n@@ -269,11 +269,14 @@ npc_mcam_init(struct npc *npc, struct roc_npc_flow *flow, int mcam_id)\n {\n \tstruct npc_mcam_write_entry_req *req;\n \tstruct npc_mcam_write_entry_rsq *rsp;\n+\tstruct mbox *mbox = mbox_get(npc->mbox);\n \tint rc = 0, idx;\n \n-\treq = mbox_alloc_msg_npc_mcam_write_entry(npc->mbox);\n-\tif (req == NULL)\n-\t\treturn -ENOSPC;\n+\treq = mbox_alloc_msg_npc_mcam_write_entry(mbox);\n+\tif (req == NULL) {\n+\t\trc = -ENOSPC;\n+\t\tgoto exit;\n+\t}\n \treq->set_cntr = 0;\n \treq->cntr = 0;\n \treq->entry = mcam_id;\n@@ -299,12 +302,15 @@ npc_mcam_init(struct npc *npc, struct roc_npc_flow *flow, int mcam_id)\n \t\treq->entry_data.kw_mask[0] |= ((uint64_t)0xffff << 32);\n \t}\n \n-\trc = mbox_process_msg(npc->mbox, (void *)&rsp);\n+\trc = mbox_process_msg(mbox, (void *)&rsp);\n \tif (rc != 0) {\n \t\tplt_err(\"npc: mcam initialisation write failed\");\n-\t\treturn rc;\n+\t\tgoto exit;\n \t}\n-\treturn 0;\n+\trc = 0;\n+exit:\n+\tmbox_put(mbox);\n+\treturn rc;\n }\n \n int\n@@ -317,18 +323,21 @@ npc_mcam_move(struct mbox *mbox, uint16_t old_ent, uint16_t new_ent)\n \t/* Old entry is disabled & it's contents are moved to new_entry,\n \t * new entry is enabled finally.\n \t */\n-\treq = mbox_alloc_msg_npc_mcam_shift_entry(mbox);\n+\treq = mbox_alloc_msg_npc_mcam_shift_entry(mbox_get(mbox));\n \tif (req == NULL)\n-\t\treturn rc;\n+\t\tgoto exit;\n \treq->curr_entry[0] = old_ent;\n \treq->new_entry[0] = new_ent;\n \treq->shift_count = 1;\n \n \trc = mbox_process_msg(mbox, (void *)&rsp);\n \tif (rc)\n-\t\treturn rc;\n+\t\tgoto exit;\n \n-\treturn 0;\n+\trc = 0;\n+exit:\n+\tmbox_put(mbox);\n+\treturn rc;\n }\n \n enum SHIFT_DIR {\n@@ -567,9 +576,9 @@ npc_allocate_mcam_entry(struct mbox *mbox, int prio,\n \tstruct npc_mcam_alloc_entry_rsp *rsp;\n \tint rc = -ENOSPC;\n \n-\treq = mbox_alloc_msg_npc_mcam_alloc_entry(mbox);\n+\treq = mbox_alloc_msg_npc_mcam_alloc_entry(mbox_get(mbox));\n \tif (req == NULL)\n-\t\treturn rc;\n+\t\tgoto exit;\n \treq->contig = 1;\n \treq->count = 1;\n \treq->priority = prio;\n@@ -577,14 +586,19 @@ npc_allocate_mcam_entry(struct mbox *mbox, int prio,\n \n \trc = mbox_process_msg(mbox, (void *)&rsp_cmd);\n \tif (rc)\n-\t\treturn rc;\n+\t\tgoto exit;\n \n-\tif (!rsp_cmd->count)\n-\t\treturn -ENOSPC;\n+\tif (!rsp_cmd->count) {\n+\t\trc = -ENOSPC;\n+\t\tgoto exit;\n+\t}\n \n \tmbox_memcpy(rsp_local, rsp_cmd, sizeof(*rsp));\n \n-\treturn 0;\n+\trc = 0;\n+exit:\n+\tmbox_put(mbox);\n+\treturn rc;\n }\n \n static void\ndiff --git a/drivers/common/cnxk/roc_sso.c b/drivers/common/cnxk/roc_sso.c\nindex 6989884373..9920d0c604 100644\n--- a/drivers/common/cnxk/roc_sso.c\n+++ b/drivers/common/cnxk/roc_sso.c\n@@ -12,67 +12,79 @@ int\n sso_lf_alloc(struct dev *dev, enum sso_lf_type lf_type, uint16_t nb_lf,\n \t     void **rsp)\n {\n+\tstruct mbox *mbox = mbox_get(dev->mbox);\n \tint rc = -ENOSPC;\n \n \tswitch (lf_type) {\n \tcase SSO_LF_TYPE_HWS: {\n \t\tstruct ssow_lf_alloc_req *req;\n \n-\t\treq = mbox_alloc_msg_ssow_lf_alloc(dev->mbox);\n+\t\treq = mbox_alloc_msg_ssow_lf_alloc(mbox);\n \t\tif (req == NULL)\n-\t\t\treturn rc;\n+\t\t\tgoto exit;\n \t\treq->hws = nb_lf;\n \t} break;\n \tcase SSO_LF_TYPE_HWGRP: {\n \t\tstruct sso_lf_alloc_req *req;\n \n-\t\treq = mbox_alloc_msg_sso_lf_alloc(dev->mbox);\n+\t\treq = mbox_alloc_msg_sso_lf_alloc(mbox);\n \t\tif (req == NULL)\n-\t\t\treturn rc;\n+\t\t\tgoto exit;\n \t\treq->hwgrps = nb_lf;\n \t} break;\n \tdefault:\n \t\tbreak;\n \t}\n \n-\trc = mbox_process_msg(dev->mbox, rsp);\n-\tif (rc)\n-\t\treturn -EIO;\n+\trc = mbox_process_msg(mbox, rsp);\n+\tif (rc) {\n+\t\trc = -EIO;\n+\t\tgoto exit;\n+\t}\n \n-\treturn 0;\n+\trc = 0;\n+exit:\n+\tmbox_put(mbox);\n+\treturn rc;\n }\n \n int\n sso_lf_free(struct dev *dev, enum sso_lf_type lf_type, uint16_t nb_lf)\n {\n+\tstruct mbox *mbox = mbox_get(dev->mbox);\n \tint rc = -ENOSPC;\n \n \tswitch (lf_type) {\n \tcase SSO_LF_TYPE_HWS: {\n \t\tstruct ssow_lf_free_req *req;\n \n-\t\treq = mbox_alloc_msg_ssow_lf_free(dev->mbox);\n+\t\treq = mbox_alloc_msg_ssow_lf_free(mbox);\n \t\tif (req == NULL)\n-\t\t\treturn rc;\n+\t\t\tgoto exit;\n \t\treq->hws = nb_lf;\n \t} break;\n \tcase SSO_LF_TYPE_HWGRP: {\n \t\tstruct sso_lf_free_req *req;\n \n-\t\treq = mbox_alloc_msg_sso_lf_free(dev->mbox);\n+\t\treq = mbox_alloc_msg_sso_lf_free(mbox);\n \t\tif (req == NULL)\n-\t\t\treturn rc;\n+\t\t\tgoto exit;\n \t\treq->hwgrps = nb_lf;\n \t} break;\n \tdefault:\n \t\tbreak;\n \t}\n \n-\trc = mbox_process(dev->mbox);\n-\tif (rc)\n-\t\treturn -EIO;\n+\trc = mbox_process(mbox);\n+\tif (rc) {\n+\t\trc = -EIO;\n+\t\tgoto exit;\n+\t}\n \n-\treturn 0;\n+\trc = 0;\n+exit:\n+\tmbox_put(mbox);\n+\treturn rc;\n }\n \n static int\n@@ -80,12 +92,13 @@ sso_rsrc_attach(struct roc_sso *roc_sso, enum sso_lf_type lf_type,\n \t\tuint16_t nb_lf)\n {\n \tstruct dev *dev = &roc_sso_to_sso_priv(roc_sso)->dev;\n+\tstruct mbox *mbox = mbox_get(dev->mbox);\n \tstruct rsrc_attach_req *req;\n \tint rc = -ENOSPC;\n \n-\treq = mbox_alloc_msg_attach_resources(dev->mbox);\n+\treq = mbox_alloc_msg_attach_resources(mbox);\n \tif (req == NULL)\n-\t\treturn rc;\n+\t\tgoto exit;\n \tswitch (lf_type) {\n \tcase SSO_LF_TYPE_HWS:\n \t\treq->ssow = nb_lf;\n@@ -94,14 +107,20 @@ sso_rsrc_attach(struct roc_sso *roc_sso, enum sso_lf_type lf_type,\n \t\treq->sso = nb_lf;\n \t\tbreak;\n \tdefault:\n-\t\treturn SSO_ERR_PARAM;\n+\t\trc = SSO_ERR_PARAM;\n+\t\tgoto exit;\n \t}\n \n \treq->modify = true;\n-\tif (mbox_process(dev->mbox))\n-\t\treturn -EIO;\n+\tif (mbox_process(mbox)) {\n+\t\trc = -EIO;\n+\t\tgoto exit;\n+\t}\n \n-\treturn 0;\n+\trc = 0;\n+exit:\n+\tmbox_put(mbox);\n+\treturn rc;\n }\n \n static int\n@@ -109,11 +128,12 @@ sso_rsrc_detach(struct roc_sso *roc_sso, enum sso_lf_type lf_type)\n {\n \tstruct dev *dev = &roc_sso_to_sso_priv(roc_sso)->dev;\n \tstruct rsrc_detach_req *req;\n+\tstruct mbox *mbox = mbox_get(dev->mbox);\n \tint rc = -ENOSPC;\n \n-\treq = mbox_alloc_msg_detach_resources(dev->mbox);\n+\treq = mbox_alloc_msg_detach_resources(mbox);\n \tif (req == NULL)\n-\t\treturn rc;\n+\t\tgoto exit;\n \tswitch (lf_type) {\n \tcase SSO_LF_TYPE_HWS:\n \t\treq->ssow = true;\n@@ -122,14 +142,20 @@ sso_rsrc_detach(struct roc_sso *roc_sso, enum sso_lf_type lf_type)\n \t\treq->sso = true;\n \t\tbreak;\n \tdefault:\n-\t\treturn SSO_ERR_PARAM;\n+\t\trc = SSO_ERR_PARAM;\n+\t\tgoto exit;\n \t}\n \n \treq->partial = true;\n-\tif (mbox_process(dev->mbox))\n-\t\treturn -EIO;\n+\tif (mbox_process(mbox)) {\n+\t\trc = -EIO;\n+\t\tgoto exit;\n+\t}\n \n-\treturn 0;\n+\trc = 0;\n+exit:\n+\tmbox_put(mbox);\n+\treturn rc;\n }\n \n static int\n@@ -137,19 +163,24 @@ sso_rsrc_get(struct roc_sso *roc_sso)\n {\n \tstruct dev *dev = &roc_sso_to_sso_priv(roc_sso)->dev;\n \tstruct free_rsrcs_rsp *rsrc_cnt;\n+\tstruct mbox *mbox = mbox_get(dev->mbox);\n \tint rc;\n \n-\tmbox_alloc_msg_free_rsrc_cnt(dev->mbox);\n-\trc = mbox_process_msg(dev->mbox, (void **)&rsrc_cnt);\n+\tmbox_alloc_msg_free_rsrc_cnt(mbox);\n+\trc = mbox_process_msg(mbox, (void **)&rsrc_cnt);\n \tif (rc) {\n \t\tplt_err(\"Failed to get free resource count\\n\");\n-\t\treturn -EIO;\n+\t\trc = -EIO;\n+\t\tgoto exit;\n \t}\n \n \troc_sso->max_hwgrp = rsrc_cnt->sso;\n \troc_sso->max_hws = rsrc_cnt->ssow;\n \n-\treturn 0;\n+\trc = 0;\n+exit:\n+\tmbox_put(mbox);\n+\treturn rc;\n }\n \n void\n@@ -195,17 +226,22 @@ sso_msix_fill(struct roc_sso *roc_sso, uint16_t nb_hws, uint16_t nb_hwgrp)\n \tstruct dev *dev = &sso->dev;\n \tint i, rc;\n \n-\tmbox_alloc_msg_msix_offset(dev->mbox);\n+\tmbox_alloc_msg_msix_offset(mbox_get(dev->mbox));\n \trc = mbox_process_msg(dev->mbox, (void **)&rsp);\n-\tif (rc)\n-\t\treturn -EIO;\n+\tif (rc) {\n+\t\trc = -EIO;\n+\t\tgoto exit;\n+\t}\n \n \tfor (i = 0; i < nb_hws; i++)\n \t\tsso->hws_msix_offset[i] = rsp->ssow_msixoff[i];\n \tfor (i = 0; i < nb_hwgrp; i++)\n \t\tsso->hwgrp_msix_offset[i] = rsp->sso_msixoff[i];\n \n-\treturn 0;\n+\trc = 0;\n+exit:\n+\tmbox_put(dev->mbox);\n+\treturn rc;\n }\n \n /* Public Functions. */\n@@ -288,26 +324,28 @@ roc_sso_hws_stats_get(struct roc_sso *roc_sso, uint8_t hws,\n \tstruct sso *sso = roc_sso_to_sso_priv(roc_sso);\n \tstruct sso_hws_stats *req_rsp;\n \tstruct dev *dev = &sso->dev;\n+\tstruct mbox *mbox;\n \tint rc;\n \n \tplt_spinlock_lock(&sso->mbox_lock);\n+\tmbox = mbox_get(dev->mbox);\n \treq_rsp = (struct sso_hws_stats *)mbox_alloc_msg_sso_hws_get_stats(\n-\t\tdev->mbox);\n+\t\tmbox);\n \tif (req_rsp == NULL) {\n-\t\trc = mbox_process(dev->mbox);\n+\t\trc = mbox_process(mbox);\n \t\tif (rc) {\n \t\t\trc = -EIO;\n \t\t\tgoto fail;\n \t\t}\n \t\treq_rsp = (struct sso_hws_stats *)\n-\t\t\tmbox_alloc_msg_sso_hws_get_stats(dev->mbox);\n+\t\t\tmbox_alloc_msg_sso_hws_get_stats(mbox);\n \t\tif (req_rsp == NULL) {\n \t\t\trc = -ENOSPC;\n \t\t\tgoto fail;\n \t\t}\n \t}\n \treq_rsp->hws = hws;\n-\trc = mbox_process_msg(dev->mbox, (void **)&req_rsp);\n+\trc = mbox_process_msg(mbox, (void **)&req_rsp);\n \tif (rc) {\n \t\trc = -EIO;\n \t\tgoto fail;\n@@ -315,6 +353,7 @@ roc_sso_hws_stats_get(struct roc_sso *roc_sso, uint8_t hws,\n \n \tstats->arbitration = req_rsp->arbitration;\n fail:\n+\tmbox_put(mbox);\n \tplt_spinlock_unlock(&sso->mbox_lock);\n \treturn rc;\n }\n@@ -326,26 +365,28 @@ roc_sso_hwgrp_stats_get(struct roc_sso *roc_sso, uint8_t hwgrp,\n \tstruct sso *sso = roc_sso_to_sso_priv(roc_sso);\n \tstruct sso_grp_stats *req_rsp;\n \tstruct dev *dev = &sso->dev;\n+\tstruct mbox *mbox;\n \tint rc;\n \n \tplt_spinlock_lock(&sso->mbox_lock);\n+\tmbox = mbox_get(dev->mbox);\n \treq_rsp = (struct sso_grp_stats *)mbox_alloc_msg_sso_grp_get_stats(\n-\t\tdev->mbox);\n+\t\tmbox);\n \tif (req_rsp == NULL) {\n-\t\trc = mbox_process(dev->mbox);\n+\t\trc = mbox_process(mbox);\n \t\tif (rc) {\n \t\t\trc = -EIO;\n \t\t\tgoto fail;\n \t\t}\n \t\treq_rsp = (struct sso_grp_stats *)\n-\t\t\tmbox_alloc_msg_sso_grp_get_stats(dev->mbox);\n+\t\t\tmbox_alloc_msg_sso_grp_get_stats(mbox);\n \t\tif (req_rsp == NULL) {\n \t\t\trc = -ENOSPC;\n \t\t\tgoto fail;\n \t\t}\n \t}\n \treq_rsp->grp = hwgrp;\n-\trc = mbox_process_msg(dev->mbox, (void **)&req_rsp);\n+\trc = mbox_process_msg(mbox, (void **)&req_rsp);\n \tif (rc) {\n \t\trc = -EIO;\n \t\tgoto fail;\n@@ -361,6 +402,7 @@ roc_sso_hwgrp_stats_get(struct roc_sso *roc_sso, uint8_t hwgrp,\n \tstats->ws_pc = req_rsp->ws_pc;\n \n fail:\n+\tmbox_put(mbox);\n \tplt_spinlock_unlock(&sso->mbox_lock);\n \treturn rc;\n }\n@@ -382,22 +424,24 @@ roc_sso_hwgrp_qos_config(struct roc_sso *roc_sso, struct roc_sso_hwgrp_qos *qos,\n \tstruct sso *sso = roc_sso_to_sso_priv(roc_sso);\n \tstruct dev *dev = &sso->dev;\n \tstruct sso_grp_qos_cfg *req;\n+\tstruct mbox *mbox;\n \tint i, rc;\n \n \tplt_spinlock_lock(&sso->mbox_lock);\n+\tmbox = mbox_get(dev->mbox);\n \tfor (i = 0; i < nb_qos; i++) {\n \t\tuint8_t iaq_prcnt = qos[i].iaq_prcnt;\n \t\tuint8_t taq_prcnt = qos[i].taq_prcnt;\n \n-\t\treq = mbox_alloc_msg_sso_grp_qos_config(dev->mbox);\n+\t\treq = mbox_alloc_msg_sso_grp_qos_config(mbox);\n \t\tif (req == NULL) {\n-\t\t\trc = mbox_process(dev->mbox);\n+\t\t\trc = mbox_process(mbox);\n \t\t\tif (rc) {\n \t\t\t\trc = -EIO;\n \t\t\t\tgoto fail;\n \t\t\t}\n \n-\t\t\treq = mbox_alloc_msg_sso_grp_qos_config(dev->mbox);\n+\t\t\treq = mbox_alloc_msg_sso_grp_qos_config(mbox);\n \t\t\tif (req == NULL) {\n \t\t\t\trc = -ENOSPC;\n \t\t\t\tgoto fail;\n@@ -412,10 +456,11 @@ roc_sso_hwgrp_qos_config(struct roc_sso *roc_sso, struct roc_sso_hwgrp_qos *qos,\n \t\t\t       100;\n \t}\n \n-\trc = mbox_process(dev->mbox);\n+\trc = mbox_process(mbox);\n \tif (rc)\n \t\trc = -EIO;\n fail:\n+\tmbox_put(mbox);\n \tplt_spinlock_unlock(&sso->mbox_lock);\n \treturn rc;\n }\n@@ -565,19 +610,25 @@ int\n sso_hwgrp_alloc_xaq(struct dev *dev, uint32_t npa_aura_id, uint16_t hwgrps)\n {\n \tstruct sso_hw_setconfig *req;\n+\tstruct mbox *mbox = mbox_get(dev->mbox);\n \tint rc = -ENOSPC;\n \n-\treq = mbox_alloc_msg_sso_hw_setconfig(dev->mbox);\n+\treq = mbox_alloc_msg_sso_hw_setconfig(mbox);\n \tif (req == NULL)\n-\t\treturn rc;\n+\t\tgoto exit;\n \treq->npa_pf_func = idev_npa_pffunc_get();\n \treq->npa_aura_id = npa_aura_id;\n \treq->hwgrps = hwgrps;\n \n-\tif (mbox_process(dev->mbox))\n-\t\treturn -EIO;\n+\tif (mbox_process(dev->mbox)) {\n+\t\trc = -EIO;\n+\t\tgoto exit;\n+\t}\n \n-\treturn 0;\n+\trc = 0;\n+exit:\n+\tmbox_put(mbox);\n+\treturn rc;\n }\n \n int\n@@ -598,16 +649,25 @@ int\n sso_hwgrp_release_xaq(struct dev *dev, uint16_t hwgrps)\n {\n \tstruct sso_hw_xaq_release *req;\n+\tstruct mbox *mbox = mbox_get(dev->mbox);\n+\tint rc;\n \n-\treq = mbox_alloc_msg_sso_hw_release_xaq_aura(dev->mbox);\n-\tif (req == NULL)\n-\t\treturn -EINVAL;\n+\treq = mbox_alloc_msg_sso_hw_release_xaq_aura(mbox);\n+\tif (req == NULL) {\n+\t\trc =  -EINVAL;\n+\t\tgoto exit;\n+\t}\n \treq->hwgrps = hwgrps;\n \n-\tif (mbox_process(dev->mbox))\n-\t\treturn -EIO;\n+\tif (mbox_process(mbox)) {\n+\t\trc = -EIO;\n+\t\tgoto exit;\n+\t}\n \n-\treturn 0;\n+\trc = 0;\n+exit:\n+\tmbox_put(mbox);\n+\treturn rc;\n }\n \n int\n@@ -630,10 +690,12 @@ roc_sso_hwgrp_set_priority(struct roc_sso *roc_sso, uint16_t hwgrp,\n \tstruct sso *sso = roc_sso_to_sso_priv(roc_sso);\n \tstruct dev *dev = &sso->dev;\n \tstruct sso_grp_priority *req;\n+\tstruct mbox *mbox;\n \tint rc = -ENOSPC;\n \n \tplt_spinlock_lock(&sso->mbox_lock);\n-\treq = mbox_alloc_msg_sso_grp_set_priority(dev->mbox);\n+\tmbox = mbox_get(dev->mbox);\n+\treq = mbox_alloc_msg_sso_grp_set_priority(mbox);\n \tif (req == NULL)\n \t\tgoto fail;\n \treq->grp = hwgrp;\n@@ -641,17 +703,19 @@ roc_sso_hwgrp_set_priority(struct roc_sso *roc_sso, uint16_t hwgrp,\n \treq->affinity = affinity;\n \treq->priority = priority;\n \n-\trc = mbox_process(dev->mbox);\n+\trc = mbox_process(mbox);\n \tif (rc) {\n \t\trc = -EIO;\n \t\tgoto fail;\n \t}\n+\tmbox_put(mbox);\n \tplt_spinlock_unlock(&sso->mbox_lock);\n \tplt_sso_dbg(\"HWGRP %d weight %d affinity %d priority %d\", hwgrp, weight,\n \t\t    affinity, priority);\n \n \treturn 0;\n fail:\n+\tmbox_put(mbox);\n \tplt_spinlock_unlock(&sso->mbox_lock);\n \treturn rc;\n }\ndiff --git a/drivers/common/cnxk/roc_tim.c b/drivers/common/cnxk/roc_tim.c\nindex 0f9209937b..90ce72cfa0 100644\n--- a/drivers/common/cnxk/roc_tim.c\n+++ b/drivers/common/cnxk/roc_tim.c\n@@ -12,17 +12,23 @@ tim_fill_msix(struct roc_tim *roc_tim, uint16_t nb_ring)\n \tstruct tim *tim = roc_tim_to_tim_priv(roc_tim);\n \tstruct dev *dev = &sso->dev;\n \tstruct msix_offset_rsp *rsp;\n+\tstruct mbox *mbox = mbox_get(dev->mbox);\n \tint i, rc;\n \n-\tmbox_alloc_msg_msix_offset(dev->mbox);\n-\trc = mbox_process_msg(dev->mbox, (void **)&rsp);\n-\tif (rc)\n-\t\treturn -EIO;\n+\tmbox_alloc_msg_msix_offset(mbox);\n+\trc = mbox_process_msg(mbox, (void **)&rsp);\n+\tif (rc) {\n+\t\trc = -EIO;\n+\t\tgoto exit;\n+\t}\n \n \tfor (i = 0; i < nb_ring; i++)\n \t\ttim->tim_msix_offsets[i] = rsp->timlf_msixoff[i];\n \n-\treturn 0;\n+\trc = 0;\n+exit:\n+\tmbox_put(mbox);\n+\treturn rc;\n }\n \n static void\n@@ -91,12 +97,12 @@ roc_tim_lf_enable(struct roc_tim *roc_tim, uint8_t ring_id, uint64_t *start_tsc,\n {\n \tstruct sso *sso = roc_sso_to_sso_priv(roc_tim->roc_sso);\n \tstruct dev *dev = &sso->dev;\n+\tstruct mbox *mbox = mbox_get(dev->mbox);\n \tstruct tim_enable_rsp *rsp;\n \tstruct tim_ring_req *req;\n \tint rc = -ENOSPC;\n \n-\tplt_spinlock_lock(&sso->mbox_lock);\n-\treq = mbox_alloc_msg_tim_enable_ring(dev->mbox);\n+\treq = mbox_alloc_msg_tim_enable_ring(mbox);\n \tif (req == NULL)\n \t\tgoto fail;\n \treq->ring = ring_id;\n@@ -114,7 +120,7 @@ roc_tim_lf_enable(struct roc_tim *roc_tim, uint8_t ring_id, uint64_t *start_tsc,\n \t\t*start_tsc = rsp->timestarted;\n \n fail:\n-\tplt_spinlock_unlock(&sso->mbox_lock);\n+\tmbox_put(mbox);\n \treturn rc;\n }\n \n@@ -123,11 +129,11 @@ roc_tim_lf_disable(struct roc_tim *roc_tim, uint8_t ring_id)\n {\n \tstruct sso *sso = roc_sso_to_sso_priv(roc_tim->roc_sso);\n \tstruct dev *dev = &sso->dev;\n+\tstruct mbox *mbox = mbox_get(dev->mbox);\n \tstruct tim_ring_req *req;\n \tint rc = -ENOSPC;\n \n-\tplt_spinlock_lock(&sso->mbox_lock);\n-\treq = mbox_alloc_msg_tim_disable_ring(dev->mbox);\n+\treq = mbox_alloc_msg_tim_disable_ring(mbox);\n \tif (req == NULL)\n \t\tgoto fail;\n \treq->ring = ring_id;\n@@ -139,7 +145,7 @@ roc_tim_lf_disable(struct roc_tim *roc_tim, uint8_t ring_id)\n \t}\n \n fail:\n-\tplt_spinlock_unlock(&sso->mbox_lock);\n+\tmbox_put(mbox);\n \treturn rc;\n }\n \n@@ -159,11 +165,11 @@ roc_tim_lf_config(struct roc_tim *roc_tim, uint8_t ring_id,\n {\n \tstruct sso *sso = roc_sso_to_sso_priv(roc_tim->roc_sso);\n \tstruct dev *dev = &sso->dev;\n+\tstruct mbox *mbox = mbox_get(dev->mbox);\n \tstruct tim_config_req *req;\n \tint rc = -ENOSPC;\n \n-\tplt_spinlock_lock(&sso->mbox_lock);\n-\treq = mbox_alloc_msg_tim_config_ring(dev->mbox);\n+\treq = mbox_alloc_msg_tim_config_ring(mbox);\n \tif (req == NULL)\n \t\tgoto fail;\n \treq->ring = ring_id;\n@@ -178,14 +184,14 @@ roc_tim_lf_config(struct roc_tim *roc_tim, uint8_t ring_id,\n \treq->clockfreq = clockfreq;\n \treq->gpioedge = TIM_GPIO_LTOH_TRANS;\n \n-\trc = mbox_process(dev->mbox);\n+\trc = mbox_process(mbox);\n \tif (rc) {\n \t\ttim_err_desc(rc);\n \t\trc = -EIO;\n \t}\n \n fail:\n-\tplt_spinlock_unlock(&sso->mbox_lock);\n+\tmbox_put(mbox);\n \treturn rc;\n }\n \n@@ -196,12 +202,12 @@ roc_tim_lf_interval(struct roc_tim *roc_tim, enum roc_tim_clk_src clk_src,\n {\n \tstruct sso *sso = roc_sso_to_sso_priv(roc_tim->roc_sso);\n \tstruct dev *dev = &sso->dev;\n+\tstruct mbox *mbox = mbox_get(dev->mbox);\n \tstruct tim_intvl_req *req;\n \tstruct tim_intvl_rsp *rsp;\n \tint rc = -ENOSPC;\n \n-\tplt_spinlock_lock(&sso->mbox_lock);\n-\treq = mbox_alloc_msg_tim_get_min_intvl(dev->mbox);\n+\treq = mbox_alloc_msg_tim_get_min_intvl(mbox);\n \tif (req == NULL)\n \t\tgoto fail;\n \n@@ -218,7 +224,7 @@ roc_tim_lf_interval(struct roc_tim *roc_tim, enum roc_tim_clk_src clk_src,\n \t*interval = rsp->intvl_cyc;\n \n fail:\n-\tplt_spinlock_unlock(&sso->mbox_lock);\n+\tmbox_put(mbox);\n \treturn rc;\n }\n \n@@ -231,17 +237,17 @@ roc_tim_lf_alloc(struct roc_tim *roc_tim, uint8_t ring_id, uint64_t *clk)\n \tstruct tim_lf_alloc_req *req;\n \tstruct tim_lf_alloc_rsp *rsp;\n \tstruct dev *dev = &sso->dev;\n+\tstruct mbox *mbox = mbox_get(dev->mbox);\n \tint rc = -ENOSPC;\n \n-\tplt_spinlock_lock(&sso->mbox_lock);\n-\treq = mbox_alloc_msg_tim_lf_alloc(dev->mbox);\n+\treq = mbox_alloc_msg_tim_lf_alloc(mbox);\n \tif (req == NULL)\n \t\tgoto fail;\n \treq->npa_pf_func = idev_npa_pffunc_get();\n \treq->sso_pf_func = idev_sso_pffunc_get();\n \treq->ring = ring_id;\n \n-\trc = mbox_process_msg(dev->mbox, (void **)&rsp);\n+\trc = mbox_process_msg(mbox, (void **)&rsp);\n \tif (rc) {\n \t\ttim_err_desc(rc);\n \t\trc = -EIO;\n@@ -255,19 +261,19 @@ roc_tim_lf_alloc(struct roc_tim *roc_tim, uint8_t ring_id, uint64_t *clk)\n \t\t\t\t   tim->tim_msix_offsets[ring_id]);\n \tif (rc < 0) {\n \t\tplt_tim_dbg(\"Failed to register Ring[%d] IRQ\", ring_id);\n-\t\tfree_req = mbox_alloc_msg_tim_lf_free(dev->mbox);\n+\t\tfree_req = mbox_alloc_msg_tim_lf_free(mbox);\n \t\tif (free_req == NULL) {\n \t\t\trc = -ENOSPC;\n \t\t\tgoto fail;\n \t\t}\n \t\tfree_req->ring = ring_id;\n-\t\trc = mbox_process(dev->mbox);\n+\t\trc = mbox_process(mbox);\n \t\tif (rc)\n \t\t\trc = -EIO;\n \t}\n \n fail:\n-\tplt_spinlock_unlock(&sso->mbox_lock);\n+\tmbox_put(dev->mbox);\n \treturn rc;\n }\n \n@@ -283,8 +289,7 @@ roc_tim_lf_free(struct roc_tim *roc_tim, uint8_t ring_id)\n \ttim_unregister_irq_priv(roc_tim, sso->pci_dev->intr_handle, ring_id,\n \t\t\t\ttim->tim_msix_offsets[ring_id]);\n \n-\tplt_spinlock_lock(&sso->mbox_lock);\n-\treq = mbox_alloc_msg_tim_lf_free(dev->mbox);\n+\treq = mbox_alloc_msg_tim_lf_free(mbox_get(dev->mbox));\n \tif (req == NULL)\n \t\tgoto fail;\n \treq->ring = ring_id;\n@@ -293,11 +298,13 @@ roc_tim_lf_free(struct roc_tim *roc_tim, uint8_t ring_id)\n \tif (rc < 0) {\n \t\ttim_err_desc(rc);\n \t\trc = -EIO;\n+\t\tgoto fail;\n \t}\n+\trc = 0;\n \n fail:\n-\tplt_spinlock_unlock(&sso->mbox_lock);\n-\treturn 0;\n+\tmbox_put(dev->mbox);\n+\treturn rc;\n }\n \n int\n@@ -318,8 +325,7 @@ roc_tim_init(struct roc_tim *roc_tim)\n \tdev = &sso->dev;\n \tPLT_STATIC_ASSERT(sizeof(struct tim) <= TIM_MEM_SZ);\n \tnb_lfs = roc_tim->nb_lfs;\n-\tplt_spinlock_lock(&sso->mbox_lock);\n-\tmbox_alloc_msg_free_rsrc_cnt(dev->mbox);\n+\tmbox_alloc_msg_free_rsrc_cnt(mbox_get(dev->mbox));\n \trc = mbox_process_msg(dev->mbox, (void *)&free_rsrc);\n \tif (rc) {\n \t\tplt_err(\"Unable to get free rsrc count.\");\n@@ -350,11 +356,12 @@ roc_tim_init(struct roc_tim *roc_tim)\n \t\tgoto fail;\n \t}\n \n+\tmbox_put(dev->mbox);\n \trc = tim_fill_msix(roc_tim, nb_lfs);\n \tif (rc < 0) {\n \t\tplt_err(\"Unable to get TIM MSIX vectors\");\n \n-\t\tdetach_req = mbox_alloc_msg_detach_resources(dev->mbox);\n+\t\tdetach_req = mbox_alloc_msg_detach_resources(mbox_get(dev->mbox));\n \t\tif (detach_req == NULL) {\n \t\t\tnb_lfs = 0;\n \t\t\tgoto fail;\n@@ -363,10 +370,13 @@ roc_tim_init(struct roc_tim *roc_tim)\n \t\tdetach_req->timlfs = true;\n \t\tmbox_process(dev->mbox);\n \t\tnb_lfs = 0;\n+\t} else {\n+\t\tgoto done;\n \t}\n \n fail:\n-\tplt_spinlock_unlock(&sso->mbox_lock);\n+\tmbox_put(dev->mbox);\n+done:\n \treturn nb_lfs;\n }\n \n@@ -376,13 +386,13 @@ roc_tim_fini(struct roc_tim *roc_tim)\n \tstruct sso *sso = roc_sso_to_sso_priv(roc_tim->roc_sso);\n \tstruct rsrc_detach_req *detach_req;\n \tstruct dev *dev = &sso->dev;\n+\tstruct mbox *mbox = mbox_get(dev->mbox);\n \n-\tplt_spinlock_lock(&sso->mbox_lock);\n-\tdetach_req = mbox_alloc_msg_detach_resources(dev->mbox);\n+\tdetach_req = mbox_alloc_msg_detach_resources(mbox);\n \tPLT_ASSERT(detach_req);\n \tdetach_req->partial = true;\n \tdetach_req->timlfs = true;\n \n-\tmbox_process(dev->mbox);\n-\tplt_spinlock_unlock(&sso->mbox_lock);\n+\tmbox_process(mbox);\n+\tmbox_put(mbox);\n }\ndiff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map\nindex 17f0ec6b48..77bf3f2807 100644\n--- a/drivers/common/cnxk/version.map\n+++ b/drivers/common/cnxk/version.map\n@@ -321,6 +321,8 @@ INTERNAL {\n \troc_npa_ctx_dump;\n \troc_npa_dev_fini;\n \troc_npa_dev_init;\n+\troc_npa_dev_lock;\n+\troc_npa_dev_unlock;\n \troc_npa_dump;\n \troc_npa_lf_init_cb_register;\n \troc_npa_pool_create;\n",
    "prefixes": [
        "1/1"
    ]
}