Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/121134/?format=api
{ "id": 121134, "url": "http://patches.dpdk.org/api/patches/121134/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20221220192645.14042-37-syalavarthi@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20221220192645.14042-37-syalavarthi@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20221220192645.14042-37-syalavarthi@marvell.com", "date": "2022-12-20T19:26:43", "name": "[v3,36/38] ml/cnxk: add support to use lock during jcmd enq", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "af7cbc519522d971370ec14c907d23f5e87e1482", "submitter": { "id": 2480, "url": "http://patches.dpdk.org/api/people/2480/?format=api", "name": "Srikanth Yalavarthi", "email": "syalavarthi@marvell.com" }, "delegate": { "id": 1, "url": "http://patches.dpdk.org/api/users/1/?format=api", "username": "tmonjalo", "first_name": "Thomas", "last_name": "Monjalon", "email": "thomas@monjalon.net" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20221220192645.14042-37-syalavarthi@marvell.com/mbox/", "series": [ { "id": 26199, "url": "http://patches.dpdk.org/api/series/26199/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=26199", "date": "2022-12-20T19:26:07", "name": "Implementation of ML CNXK driver", "version": 3, "mbox": "http://patches.dpdk.org/series/26199/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/121134/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/121134/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 86FADA0545;\n\tTue, 20 Dec 2022 20:30:37 +0100 (CET)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 0459B42DBA;\n\tTue, 20 Dec 2022 20:27:28 +0100 (CET)", "from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com\n [67.231.148.174])\n by mails.dpdk.org (Postfix) with ESMTP id AE82842D3A\n for <dev@dpdk.org>; Tue, 20 Dec 2022 20:27:03 +0100 (CET)", "from pps.filterd (m0045849.ppops.net [127.0.0.1])\n by mx0a-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id\n 2BKHOmm9018275 for <dev@dpdk.org>; Tue, 20 Dec 2022 11:27:03 -0800", "from dc5-exch01.marvell.com ([199.233.59.181])\n by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3mkapj2tqc-2\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Tue, 20 Dec 2022 11:27:02 -0800", "from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.42;\n Tue, 20 Dec 2022 11:27:01 -0800", "from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.42 via Frontend\n Transport; Tue, 20 Dec 2022 11:27:01 -0800", "from ml-host-33.caveonetworks.com (unknown [10.110.143.233])\n by maili.marvell.com (Postfix) with ESMTP id 908EB3F7073;\n Tue, 20 Dec 2022 11:27:01 -0800 (PST)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-type; s=pfpt0220; bh=bUiqW5kEd7/njPJvMyBUhoNr4THei2hoFH7UXwml43s=;\n b=U7poz/fR99VFLcxnkJqpZi9SSnrI0DaTG2+76a5G/UFaFoTaATD/TJZwKjrjOgPjhc6f\n j5ku/nc19CoaloZRQgrMZQ9zC27F1BxSB52fDzl0lTvdot0XKXjyoIPyGFzI4+NUT3vB\n B3MnskrK6islOVJB3fK9Mb8txIiWu/YqUfX4jZWZvopwLH8NVO4MV1jxcmCQA4xVP9aY\n WZe1sogt7tV3y0FRvY6wfocQXrfJ534vkCSKMCoJrR8guHkmzKKIwviSvdzWkG1yl7ZC\n wxWH8CYMwljbDTEsDDXo6yBM90bPPE7l2nXU7vXpGa2pLgAvT+flm2cBEznfUz40M1vO RQ==", "From": "Srikanth Yalavarthi <syalavarthi@marvell.com>", "To": "Srikanth Yalavarthi <syalavarthi@marvell.com>", "CC": "<dev@dpdk.org>, <sshankarnara@marvell.com>, <jerinj@marvell.com>,\n <aprabhu@marvell.com>", "Subject": "[PATCH v3 36/38] ml/cnxk: add support to use lock during jcmd enq", "Date": "Tue, 20 Dec 2022 11:26:43 -0800", "Message-ID": "<20221220192645.14042-37-syalavarthi@marvell.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": "<20221220192645.14042-1-syalavarthi@marvell.com>", "References": "<20221208201806.21893-1-syalavarthi@marvell.com>\n <20221220192645.14042-1-syalavarthi@marvell.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Proofpoint-ORIG-GUID": "-A0uOLs1Z68eZ-i2P8R0Ievtp7UQH2AQ", "X-Proofpoint-GUID": "-A0uOLs1Z68eZ-i2P8R0Ievtp7UQH2AQ", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.205,Aquarius:18.0.923,Hydra:6.0.545,FMLib:17.11.122.1\n definitions=2022-12-20_06,2022-12-20_01,2022-06-22_01", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Added device argument \"hw_queue_lock\" to select the JCMDQ enqueue\nROC function to be used in fast path.\n\nhw_queue_lock:\n\n0: Disable, use lock free version of JCMDQ enqueue ROC \tfunction for\n\tjob queuing. To avoid race condition in request queuing to\n\thardware, disabling hw_queue_lock restricts the number of\n\tqueue-pairs supported by cnxk driver to 1.\n\n1: Enable, (default) use spin-lock version of JCMDQ enqueue ROC\n\tfunction for job queuing. Enabling spinlock version would\n\tdisable restrictions on the number of queue-pairs that\n\tcan be created.\n\nSigned-off-by: Srikanth Yalavarthi <syalavarthi@marvell.com>\n---\n drivers/ml/cnxk/cn10k_ml_dev.c | 31 ++++++++++++++++++++++++++++++-\n drivers/ml/cnxk/cn10k_ml_dev.h | 13 +++++++++++--\n drivers/ml/cnxk/cn10k_ml_ops.c | 20 +++++++++++++++++---\n 3 files changed, 58 insertions(+), 6 deletions(-)", "diff": "diff --git a/drivers/ml/cnxk/cn10k_ml_dev.c b/drivers/ml/cnxk/cn10k_ml_dev.c\nindex 5c02d67c8e..aa503b2691 100644\n--- a/drivers/ml/cnxk/cn10k_ml_dev.c\n+++ b/drivers/ml/cnxk/cn10k_ml_dev.c\n@@ -22,12 +22,14 @@\n #define CN10K_ML_FW_REPORT_DPE_WARNINGS \"report_dpe_warnings\"\n #define CN10K_ML_DEV_CACHE_MODEL_DATA\t\"cache_model_data\"\n #define CN10K_ML_OCM_ALLOC_MODE\t\t\"ocm_alloc_mode\"\n+#define CN10K_ML_DEV_HW_QUEUE_LOCK\t\"hw_queue_lock\"\n \n #define CN10K_ML_FW_PATH_DEFAULT\t\t\"/lib/firmware/mlip-fw.bin\"\n #define CN10K_ML_FW_ENABLE_DPE_WARNINGS_DEFAULT 1\n #define CN10K_ML_FW_REPORT_DPE_WARNINGS_DEFAULT 0\n #define CN10K_ML_DEV_CACHE_MODEL_DATA_DEFAULT\t1\n #define CN10K_ML_OCM_ALLOC_MODE_DEFAULT\t\t\"lowest\"\n+#define CN10K_ML_DEV_HW_QUEUE_LOCK_DEFAULT\t1\n \n /* ML firmware macros */\n #define FW_MEMZONE_NAME\t\t \"ml_cn10k_fw_mz\"\n@@ -46,6 +48,7 @@ static const char *const valid_args[] = {CN10K_ML_FW_PATH,\n \t\t\t\t\t CN10K_ML_FW_REPORT_DPE_WARNINGS,\n \t\t\t\t\t CN10K_ML_DEV_CACHE_MODEL_DATA,\n \t\t\t\t\t CN10K_ML_OCM_ALLOC_MODE,\n+\t\t\t\t\t CN10K_ML_DEV_HW_QUEUE_LOCK,\n \t\t\t\t\t NULL};\n \n /* Dummy operations for ML device */\n@@ -87,6 +90,7 @@ cn10k_mldev_parse_devargs(struct rte_devargs *devargs, struct cn10k_ml_dev *mlde\n \tbool cache_model_data_set = false;\n \tstruct rte_kvargs *kvlist = NULL;\n \tbool ocm_alloc_mode_set = false;\n+\tbool hw_queue_lock_set = false;\n \tchar *ocm_alloc_mode = NULL;\n \tbool fw_path_set = false;\n \tchar *fw_path = NULL;\n@@ -158,6 +162,18 @@ cn10k_mldev_parse_devargs(struct rte_devargs *devargs, struct cn10k_ml_dev *mlde\n \t\tocm_alloc_mode_set = true;\n \t}\n \n+\tif (rte_kvargs_count(kvlist, CN10K_ML_DEV_HW_QUEUE_LOCK) == 1) {\n+\t\tret = rte_kvargs_process(kvlist, CN10K_ML_DEV_HW_QUEUE_LOCK, &parse_integer_arg,\n+\t\t\t\t\t &mldev->hw_queue_lock);\n+\t\tif (ret < 0) {\n+\t\t\tplt_err(\"Error processing arguments, key = %s\\n\",\n+\t\t\t\tCN10K_ML_DEV_HW_QUEUE_LOCK);\n+\t\t\tret = -EINVAL;\n+\t\t\tgoto exit;\n+\t\t}\n+\t\thw_queue_lock_set = true;\n+\t}\n+\n check_args:\n \tif (!fw_path_set)\n \t\tmldev->fw.path = CN10K_ML_FW_PATH_DEFAULT;\n@@ -215,6 +231,18 @@ cn10k_mldev_parse_devargs(struct rte_devargs *devargs, struct cn10k_ml_dev *mlde\n \t}\n \tplt_info(\"ML: %s = %s\", CN10K_ML_OCM_ALLOC_MODE, mldev->ocm.alloc_mode);\n \n+\tif (!hw_queue_lock_set) {\n+\t\tmldev->hw_queue_lock = CN10K_ML_DEV_HW_QUEUE_LOCK_DEFAULT;\n+\t} else {\n+\t\tif ((mldev->hw_queue_lock < 0) || (mldev->hw_queue_lock > 1)) {\n+\t\t\tplt_err(\"Invalid argument, %s = %d\\n\", CN10K_ML_DEV_HW_QUEUE_LOCK,\n+\t\t\t\tmldev->hw_queue_lock);\n+\t\t\tret = -EINVAL;\n+\t\t\tgoto exit;\n+\t\t}\n+\t}\n+\tplt_info(\"ML: %s = %d\", CN10K_ML_DEV_HW_QUEUE_LOCK, mldev->hw_queue_lock);\n+\n exit:\n \tif (kvlist)\n \t\trte_kvargs_free(kvlist);\n@@ -756,4 +784,5 @@ RTE_PMD_REGISTER_PARAM_STRING(MLDEV_NAME_CN10K_PMD, CN10K_ML_FW_PATH\n \t\t\t \"=<path>\" CN10K_ML_FW_ENABLE_DPE_WARNINGS\n \t\t\t \"=<0|1>\" CN10K_ML_FW_REPORT_DPE_WARNINGS\n \t\t\t \"=<0|1>\" CN10K_ML_DEV_CACHE_MODEL_DATA\n-\t\t\t \"=<0|1>\" CN10K_ML_OCM_ALLOC_MODE \"=<lowest|largest>\");\n+\t\t\t \"=<0|1>\" CN10K_ML_OCM_ALLOC_MODE\n+\t\t\t \"=<lowest|largest>\" CN10K_ML_DEV_HW_QUEUE_LOCK \"=<0|1>\");\ndiff --git a/drivers/ml/cnxk/cn10k_ml_dev.h b/drivers/ml/cnxk/cn10k_ml_dev.h\nindex 718edadde7..49676ac9e7 100644\n--- a/drivers/ml/cnxk/cn10k_ml_dev.h\n+++ b/drivers/ml/cnxk/cn10k_ml_dev.h\n@@ -21,8 +21,11 @@\n /* Maximum number of models per device */\n #define ML_CN10K_MAX_MODELS 16\n \n-/* Maximum number of queue-pairs per device */\n-#define ML_CN10K_MAX_QP_PER_DEVICE 1\n+/* Maximum number of queue-pairs per device, spinlock version */\n+#define ML_CN10K_MAX_QP_PER_DEVICE_SL 16\n+\n+/* Maximum number of queue-pairs per device, lock-free version */\n+#define ML_CN10K_MAX_QP_PER_DEVICE_LF 1\n \n /* Maximum number of descriptors per queue-pair */\n #define ML_CN10K_MAX_DESC_PER_QP 1024\n@@ -384,6 +387,12 @@ struct cn10k_ml_dev {\n \n \t/* Enable / disable model data caching */\n \tint cache_model_data;\n+\n+\t/* Use spinlock version of ROC enqueue */\n+\tint hw_queue_lock;\n+\n+\t/* JCMD enqueue function handler */\n+\tbool (*ml_jcmdq_enqueue)(struct roc_ml *roc_ml, struct ml_job_cmd_s *job_cmd);\n };\n \n uint64_t cn10k_ml_fw_flags_get(struct cn10k_ml_fw *fw);\ndiff --git a/drivers/ml/cnxk/cn10k_ml_ops.c b/drivers/ml/cnxk/cn10k_ml_ops.c\nindex 1e6d366c59..c82f3de5c8 100644\n--- a/drivers/ml/cnxk/cn10k_ml_ops.c\n+++ b/drivers/ml/cnxk/cn10k_ml_ops.c\n@@ -534,13 +534,21 @@ cn10k_ml_cache_model_data(struct rte_ml_dev *dev, int16_t model_id)\n static int\n cn10k_ml_dev_info_get(struct rte_ml_dev *dev, struct rte_ml_dev_info *dev_info)\n {\n+\tstruct cn10k_ml_dev *mldev;\n+\n \tif (dev_info == NULL)\n \t\treturn -EINVAL;\n \n+\tmldev = dev->data->dev_private;\n+\n \tmemset(dev_info, 0, sizeof(struct rte_ml_dev_info));\n \tdev_info->driver_name = dev->device->driver->name;\n \tdev_info->max_models = ML_CN10K_MAX_MODELS;\n-\tdev_info->max_queue_pairs = ML_CN10K_MAX_QP_PER_DEVICE;\n+\tif (mldev->hw_queue_lock)\n+\t\tdev_info->max_queue_pairs = ML_CN10K_MAX_QP_PER_DEVICE_SL;\n+\telse\n+\t\tdev_info->max_queue_pairs = ML_CN10K_MAX_QP_PER_DEVICE_LF;\n+\n \tdev_info->max_desc = ML_CN10K_MAX_DESC_PER_QP;\n \tdev_info->max_segments = ML_CN10K_MAX_SEGMENTS;\n \tdev_info->min_align_size = ML_CN10K_ALIGN_SIZE;\n@@ -703,6 +711,12 @@ cn10k_ml_dev_configure(struct rte_ml_dev *dev, const struct rte_ml_dev_config *c\n \telse\n \t\tmldev->xstats_enabled = false;\n \n+\t/* Set JCMDQ enqueue function */\n+\tif (mldev->hw_queue_lock == 1)\n+\t\tmldev->ml_jcmdq_enqueue = roc_ml_jcmdq_enqueue_sl;\n+\telse\n+\t\tmldev->ml_jcmdq_enqueue = roc_ml_jcmdq_enqueue_lf;\n+\n \tdev->enqueue_burst = cn10k_ml_enqueue_burst;\n \tdev->dequeue_burst = cn10k_ml_dequeue_burst;\n \tdev->op_error_get = cn10k_ml_op_error_get;\n@@ -1992,7 +2006,7 @@ cn10k_ml_enqueue_burst(struct rte_ml_dev *dev, uint16_t qp_id, struct rte_ml_op\n \treq->result.user_ptr = op->user_ptr;\n \n \tplt_write64(ML_CN10K_POLL_JOB_START, &req->status);\n-\tenqueued = roc_ml_jcmdq_enqueue_lf(&mldev->roc, &req->jcmd);\n+\tenqueued = mldev->ml_jcmdq_enqueue(&mldev->roc, &req->jcmd);\n \tif (unlikely(!enqueued))\n \t\tgoto jcmdq_full;\n \n@@ -2113,7 +2127,7 @@ cn10k_ml_inference_sync(struct rte_ml_dev *dev, struct rte_ml_op *op)\n \ttimeout = true;\n \treq->timeout = plt_tsc_cycles() + ML_CN10K_CMD_TIMEOUT * plt_tsc_hz();\n \tdo {\n-\t\tif (roc_ml_jcmdq_enqueue_lf(&mldev->roc, &req->jcmd)) {\n+\t\tif (mldev->ml_jcmdq_enqueue(&mldev->roc, &req->jcmd)) {\n \t\t\treq->op = op;\n \t\t\ttimeout = false;\n \t\t\tbreak;\n", "prefixes": [ "v3", "36/38" ] }