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GET /api/patches/121053/?format=api
{ "id": 121053, "url": "http://patches.dpdk.org/api/patches/121053/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20221220034741.447037-3-simei.su@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20221220034741.447037-3-simei.su@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20221220034741.447037-3-simei.su@intel.com", "date": "2022-12-20T03:47:41", "name": "[2/2] net/igc: enable Tx timestamp offload", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "c32b9b7c67d0c99ec8de58b0081d3f88f2d5712e", "submitter": { "id": 1298, "url": "http://patches.dpdk.org/api/people/1298/?format=api", "name": "Simei Su", "email": "simei.su@intel.com" }, "delegate": { "id": 1540, "url": "http://patches.dpdk.org/api/users/1540/?format=api", "username": "qzhan15", "first_name": "Qi", "last_name": "Zhang", "email": "qi.z.zhang@intel.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20221220034741.447037-3-simei.su@intel.com/mbox/", "series": [ { "id": 26188, "url": "http://patches.dpdk.org/api/series/26188/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=26188", "date": "2022-12-20T03:47:39", "name": "net/igc: support Tx timestamp offload", "version": 1, "mbox": "http://patches.dpdk.org/series/26188/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/121053/comments/", "check": "warning", "checks": "http://patches.dpdk.org/api/patches/121053/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 022D1A00C5;\n\tTue, 20 Dec 2022 04:48:08 +0100 (CET)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 7222A4114A;\n\tTue, 20 Dec 2022 04:48:03 +0100 (CET)", "from mga12.intel.com (mga12.intel.com [192.55.52.136])\n by mails.dpdk.org (Postfix) with ESMTP id 4D250410DE\n for <dev@dpdk.org>; Tue, 20 Dec 2022 04:48:00 +0100 (CET)", "from fmsmga004.fm.intel.com ([10.253.24.48])\n by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 19 Dec 2022 19:48:00 -0800", "from unknown (HELO npg-dpdk-simeisu-cvl-119d218.sh.intel.com)\n ([10.67.119.208])\n by fmsmga004.fm.intel.com with ESMTP; 19 Dec 2022 19:47:58 -0800" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1671508080; x=1703044080;\n h=from:to:cc:subject:date:message-id:in-reply-to: references;\n bh=Vm56hqsuJjDhg5sI1lgapWF7ia2DezSIdXKgrf4hJBw=;\n b=Ag0fj2xHO1XWTx8VYKAqXQ+m2PCf0pyD6D1QR6ESOsB1CMz776TvHuN2\n ZRpXt2fAQUN86dvSjx2AZilRYyLdRGSkkfo4tom/H87wBrD/Zwdtim8Zr\n /bHfCGz9q0juTyU3OiVTKDNrciX+iI4UKie6zPXwbRQNR77iHgbvl3K5d\n EFTSGwgde9CpmiXtmaL6LamJnpSCWQ2HbBxKEt6ras69hvqD0MtyDG2Ab\n 0X1f/6w9Y0ys9Yi4Kod+oujge5CEawgMybWuv/IhQoGCb+XIqCCKpxI2K\n emkDK6e+kR6sTM7li7kDKZmIim38fqomZacaVU3hr2B0bJIMLiqF5FK/r w==;", "X-IronPort-AV": [ "E=McAfee;i=\"6500,9779,10566\"; a=\"299198848\"", "E=Sophos;i=\"5.96,258,1665471600\"; d=\"scan'208\";a=\"299198848\"", "E=McAfee;i=\"6500,9779,10566\"; a=\"719378287\"", "E=Sophos;i=\"5.96,258,1665471600\"; d=\"scan'208\";a=\"719378287\"" ], "X-ExtLoop1": "1", "From": "Simei Su <simei.su@intel.com>", "To": "qi.z.zhang@intel.com,\n\tjunfeng.guo@intel.com", "Cc": "dev@dpdk.org,\n\twenjun1.wu@intel.com,\n\tSimei Su <simei.su@intel.com>", "Subject": "[PATCH 2/2] net/igc: enable Tx timestamp offload", "Date": "Tue, 20 Dec 2022 11:47:41 +0800", "Message-Id": "<20221220034741.447037-3-simei.su@intel.com>", "X-Mailer": "git-send-email 2.9.5", "In-Reply-To": "<20221220034741.447037-1-simei.su@intel.com>", "References": "<20221220034741.447037-1-simei.su@intel.com>", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "This patch supports Tx timestamp offload by leveraging NIC's\n\"Launch Time\" for \"RTE_ETH_TX_OFFLOAD_SEND_ON_TIMESTAMP\".\n\nSigned-off-by: Simei Su <simei.su@intel.com>\n---\n drivers/net/igc/igc_ethdev.c | 70 ++++++++++++++++++++++++++++++++++++++++++++\n drivers/net/igc/igc_ethdev.h | 6 +++-\n drivers/net/igc/igc_txrx.c | 58 +++++++++++++++++++++++++++++++-----\n drivers/net/igc/igc_txrx.h | 3 ++\n 4 files changed, 128 insertions(+), 9 deletions(-)", "diff": "diff --git a/drivers/net/igc/igc_ethdev.c b/drivers/net/igc/igc_ethdev.c\nindex ef3346b..28f6cd5 100644\n--- a/drivers/net/igc/igc_ethdev.c\n+++ b/drivers/net/igc/igc_ethdev.c\n@@ -88,6 +88,9 @@\n #define IGC_I225_RX_LATENCY_1000\t300\n #define IGC_I225_RX_LATENCY_2500\t1485\n \n+uint64_t igc_timestamp_dynflag;\n+int igc_timestamp_dynfield_offset = -1;\n+\n static const struct rte_eth_desc_lim rx_desc_lim = {\n \t.nb_max = IGC_MAX_RXD,\n \t.nb_min = IGC_MIN_RXD,\n@@ -267,6 +270,7 @@ static int eth_igc_timesync_read_time(struct rte_eth_dev *dev,\n \t\t\t\t struct timespec *timestamp);\n static int eth_igc_timesync_write_time(struct rte_eth_dev *dev,\n \t\t\t\t const struct timespec *timestamp);\n+static int eth_igc_read_clock(struct rte_eth_dev *dev, uint64_t *clock);\n \n static const struct eth_dev_ops eth_igc_ops = {\n \t.dev_configure\t\t= eth_igc_configure,\n@@ -327,6 +331,7 @@ static const struct eth_dev_ops eth_igc_ops = {\n \t.timesync_adjust_time\t= eth_igc_timesync_adjust_time,\n \t.timesync_read_time\t= eth_igc_timesync_read_time,\n \t.timesync_write_time\t= eth_igc_timesync_write_time,\n+\t.read_clock = eth_igc_read_clock,\n };\n \n /*\n@@ -949,7 +954,12 @@ eth_igc_start(struct rte_eth_dev *dev)\n \tstruct igc_adapter *adapter = IGC_DEV_PRIVATE(dev);\n \tstruct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);\n \tstruct rte_intr_handle *intr_handle = pci_dev->intr_handle;\n+\tuint32_t nsec, sec, baset_l, baset_h, tqavctrl;\n+\tstruct timespec system_time;\n+\tint64_t n, systime;\n+\tuint32_t txqctl = 0;\n \tuint32_t *speeds;\n+\tuint16_t i;\n \tint ret;\n \n \tPMD_INIT_FUNC_TRACE();\n@@ -1009,6 +1019,55 @@ eth_igc_start(struct rte_eth_dev *dev)\n \t\treturn ret;\n \t}\n \n+\tif (igc_timestamp_dynflag > 0) {\n+\t\tadapter->base_time = 0;\n+\t\tadapter->cycle_time = NSEC_PER_SEC;\n+\n+\t\tIGC_WRITE_REG(hw, IGC_TSSDP, 0);\n+\t\tIGC_WRITE_REG(hw, IGC_TSIM, TSINTR_TXTS);\n+\t\tIGC_WRITE_REG(hw, IGC_IMS, IGC_ICR_TS);\n+\n+\t\tIGC_WRITE_REG(hw, IGC_TSAUXC, 0);\n+\t\tIGC_WRITE_REG(hw, IGC_I350_DTXMXPKTSZ, IGC_DTXMXPKTSZ_TSN);\n+\t\tIGC_WRITE_REG(hw, IGC_TXPBS, IGC_TXPBSIZE_TSN);\n+\n+\t\ttqavctrl = IGC_READ_REG(hw, IGC_I210_TQAVCTRL);\n+\t\ttqavctrl |= IGC_TQAVCTRL_TRANSMIT_MODE_TSN |\n+\t\t\t IGC_TQAVCTRL_ENHANCED_QAV;\n+\t\tIGC_WRITE_REG(hw, IGC_I210_TQAVCTRL, tqavctrl);\n+\n+\t\tIGC_WRITE_REG(hw, IGC_QBVCYCLET_S, adapter->cycle_time);\n+\t\tIGC_WRITE_REG(hw, IGC_QBVCYCLET, adapter->cycle_time);\n+\n+\t\tfor (i = 0; i < dev->data->nb_tx_queues; i++) {\n+\t\t\tIGC_WRITE_REG(hw, IGC_STQT(i), 0);\n+\t\t\tIGC_WRITE_REG(hw, IGC_ENDQT(i), NSEC_PER_SEC);\n+\n+\t\t\ttxqctl |= IGC_TXQCTL_QUEUE_MODE_LAUNCHT;\n+\t\t\tIGC_WRITE_REG(hw, IGC_TXQCTL(i), txqctl);\n+\t\t}\n+\n+\t\tclock_gettime(CLOCK_REALTIME, &system_time);\n+\t\tIGC_WRITE_REG(hw, IGC_SYSTIML, system_time.tv_nsec);\n+\t\tIGC_WRITE_REG(hw, IGC_SYSTIMH, system_time.tv_sec);\n+\n+\t\tnsec = IGC_READ_REG(hw, IGC_SYSTIML);\n+\t\tsec = IGC_READ_REG(hw, IGC_SYSTIMH);\n+\t\tsystime = (int64_t)sec * NSEC_PER_SEC + (int64_t)nsec;\n+\n+\t\tif (systime > adapter->base_time) {\n+\t\t\tn = (systime - adapter->base_time) /\n+\t\t\t adapter->cycle_time;\n+\t\t\tadapter->base_time = adapter->base_time +\n+\t\t\t\t(n + 1) * adapter->cycle_time;\n+\t\t}\n+\n+\t\tbaset_h = adapter->base_time / NSEC_PER_SEC;\n+\t\tbaset_l = adapter->base_time % NSEC_PER_SEC;\n+\t\tIGC_WRITE_REG(hw, IGC_BASET_H, baset_h);\n+\t\tIGC_WRITE_REG(hw, IGC_BASET_L, baset_l);\n+\t}\n+\n \tigc_clear_hw_cntrs_base_generic(hw);\n \n \t/* VLAN Offload Settings */\n@@ -2804,6 +2863,17 @@ eth_igc_timesync_disable(struct rte_eth_dev *dev)\n }\n \n static int\n+eth_igc_read_clock(__rte_unused struct rte_eth_dev *dev, uint64_t *clock)\n+{\n+\tstruct timespec system_time;\n+\n+\tclock_gettime(CLOCK_REALTIME, &system_time);\n+\t*clock = system_time.tv_sec * NSEC_PER_SEC + system_time.tv_nsec;\n+\n+\treturn 0;\n+}\n+\n+static int\n eth_igc_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,\n \tstruct rte_pci_device *pci_dev)\n {\ndiff --git a/drivers/net/igc/igc_ethdev.h b/drivers/net/igc/igc_ethdev.h\nindex 237d3c1..8d7eb54 100644\n--- a/drivers/net/igc/igc_ethdev.h\n+++ b/drivers/net/igc/igc_ethdev.h\n@@ -87,7 +87,8 @@ extern \"C\" {\n \tRTE_ETH_TX_OFFLOAD_SCTP_CKSUM | \\\n \tRTE_ETH_TX_OFFLOAD_TCP_TSO | \\\n \tRTE_ETH_TX_OFFLOAD_UDP_TSO\t | \\\n-\tRTE_ETH_TX_OFFLOAD_MULTI_SEGS)\n+\tRTE_ETH_TX_OFFLOAD_MULTI_SEGS | \\\n+\tRTE_ETH_TX_OFFLOAD_SEND_ON_TIMESTAMP)\n \n #define IGC_RSS_OFFLOAD_ALL\t( \\\n \tRTE_ETH_RSS_IPV4 | \\\n@@ -240,6 +241,9 @@ struct igc_adapter {\n \tstruct igc_syn_filter syn_filter;\n \tstruct igc_rss_filter rss_filter;\n \tstruct igc_flow_list flow_list;\n+\n+\tint64_t base_time;\n+\tuint32_t cycle_time;\n };\n \n #define IGC_DEV_PRIVATE(_dev)\t((_dev)->data->dev_private)\ndiff --git a/drivers/net/igc/igc_txrx.c b/drivers/net/igc/igc_txrx.c\nindex 0236c7f..dd48655 100644\n--- a/drivers/net/igc/igc_txrx.c\n+++ b/drivers/net/igc/igc_txrx.c\n@@ -1411,6 +1411,19 @@ what_advctx_update(struct igc_tx_queue *txq, uint64_t flags,\n \treturn IGC_CTX_NUM;\n }\n \n+static uint32_t igc_tx_launchtime(uint64_t txtime, uint16_t port_id)\n+{\n+\tstruct rte_eth_dev *dev = &rte_eth_devices[port_id];\n+\tstruct igc_adapter *adapter = IGC_DEV_PRIVATE(dev);\n+\tuint64_t base_time = adapter->base_time;\n+\tuint64_t cycle_time = adapter->cycle_time;\n+\tuint32_t launchtime;\n+\n+\tlaunchtime = (txtime - base_time) % cycle_time;\n+\n+\treturn rte_cpu_to_le_32(launchtime);\n+}\n+\n /*\n * This is a separate function, looking for optimization opportunity here\n * Rework required to go with the pre-defined values.\n@@ -1418,7 +1431,8 @@ what_advctx_update(struct igc_tx_queue *txq, uint64_t flags,\n static inline void\n igc_set_xmit_ctx(struct igc_tx_queue *txq,\n \t\tvolatile struct igc_adv_tx_context_desc *ctx_txd,\n-\t\tuint64_t ol_flags, union igc_tx_offload tx_offload)\n+\t\tuint64_t ol_flags, union igc_tx_offload tx_offload,\n+\t\tuint64_t txtime)\n {\n \tuint32_t type_tucmd_mlhl;\n \tuint32_t mss_l4len_idx;\n@@ -1492,16 +1506,23 @@ igc_set_xmit_ctx(struct igc_tx_queue *txq,\n \t\t}\n \t}\n \n-\ttxq->ctx_cache[ctx_curr].flags = ol_flags;\n-\ttxq->ctx_cache[ctx_curr].tx_offload.data =\n-\t\ttx_offload_mask.data & tx_offload.data;\n-\ttxq->ctx_cache[ctx_curr].tx_offload_mask = tx_offload_mask;\n+\tif (!txtime) {\n+\t\ttxq->ctx_cache[ctx_curr].flags = ol_flags;\n+\t\ttxq->ctx_cache[ctx_curr].tx_offload.data =\n+\t\t\ttx_offload_mask.data & tx_offload.data;\n+\t\ttxq->ctx_cache[ctx_curr].tx_offload_mask = tx_offload_mask;\n+\t}\n \n \tctx_txd->type_tucmd_mlhl = rte_cpu_to_le_32(type_tucmd_mlhl);\n \tvlan_macip_lens = (uint32_t)tx_offload.data;\n \tctx_txd->vlan_macip_lens = rte_cpu_to_le_32(vlan_macip_lens);\n \tctx_txd->mss_l4len_idx = rte_cpu_to_le_32(mss_l4len_idx);\n-\tctx_txd->u.launch_time = 0;\n+\n+\tif (txtime)\n+\t\tctx_txd->u.launch_time = igc_tx_launchtime(txtime,\n+\t\t\t\t\t\t\t txq->port_id);\n+\telse\n+\t\tctx_txd->u.launch_time = 0;\n }\n \n static inline uint32_t\n@@ -1551,6 +1572,7 @@ igc_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)\n \tuint64_t tx_ol_req;\n \tuint32_t new_ctx = 0;\n \tunion igc_tx_offload tx_offload = {0};\n+\tuint64_t ts;\n \n \ttx_id = txq->tx_tail;\n \ttxe = &sw_ring[tx_id];\n@@ -1698,8 +1720,16 @@ igc_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)\n \t\t\t\t\ttxe->mbuf = NULL;\n \t\t\t\t}\n \n-\t\t\t\tigc_set_xmit_ctx(txq, ctx_txd, tx_ol_req,\n-\t\t\t\t\t\ttx_offload);\n+\t\t\t\tif (igc_timestamp_dynflag > 0) {\n+\t\t\t\t\tts = *RTE_MBUF_DYNFIELD(tx_pkt,\n+\t\t\t\t\t\tigc_timestamp_dynfield_offset,\n+\t\t\t\t\t\tuint64_t *);\n+\t\t\t\t\tigc_set_xmit_ctx(txq, ctx_txd,\n+\t\t\t\t\t\ttx_ol_req, tx_offload, ts);\n+\t\t\t\t} else {\n+\t\t\t\t\tigc_set_xmit_ctx(txq, ctx_txd,\n+\t\t\t\t\t\ttx_ol_req, tx_offload, 0);\n+\t\t\t\t}\n \n \t\t\t\ttxe->last_id = tx_last;\n \t\t\t\ttx_id = txe->next_id;\n@@ -2081,9 +2111,11 @@ void\n igc_tx_init(struct rte_eth_dev *dev)\n {\n \tstruct igc_hw *hw = IGC_DEV_PRIVATE_HW(dev);\n+\tuint64_t offloads = dev->data->dev_conf.txmode.offloads;\n \tuint32_t tctl;\n \tuint32_t txdctl;\n \tuint16_t i;\n+\tint err;\n \n \t/* Setup the Base and Length of the Tx Descriptor Rings. */\n \tfor (i = 0; i < dev->data->nb_tx_queues; i++) {\n@@ -2113,6 +2145,16 @@ igc_tx_init(struct rte_eth_dev *dev)\n \t\tIGC_WRITE_REG(hw, IGC_TXDCTL(txq->reg_idx), txdctl);\n \t}\n \n+\tif (offloads & RTE_ETH_TX_OFFLOAD_SEND_ON_TIMESTAMP) {\n+\t\terr = rte_mbuf_dyn_tx_timestamp_register(\n+\t\t\t&igc_timestamp_dynfield_offset,\n+\t\t\t&igc_timestamp_dynflag);\n+\t\tif (err) {\n+\t\t\tPMD_DRV_LOG(ERR,\n+\t\t\t\t\"Cannot register mbuf field/flag for timestamp\");\n+\t\t}\n+\t}\n+\n \tigc_config_collision_dist(hw);\n \n \t/* Program the Transmit Control Register. */\ndiff --git a/drivers/net/igc/igc_txrx.h b/drivers/net/igc/igc_txrx.h\nindex e7272f8..73757d2 100644\n--- a/drivers/net/igc/igc_txrx.h\n+++ b/drivers/net/igc/igc_txrx.h\n@@ -11,6 +11,9 @@\n extern \"C\" {\n #endif\n \n+extern uint64_t igc_timestamp_dynflag;\n+extern int igc_timestamp_dynfield_offset;\n+\n struct igc_rx_entry {\n \tstruct rte_mbuf *mbuf; /**< mbuf associated with RX descriptor. */\n };\n", "prefixes": [ "2/2" ] }