Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/120197/?format=api
{ "id": 120197, "url": "http://patches.dpdk.org/api/patches/120197/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20221128095442.3185112-1-ndabilpuram@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20221128095442.3185112-1-ndabilpuram@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20221128095442.3185112-1-ndabilpuram@marvell.com", "date": "2022-11-28T09:54:32", "name": "[01/11] common/cnxk: free pending sqe buffers", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "3558c14411e5fadd62673b4b783c07072f5ff23c", "submitter": { "id": 1202, "url": "http://patches.dpdk.org/api/people/1202/?format=api", "name": "Nithin Dabilpuram", "email": "ndabilpuram@marvell.com" }, "delegate": { "id": 310, "url": "http://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20221128095442.3185112-1-ndabilpuram@marvell.com/mbox/", "series": [ { "id": 25906, "url": "http://patches.dpdk.org/api/series/25906/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=25906", "date": "2022-11-28T09:54:32", "name": "[01/11] common/cnxk: free pending sqe buffers", "version": 1, "mbox": "http://patches.dpdk.org/series/25906/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/120197/comments/", "check": "warning", "checks": "http://patches.dpdk.org/api/patches/120197/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id B92C0A00C3;\n\tMon, 28 Nov 2022 10:54:55 +0100 (CET)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 5BFD84067C;\n\tMon, 28 Nov 2022 10:54:55 +0100 (CET)", "from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com\n [67.231.148.174])\n by mails.dpdk.org (Postfix) with ESMTP id 2296B40156\n for <dev@dpdk.org>; Mon, 28 Nov 2022 10:54:53 +0100 (CET)", "from pps.filterd (m0045849.ppops.net [127.0.0.1])\n by mx0a-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id\n 2AS5ifW3025002 for <dev@dpdk.org>; Mon, 28 Nov 2022 01:54:53 -0800", "from dc5-exch02.marvell.com ([199.233.59.182])\n by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3m4q3srsdx-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Mon, 28 Nov 2022 01:54:53 -0800", "from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18;\n Mon, 28 Nov 2022 01:54:51 -0800", "from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend\n Transport; Mon, 28 Nov 2022 01:54:51 -0800", "from hyd1588t430.caveonetworks.com (unknown [10.29.52.204])\n by maili.marvell.com (Postfix) with ESMTP id 3CB483F704A;\n Mon, 28 Nov 2022 01:54:49 -0800 (PST)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : mime-version : content-transfer-encoding :\n content-type; s=pfpt0220; bh=9i0nlE6PEKGbSw8ZB1ky2J9Tc0/ExYtPeNDtB3DeLX0=;\n b=NyTvCwReJjCsT+3MG7yJRKhEYCIxRH+QvO6z8L1uUINVEzKOyRS8lvzGH6AQtaiMj0pb\n 1ItPGI/mVD0LNF0oYQfbL+mQgQ3vQG1A9TlqLZStC0yhOfbzMJjCGsKPNb1IrVQ8/Pj1\n sXOssv1disRsXUFVqFQERv9+jdpbfOJcHYUvLBaRP5emCD6aaSmIvDG1hQJ743NjXo6b\n gnp1NgOU4dFt4sMwcHL+5Z+6vkZqwxNE8hXJL/F7sjXM5eTF4Qa/n3TSkdrm+EIZS3wu\n MInJhLGJrPP84Ovo5oUZoMMnkbG8ai3JKEM+RZ0FjDHlI2b2A4zOaWiG02MdsuJEACT9 Sg==", "From": "Nithin Dabilpuram <ndabilpuram@marvell.com>", "To": "Nithin Dabilpuram <ndabilpuram@marvell.com>, Kiran Kumar K\n <kirankumark@marvell.com>, Sunil Kumar Kori <skori@marvell.com>, Satha Rao\n <skoteshwar@marvell.com>", "CC": "<jerinj@marvell.com>, <dev@dpdk.org>", "Subject": "[PATCH 01/11] common/cnxk: free pending sqe buffers", "Date": "Mon, 28 Nov 2022 15:24:32 +0530", "Message-ID": "<20221128095442.3185112-1-ndabilpuram@marvell.com>", "X-Mailer": "git-send-email 2.25.1", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-ORIG-GUID": "h1E4crlvK6yrxZ3qf4KGnoOpVVDnI3po", "X-Proofpoint-GUID": "h1E4crlvK6yrxZ3qf4KGnoOpVVDnI3po", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.219,Aquarius:18.0.895,Hydra:6.0.545,FMLib:17.11.122.1\n definitions=2022-11-28_07,2022-11-25_01,2022-06-22_01", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "From: Satha Rao <skoteshwar@marvell.com>\n\nThis patch provides a callback mechanism when SQ receives MNQ_ERR.\nEven when SQ got MNQ_ERR interrupt application still enqueue\npackets for sending they will be struck at SQ, so we are freeing\nall these pending packets when we called SQ finish.\n\nSigned-off-by: Satha Rao <skoteshwar@marvell.com>\n---\n\nDepends-on: series-25794 (\"net/cnxk: rework no-fast-free offload handling\")\n\n drivers/common/cnxk/roc_dev_priv.h | 4 +\n drivers/common/cnxk/roc_nix.h | 5 +\n drivers/common/cnxk/roc_nix_irq.c | 11 ++-\n drivers/common/cnxk/roc_nix_priv.h | 2 +\n drivers/common/cnxk/roc_nix_queue.c | 32 +++++--\n drivers/common/cnxk/roc_nix_tm.c | 141 +++++++++++++++++++++++++++-\n drivers/common/cnxk/version.map | 2 +\n 7 files changed, 186 insertions(+), 11 deletions(-)", "diff": "diff --git a/drivers/common/cnxk/roc_dev_priv.h b/drivers/common/cnxk/roc_dev_priv.h\nindex 302dc0feb0..e21a7154c0 100644\n--- a/drivers/common/cnxk/roc_dev_priv.h\n+++ b/drivers/common/cnxk/roc_dev_priv.h\n@@ -30,6 +30,9 @@ typedef void (*link_info_t)(void *roc_nix,\n /* PTP info callback */\n typedef int (*ptp_info_t)(void *roc_nix, bool enable);\n \n+/* Queue Error get callback */\n+typedef void (*q_err_cb_t)(void *roc_nix, void *data);\n+\n /* Link status get callback */\n typedef void (*link_status_get_t)(void *roc_nix,\n \t\t\t\t struct cgx_link_user_info *link);\n@@ -38,6 +41,7 @@ struct dev_ops {\n \tlink_info_t link_status_update;\n \tptp_info_t ptp_info_update;\n \tlink_status_get_t link_status_get;\n+\tq_err_cb_t q_err_cb;\n };\n \n #define dev_is_vf(dev) ((dev)->hwcap & DEV_HWCAP_F_VF)\ndiff --git a/drivers/common/cnxk/roc_nix.h b/drivers/common/cnxk/roc_nix.h\nindex 6654a2df78..dfc87e8758 100644\n--- a/drivers/common/cnxk/roc_nix.h\n+++ b/drivers/common/cnxk/roc_nix.h\n@@ -405,6 +405,9 @@ typedef void (*link_status_t)(struct roc_nix *roc_nix,\n /* PTP info update callback */\n typedef int (*ptp_info_update_t)(struct roc_nix *roc_nix, bool enable);\n \n+/* Queue Error get callback */\n+typedef void (*q_err_get_t)(struct roc_nix *roc_nix, void *data);\n+\n /* Link status get callback */\n typedef void (*link_info_get_t)(struct roc_nix *roc_nix,\n \t\t\t\tstruct roc_nix_link_info *link);\n@@ -783,6 +786,8 @@ void __roc_api roc_nix_mac_link_cb_unregister(struct roc_nix *roc_nix);\n int __roc_api roc_nix_mac_link_info_get_cb_register(\n \tstruct roc_nix *roc_nix, link_info_get_t link_info_get);\n void __roc_api roc_nix_mac_link_info_get_cb_unregister(struct roc_nix *roc_nix);\n+int __roc_api roc_nix_q_err_cb_register(struct roc_nix *roc_nix, q_err_get_t sq_err_handle);\n+void __roc_api roc_nix_q_err_cb_unregister(struct roc_nix *roc_nix);\n \n /* Ops */\n int __roc_api roc_nix_switch_hdr_set(struct roc_nix *roc_nix,\ndiff --git a/drivers/common/cnxk/roc_nix_irq.c b/drivers/common/cnxk/roc_nix_irq.c\nindex d72980fb18..661af79193 100644\n--- a/drivers/common/cnxk/roc_nix_irq.c\n+++ b/drivers/common/cnxk/roc_nix_irq.c\n@@ -249,9 +249,9 @@ nix_lf_q_irq(void *param)\n {\n \tstruct nix_qint *qint = (struct nix_qint *)param;\n \tuint8_t irq, qintx = qint->qintx;\n+\tint q, cq, rq, sq, intr_cb = 0;\n \tstruct nix *nix = qint->nix;\n \tstruct dev *dev = &nix->dev;\n-\tint q, cq, rq, sq;\n \tuint64_t intr;\n \tuint8_t rc;\n \n@@ -301,8 +301,10 @@ nix_lf_q_irq(void *param)\n \n \t\t/* Detect Meta-descriptor enqueue error */\n \t\trc = nix_lf_sq_debug_reg(nix, NIX_LF_MNQ_ERR_DBG);\n-\t\tif (rc)\n+\t\tif (rc) {\n \t\t\tplt_err(\"SQ=%d NIX_SQINT_MNQ_ERR, errcode %x\", sq, rc);\n+\t\t\tintr_cb = 1;\n+\t\t}\n \n \t\t/* Detect Send error */\n \t\trc = nix_lf_sq_debug_reg(nix, NIX_LF_SEND_ERR_DBG);\n@@ -321,6 +323,11 @@ nix_lf_q_irq(void *param)\n \t/* Dump registers to std out */\n \troc_nix_lf_reg_dump(nix_priv_to_roc_nix(nix), NULL);\n \troc_nix_queues_ctx_dump(nix_priv_to_roc_nix(nix), NULL);\n+\n+\t/* Call reset callback */\n+\tif (intr_cb)\n+\t\tif (dev->ops->q_err_cb)\n+\t\t\tdev->ops->q_err_cb(nix_priv_to_roc_nix(nix), NULL);\n }\n \n int\ndiff --git a/drivers/common/cnxk/roc_nix_priv.h b/drivers/common/cnxk/roc_nix_priv.h\nindex 2eba44c248..02290a1b86 100644\n--- a/drivers/common/cnxk/roc_nix_priv.h\n+++ b/drivers/common/cnxk/roc_nix_priv.h\n@@ -406,6 +406,8 @@ int nix_tm_bp_config_set(struct roc_nix *roc_nix, uint16_t sq, uint16_t tc,\n \t\t\t bool enable, bool force_flush);\n void nix_rq_vwqe_flush(struct roc_nix_rq *rq, uint16_t vwqe_interval);\n int nix_tm_mark_init(struct nix *nix);\n+void nix_tm_sq_free_sqe_buffer(uint64_t *sqe, int head_off, int end_off, int instr_sz);\n+int roc_nix_tm_sq_free_pending_sqe(struct nix *nix, int q);\n \n /*\n * TM priv utils.\ndiff --git a/drivers/common/cnxk/roc_nix_queue.c b/drivers/common/cnxk/roc_nix_queue.c\nindex 1cb1fd2101..8a84a34bef 100644\n--- a/drivers/common/cnxk/roc_nix_queue.c\n+++ b/drivers/common/cnxk/roc_nix_queue.c\n@@ -1089,9 +1089,8 @@ sq_cn9k_fini(struct nix *nix, struct roc_nix_sq *sq)\n \twhile (count) {\n \t\tvoid *next_sqb;\n \n-\t\tnext_sqb = *(void **)((uintptr_t)sqb_buf +\n-\t\t\t\t (uint32_t)((sqes_per_sqb - 1) *\n-\t\t\t\t\t\t sq->max_sqe_sz));\n+\t\tnext_sqb = *(void **)((uint64_t *)sqb_buf +\n+\t\t\t\t (uint32_t)((sqes_per_sqb - 1) * (0x2 >> sq->max_sqe_sz) * 8));\n \t\troc_npa_aura_op_free(sq->aura_handle, 1, (uint64_t)sqb_buf);\n \t\tsqb_buf = next_sqb;\n \t\tcount--;\n@@ -1206,9 +1205,8 @@ sq_fini(struct nix *nix, struct roc_nix_sq *sq)\n \twhile (count) {\n \t\tvoid *next_sqb;\n \n-\t\tnext_sqb = *(void **)((uintptr_t)sqb_buf +\n-\t\t\t\t (uint32_t)((sqes_per_sqb - 1) *\n-\t\t\t\t\t\t sq->max_sqe_sz));\n+\t\tnext_sqb = *(void **)((uint64_t *)sqb_buf +\n+\t\t\t\t (uint32_t)((sqes_per_sqb - 1) * (0x2 >> sq->max_sqe_sz) * 8));\n \t\troc_npa_aura_op_free(sq->aura_handle, 1, (uint64_t)sqb_buf);\n \t\tsqb_buf = next_sqb;\n \t\tcount--;\n@@ -1386,3 +1384,25 @@ roc_nix_sq_head_tail_get(struct roc_nix *roc_nix, uint16_t qid, uint32_t *head,\n \t/* Update tail index as per used sqb count */\n \t*tail += (sqes_per_sqb * (sqb_cnt - 1));\n }\n+\n+int\n+roc_nix_q_err_cb_register(struct roc_nix *roc_nix, q_err_get_t sq_err_handle)\n+{\n+\tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n+\tstruct dev *dev = &nix->dev;\n+\n+\tif (sq_err_handle == NULL)\n+\t\treturn NIX_ERR_PARAM;\n+\n+\tdev->ops->q_err_cb = (q_err_cb_t)sq_err_handle;\n+\treturn 0;\n+}\n+\n+void\n+roc_nix_q_err_cb_unregister(struct roc_nix *roc_nix)\n+{\n+\tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n+\tstruct dev *dev = &nix->dev;\n+\n+\tdev->ops->q_err_cb = NULL;\n+}\ndiff --git a/drivers/common/cnxk/roc_nix_tm.c b/drivers/common/cnxk/roc_nix_tm.c\nindex be8da714cd..255ca83f48 100644\n--- a/drivers/common/cnxk/roc_nix_tm.c\n+++ b/drivers/common/cnxk/roc_nix_tm.c\n@@ -607,6 +607,136 @@ roc_nix_tm_sq_flush_spin(struct roc_nix_sq *sq)\n \treturn -EFAULT;\n }\n \n+void\n+nix_tm_sq_free_sqe_buffer(uint64_t *sqe, int head_off, int end_off, int instr_sz)\n+{\n+\tint i, j, inc = (8 * (0x2 >> instr_sz)), segs;\n+\tstruct nix_send_hdr_s *send_hdr;\n+\tuint64_t *ptr, aura_handle;\n+\tstruct idev_cfg *idev;\n+\n+\tif (!sqe)\n+\t\treturn;\n+\n+\tidev = idev_get_cfg();\n+\tif (idev == NULL)\n+\t\treturn;\n+\n+\tptr = sqe + (head_off * inc);\n+\tfor (i = head_off; i < end_off; i++) {\n+\t\tptr = sqe + (i * inc);\n+\t\tsend_hdr = (struct nix_send_hdr_s *)(ptr);\n+\t\taura_handle = roc_npa_aura_handle_gen(send_hdr->w0.aura, idev->npa->base);\n+\t\tptr += 2;\n+\t\tif (((*ptr >> 60) & 0xF) == NIX_SUBDC_EXT)\n+\t\t\tptr += 2;\n+\t\tif (((*ptr >> 60) & 0xF) == NIX_SUBDC_AGE_AND_STATS)\n+\t\t\tptr += 2;\n+\t\tif (((*ptr >> 60) & 0xF) == NIX_SUBDC_JUMP) {\n+\t\t\tptr += 1;\n+\t\t\tptr = (uint64_t *)*ptr;\n+\t\t}\n+\t\tif (((*ptr >> 60) & 0xF) == NIX_SUBDC_CRC)\n+\t\t\tptr += 2;\n+\t\t/* We are not parsing immediate send descriptor */\n+\t\tif (((*ptr >> 60) & 0xF) == NIX_SUBDC_IMM)\n+\t\t\tcontinue;\n+\t\twhile (1) {\n+\t\t\tif (((*ptr >> 60) & 0xF) == NIX_SUBDC_SG) {\n+\t\t\t\tsegs = (*ptr >> 48) & 0x3;\n+\t\t\t\tptr += 1;\n+\t\t\t\tfor (j = 0; j < segs; j++) {\n+\t\t\t\t\troc_npa_aura_op_free(aura_handle, 0, *ptr);\n+\t\t\t\t\tptr += 1;\n+\t\t\t\t}\n+\t\t\t\tif (segs == 2)\n+\t\t\t\t\tptr += 1;\n+\t\t\t} else if (((*ptr >> 60) & 0xF) == NIX_SUBDC_SG2) {\n+\t\t\t\tuint64_t aura = (*ptr >> 16) & 0xFFFFF;\n+\n+\t\t\t\taura = roc_npa_aura_handle_gen(aura, idev->npa->base);\n+\t\t\t\tptr += 1;\n+\t\t\t\troc_npa_aura_op_free(aura, 0, *ptr);\n+\t\t\t\tptr += 1;\n+\t\t\t} else\n+\t\t\t\tbreak;\n+\t\t}\n+\t}\n+}\n+\n+int\n+roc_nix_tm_sq_free_pending_sqe(struct nix *nix, int q)\n+{\n+\tint head_off, count, rc = 0, tail_off;\n+\tstruct roc_nix_sq *sq = nix->sqs[q];\n+\tvoid *sqb_buf, *dat, *tail_sqb;\n+\tstruct dev *dev = &nix->dev;\n+\tstruct ndc_sync_op *ndc_req;\n+\tuint16_t sqes_per_sqb;\n+\tstruct mbox *mbox;\n+\n+\tmbox = dev->mbox;\n+\t/* Sync NDC-NIX-TX for LF */\n+\tndc_req = mbox_alloc_msg_ndc_sync_op(mbox);\n+\tif (ndc_req == NULL)\n+\t\treturn -EFAULT;\n+\n+\tndc_req->nix_lf_tx_sync = 1;\n+\tif (mbox_process(mbox))\n+\t\trc |= NIX_ERR_NDC_SYNC;\n+\n+\tif (rc)\n+\t\tplt_err(\"NDC_SYNC failed rc %d\", rc);\n+\n+\trc = nix_q_ctx_get(dev, NIX_AQ_CTYPE_SQ, q, (void *)&dat);\n+\n+\tif (roc_model_is_cn9k()) {\n+\t\tvolatile struct nix_sq_ctx_s *ctx = (struct nix_sq_ctx_s *)dat;\n+\n+\t\t/* We will cleanup SQE buffers only when we received MNQ interrupt */\n+\t\tif (!ctx->mnq_dis)\n+\t\t\treturn -EFAULT;\n+\n+\t\tcount = ctx->sqb_count;\n+\t\tsqb_buf = (void *)ctx->head_sqb;\n+\t\ttail_sqb = (void *)ctx->tail_sqb;\n+\t\thead_off = ctx->head_offset;\n+\t\ttail_off = ctx->tail_offset;\n+\t} else {\n+\t\tvolatile struct nix_cn10k_sq_ctx_s *ctx = (struct nix_cn10k_sq_ctx_s *)dat;\n+\n+\t\t/* We will cleanup SQE buffers only when we received MNQ interrupt */\n+\t\tif (!ctx->mnq_dis)\n+\t\t\treturn -EFAULT;\n+\n+\t\tcount = ctx->sqb_count;\n+\t\t/* Free SQB's that are used */\n+\t\tsqb_buf = (void *)ctx->head_sqb;\n+\t\ttail_sqb = (void *)ctx->tail_sqb;\n+\t\thead_off = ctx->head_offset;\n+\t\ttail_off = ctx->tail_offset;\n+\t}\n+\tsqes_per_sqb = 1 << sq->sqes_per_sqb_log2;\n+\t/* Free SQB's that are used */\n+\twhile (count) {\n+\t\tvoid *next_sqb;\n+\n+\t\tif (sqb_buf == tail_sqb)\n+\t\t\tnix_tm_sq_free_sqe_buffer(sqb_buf, head_off, tail_off, sq->max_sqe_sz);\n+\t\telse\n+\t\t\tnix_tm_sq_free_sqe_buffer(sqb_buf, head_off, (sqes_per_sqb - 1),\n+\t\t\t\t\t\t sq->max_sqe_sz);\n+\t\tnext_sqb = *(void **)((uint64_t *)sqb_buf +\n+\t\t\t\t (uint32_t)((sqes_per_sqb - 1) * (0x2 >> sq->max_sqe_sz) * 8));\n+\t\troc_npa_aura_op_free(sq->aura_handle, 1, (uint64_t)sqb_buf);\n+\t\tsqb_buf = next_sqb;\n+\t\thead_off = 0;\n+\t\tcount--;\n+\t}\n+\n+\treturn 0;\n+}\n+\n /* Flush and disable tx queue and its parent SMQ */\n int\n nix_tm_sq_flush_pre(struct roc_nix_sq *sq)\n@@ -635,7 +765,7 @@ nix_tm_sq_flush_pre(struct roc_nix_sq *sq)\n \n \t/* Find the node for this SQ */\n \tnode = nix_tm_node_search(nix, qid, tree);\n-\tif (!node || !(node->flags & NIX_TM_NODE_ENABLED)) {\n+\tif (!node) {\n \t\tplt_err(\"Invalid node/state for sq %u\", qid);\n \t\treturn -EFAULT;\n \t}\n@@ -691,8 +821,13 @@ nix_tm_sq_flush_pre(struct roc_nix_sq *sq)\n \t\t/* Wait for sq entries to be flushed */\n \t\trc = roc_nix_tm_sq_flush_spin(sq);\n \t\tif (rc) {\n-\t\t\tplt_err(\"Failed to drain sq %u, rc=%d\\n\", sq->qid, rc);\n-\t\t\treturn rc;\n+\t\t\trc = roc_nix_tm_sq_free_pending_sqe(nix, sq->qid);\n+\t\t\tif (rc) {\n+\t\t\t\tplt_err(\"Failed to drain sq %u, rc=%d\\n\", sq->qid, rc);\n+\t\t\t\treturn rc;\n+\t\t\t}\n+\t\t\t/* Freed all pending SQEs for this SQ, so disable this node */\n+\t\t\tsibling->flags &= ~NIX_TM_NODE_ENABLED;\n \t\t}\n \t}\n \ndiff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map\nindex 17f0ec6b48..70503c0470 100644\n--- a/drivers/common/cnxk/version.map\n+++ b/drivers/common/cnxk/version.map\n@@ -224,6 +224,8 @@ INTERNAL {\n \troc_nix_ptp_rx_ena_dis;\n \troc_nix_ptp_sync_time_adjust;\n \troc_nix_ptp_tx_ena_dis;\n+\troc_nix_q_err_cb_register;\n+\troc_nix_q_err_cb_unregister;\n \troc_nix_queues_ctx_dump;\n \troc_nix_ras_intr_ena_dis;\n \troc_nix_reassembly_configure;\n", "prefixes": [ "01/11" ] }