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GET /api/patches/119925/?format=api
{ "id": 119925, "url": "http://patches.dpdk.org/api/patches/119925/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20221117072558.3582292-2-asekhar@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20221117072558.3582292-2-asekhar@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20221117072558.3582292-2-asekhar@marvell.com", "date": "2022-11-17T07:25:57", "name": "[v1,2/3] net/cnxk: add sg2 descriptor support", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "06c2ecaf7f4b9be18849a41d5c4e24f241411d84", "submitter": { "id": 2125, "url": "http://patches.dpdk.org/api/people/2125/?format=api", "name": "Ashwin Sekhar T K", "email": "asekhar@marvell.com" }, "delegate": { "id": 310, "url": "http://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20221117072558.3582292-2-asekhar@marvell.com/mbox/", "series": [ { "id": 25794, "url": "http://patches.dpdk.org/api/series/25794/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=25794", "date": "2022-11-17T07:25:56", "name": "[v1,1/3] net/cnxk: rework no-fast-free offload handling", "version": 1, "mbox": "http://patches.dpdk.org/series/25794/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/119925/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/119925/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 89505A00C2;\n\tThu, 17 Nov 2022 08:26:13 +0100 (CET)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 760AF40F18;\n\tThu, 17 Nov 2022 08:26:13 +0100 (CET)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n [67.231.156.173])\n by mails.dpdk.org (Postfix) with ESMTP id CA44740F18\n for <dev@dpdk.org>; Thu, 17 Nov 2022 08:26:12 +0100 (CET)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n by mx0b-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id\n 2AH6pSaD025126 for <dev@dpdk.org>; Wed, 16 Nov 2022 23:26:12 -0800", "from dc5-exch01.marvell.com ([199.233.59.181])\n by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3kwg2b0304-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Wed, 16 Nov 2022 23:26:12 -0800", "from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2;\n Wed, 16 Nov 2022 23:26:10 -0800", "from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend\n Transport; Wed, 16 Nov 2022 23:26:10 -0800", "from localhost.localdomain (unknown [10.28.36.142])\n by maili.marvell.com (Postfix) with ESMTP id 99B5A5B692A;\n Wed, 16 Nov 2022 23:26:06 -0800 (PST)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-transfer-encoding : content-type; s=pfpt0220;\n bh=r3d/jc0onlsocHFoVJEi4OcGvDojwm4eScETiwgh0xw=;\n b=VczL5fzUn0JFk94UTUsn+DAdJb8DeEfZU91lPKpClLfdn4oC+HODc4cqWa0olL4dcBTR\n e34Oc0saOERm71qyj44byiv8k6C0Hm1BQX1qEW2p8ZER2M9TuKjlFJyCIZIIl+5GiQ4x\n 7v5sQ689+2vQvy5iyQnf3U2Ero6WZlMXCe9YX0RJjDagx/ilVyx5FinGKQ413+iHoJIj\n WerUTaha/8njC01F0Vpn3FdK7ITtJnF4J32ZJpsuZkqVe8j/sYAqc+s2++iuPj+Xkady\n XCtaR8gozI079MkrrJkt+hQGjzecYtf7i7URxb8JPlrONI4+B9HQ7tOEearO6e2uCpzT 9g==", "From": "Ashwin Sekhar T K <asekhar@marvell.com>", "To": "<dev@dpdk.org>, Nithin Dabilpuram <ndabilpuram@marvell.com>, Kiran Kumar K\n <kirankumark@marvell.com>, Sunil Kumar Kori <skori@marvell.com>, Satha Rao\n <skoteshwar@marvell.com>", "CC": "<jerinj@marvell.com>, <pbhagavatula@marvell.com>, <psatheesh@marvell.com>,\n <asekhar@marvell.com>, <anoobj@marvell.com>, <gakhil@marvell.com>,\n <hkalra@marvell.com>", "Subject": "[PATCH v1 2/3] net/cnxk: add sg2 descriptor support", "Date": "Thu, 17 Nov 2022 12:55:57 +0530", "Message-ID": "<20221117072558.3582292-2-asekhar@marvell.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20221117072558.3582292-1-asekhar@marvell.com>", "References": "<20221117072558.3582292-1-asekhar@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-GUID": "0szwnZJmhDLLR17NZAvaqfSSEHYIG2g0", "X-Proofpoint-ORIG-GUID": "0szwnZJmhDLLR17NZAvaqfSSEHYIG2g0", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.219,Aquarius:18.0.895,Hydra:6.0.545,FMLib:17.11.122.1\n definitions=2022-11-17_04,2022-11-16_01,2022-06-22_01", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Add support for creating packets with segments from different\npools. This is enabled by using the SG2 descriptors. SG2\ndescriptors are only used when the segment is to be freed\nby the HW.\n\nSigned-off-by: Ashwin Sekhar T K <asekhar@marvell.com>\n---\n drivers/net/cnxk/cn10k_tx.h | 161 +++++++++++++++++++++++++++---------\n 1 file changed, 123 insertions(+), 38 deletions(-)", "diff": "diff --git a/drivers/net/cnxk/cn10k_tx.h b/drivers/net/cnxk/cn10k_tx.h\nindex a4c578354c..3f08a8a473 100644\n--- a/drivers/net/cnxk/cn10k_tx.h\n+++ b/drivers/net/cnxk/cn10k_tx.h\n@@ -54,6 +54,36 @@\n \n #define NIX_NB_SEGS_TO_SEGDW(x) ((NIX_SEGDW_MAGIC >> ((x) << 2)) & 0xF)\n \n+static __plt_always_inline uint8_t\n+cn10k_nix_mbuf_sg_dwords(struct rte_mbuf *m)\n+{\n+\tuint32_t nb_segs = m->nb_segs;\n+\tuint16_t aura0, aura;\n+\tint segw, sg_segs;\n+\n+\taura0 = roc_npa_aura_handle_to_aura(m->pool->pool_id);\n+\n+\tnb_segs--;\n+\tsegw = 2;\n+\tsg_segs = 1;\n+\twhile (nb_segs) {\n+\t\tm = m->next;\n+\t\taura = roc_npa_aura_handle_to_aura(m->pool->pool_id);\n+\t\tif (aura != aura0) {\n+\t\t\tsegw += 2 + (sg_segs == 2);\n+\t\t\tsg_segs = 0;\n+\t\t} else {\n+\t\t\tsegw += (sg_segs == 0); /* SUBDC */\n+\t\t\tsegw += 1;\t\t/* IOVA */\n+\t\t\tsg_segs += 1;\n+\t\t\tsg_segs %= 3;\n+\t\t}\n+\t\tnb_segs--;\n+\t}\n+\n+\treturn (segw + 1) / 2;\n+}\n+\n static __plt_always_inline void\n cn10k_nix_vwqe_wait_fc(struct cn10k_eth_txq *txq, int64_t req)\n {\n@@ -915,15 +945,15 @@ cn10k_nix_xmit_prepare_tstamp(struct cn10k_eth_txq *txq, uintptr_t lmt_addr,\n static __rte_always_inline uint16_t\n cn10k_nix_prepare_mseg(struct rte_mbuf *m, uint64_t *cmd, const uint16_t flags)\n {\n+\tuint64_t prefree = 0, aura0, aura, nb_segs, segdw;\n \tstruct nix_send_hdr_s *send_hdr;\n-\tunion nix_send_sg_s *sg;\n+\tunion nix_send_sg_s *sg, l_sg;\n+\tunion nix_send_sg2_s l_sg2;\n \tstruct rte_mbuf *m_next;\n-\tuint64_t *slist, sg_u;\n+\tuint8_t off, is_sg2;\n \tuint64_t len, dlen;\n \tuint64_t ol_flags;\n-\tuint64_t nb_segs;\n-\tuint64_t segdw;\n-\tuint8_t off, i;\n+\tuint64_t *slist;\n \n \tsend_hdr = (struct nix_send_hdr_s *)cmd;\n \n@@ -938,20 +968,22 @@ cn10k_nix_prepare_mseg(struct rte_mbuf *m, uint64_t *cmd, const uint16_t flags)\n \t\tol_flags = m->ol_flags;\n \n \t/* Start from second segment, first segment is already there */\n-\ti = 1;\n-\tsg_u = sg->u;\n-\tlen -= sg_u & 0xFFFF;\n+\tis_sg2 = 0;\n+\tl_sg.u = sg->u;\n+\tlen -= l_sg.u & 0xFFFF;\n \tnb_segs = m->nb_segs - 1;\n \tm_next = m->next;\n \tslist = &cmd[3 + off + 1];\n \n \t/* Set invert df if buffer is not to be freed by H/W */\n-\tif (flags & NIX_TX_OFFLOAD_MBUF_NOFF_F)\n-\t\tsg_u |= (cnxk_nix_prefree_seg(m) << 55);\n+\tif (flags & NIX_TX_OFFLOAD_MBUF_NOFF_F) {\n+\t\tprefree = cnxk_nix_prefree_seg(m);\n+\t\tl_sg.i1 = prefree;\n+\t}\n \n-\t\t/* Mark mempool object as \"put\" since it is freed by NIX */\n #ifdef RTE_LIBRTE_MEMPOOL_DEBUG\n-\tif (!(sg_u & (1ULL << 55)))\n+\t/* Mark mempool object as \"put\" since it is freed by NIX */\n+\tif (!prefree)\n \t\tRTE_MEMPOOL_CHECK_COOKIES(m->pool, (void **)&m, 1, 0);\n \trte_io_wmb();\n #endif\n@@ -964,55 +996,103 @@ cn10k_nix_prepare_mseg(struct rte_mbuf *m, uint64_t *cmd, const uint16_t flags)\n \tif (!(flags & NIX_TX_MULTI_SEG_F))\n \t\tgoto done;\n \n+\taura0 = send_hdr->w0.aura;\n \tm = m_next;\n \tif (!m)\n \t\tgoto done;\n \n \t/* Fill mbuf segments */\n \tdo {\n+\t\tuint64_t iova;\n+\n+\t\t/* Save the current mbuf properties. These can get cleared in\n+\t\t * cnxk_nix_prefree_seg()\n+\t\t */\n \t\tm_next = m->next;\n+\t\tiova = rte_mbuf_data_iova(m);\n \t\tdlen = m->data_len;\n \t\tlen -= dlen;\n-\t\tsg_u = sg_u | ((uint64_t)dlen << (i << 4));\n-\t\t*slist = rte_mbuf_data_iova(m);\n-\t\t/* Set invert df if buffer is not to be freed by H/W */\n-\t\tif (flags & NIX_TX_OFFLOAD_MBUF_NOFF_F)\n-\t\t\tsg_u |= (cnxk_nix_prefree_seg(m) << (i + 55));\n-\t\t\t/* Mark mempool object as \"put\" since it is freed by NIX\n-\t\t\t */\n-#ifdef RTE_LIBRTE_MEMPOOL_DEBUG\n-\t\tif (!(sg_u & (1ULL << (i + 55))))\n-\t\t\tRTE_MEMPOOL_CHECK_COOKIES(m->pool, (void **)&m, 1, 0);\n-#endif\n-\t\tslist++;\n-\t\ti++;\n+\n \t\tnb_segs--;\n-\t\tif (i > 2 && nb_segs) {\n-\t\t\ti = 0;\n+\t\taura = aura0;\n+\t\tprefree = 0;\n+\n+\t\tif (flags & NIX_TX_OFFLOAD_MBUF_NOFF_F) {\n+\t\t\taura = roc_npa_aura_handle_to_aura(m->pool->pool_id);\n+\t\t\tprefree = cnxk_nix_prefree_seg(m);\n+\t\t\tis_sg2 = aura != aura0 && !prefree;\n+\t\t}\n+\n+\t\tif (unlikely(is_sg2)) {\n+\t\t\t/* This mbuf belongs to a different pool and\n+\t\t\t * DF bit is not to be set, so use SG2 subdesc\n+\t\t\t * so that it is freed to the appropriate pool.\n+\t\t\t */\n+\n+\t\t\t/* Write the previous descriptor out */\n+\t\t\tsg->u = l_sg.u;\n+\n+\t\t\t/* If the current SG subdc does not have any\n+\t\t\t * iovas in it, then the SG2 subdc can overwrite\n+\t\t\t * that SG subdc.\n+\t\t\t *\n+\t\t\t * If the current SG subdc has 2 iovas in it, then\n+\t\t\t * the current iova word should be left empty.\n+\t\t\t */\n+\t\t\tslist += (-1 + (int)l_sg.segs);\n+\t\t\tsg = (union nix_send_sg_s *)slist;\n+\n+\t\t\tl_sg2.u = l_sg.u & 0xC00000000000000; /* LD_TYPE */\n+\t\t\tl_sg2.subdc = NIX_SUBDC_SG2;\n+\t\t\tl_sg2.aura = aura;\n+\t\t\tl_sg2.seg1_size = dlen;\n+\t\t\tl_sg.u = l_sg2.u;\n+\n+\t\t\tslist++;\n+\t\t\t*slist = iova;\n+\t\t\tslist++;\n+\t\t} else {\n+\t\t\t*slist = iova;\n+\t\t\t/* Set invert df if buffer is not to be freed by H/W */\n+\t\t\tl_sg.u |= (prefree << (l_sg.segs + 55));\n+\t\t\t/* Set the segment length */\n+\t\t\tl_sg.u |= ((uint64_t)dlen << (l_sg.segs << 4));\n+\t\t\tl_sg.segs += 1;\n+\t\t\tslist++;\n+\t\t}\n+\n+\t\tif ((is_sg2 || l_sg.segs > 2) && nb_segs) {\n+\t\t\tsg->u = l_sg.u;\n \t\t\t/* Next SG subdesc */\n-\t\t\t*(uint64_t *)slist = sg_u & 0xFC00000000000000;\n-\t\t\tsg->u = sg_u;\n-\t\t\tsg->segs = 3;\n \t\t\tsg = (union nix_send_sg_s *)slist;\n-\t\t\tsg_u = sg->u;\n+\t\t\tl_sg.u &= 0xC00000000000000; /* LD_TYPE */\n+\t\t\tl_sg.subdc = NIX_SUBDC_SG;\n \t\t\tslist++;\n \t\t}\n \t\tm->next = NULL;\n+\n+#ifdef RTE_LIBRTE_MEMPOOL_DEBUG\n+\t\t/* Mark mempool object as \"put\" since it is freed by NIX\n+\t\t */\n+\t\tif (!prefree)\n+\t\t\tRTE_MEMPOOL_CHECK_COOKIES(m->pool, (void **)&m, 1, 0);\n+#endif\n \t\tm = m_next;\n \t} while (nb_segs);\n \n done:\n \t/* Add remaining bytes of security data to last seg */\n \tif (flags & NIX_TX_OFFLOAD_SECURITY_F && ol_flags & RTE_MBUF_F_TX_SEC_OFFLOAD && len) {\n-\t\tuint8_t shft = ((i - 1) << 4);\n+\t\tuint8_t shft = (l_sg.subdc == NIX_SUBDC_SG) ? ((l_sg.segs - 1) << 4) : 0;\n \n-\t\tdlen = ((sg_u >> shft) & 0xFFFFULL) + len;\n-\t\tsg_u = sg_u & ~(0xFFFFULL << shft);\n-\t\tsg_u |= dlen << shft;\n+\t\tdlen = ((l_sg.u >> shft) & 0xFFFFULL) + len;\n+\t\tl_sg.u = l_sg.u & ~(0xFFFFULL << shft);\n+\t\tl_sg.u |= dlen << shft;\n \t}\n \n-\tsg->u = sg_u;\n-\tsg->segs = i;\n+\t/* Write the last subdc out */\n+\tsg->u = l_sg.u;\n+\n \tsegdw = (uint64_t *)slist - (uint64_t *)&cmd[2 + off];\n \t/* Roundup extra dwords to multiple of 2 */\n \tsegdw = (segdw >> 1) + (segdw & 0x1);\n@@ -1827,7 +1907,12 @@ cn10k_nix_xmit_pkts_vector(void *tx_queue, uint64_t *ws,\n \t\t\t\tstruct rte_mbuf *m = tx_pkts[j];\n \n \t\t\t\t/* Get dwords based on nb_segs. */\n-\t\t\t\tsegdw[j] = NIX_NB_SEGS_TO_SEGDW(m->nb_segs);\n+\t\t\t\tif (!(flags & NIX_TX_OFFLOAD_MBUF_NOFF_F &&\n+\t\t\t\t flags & NIX_TX_MULTI_SEG_F))\n+\t\t\t\t\tsegdw[j] = NIX_NB_SEGS_TO_SEGDW(m->nb_segs);\n+\t\t\t\telse\n+\t\t\t\t\tsegdw[j] = cn10k_nix_mbuf_sg_dwords(m);\n+\n \t\t\t\t/* Add dwords based on offloads. */\n \t\t\t\tsegdw[j] += 1 + /* SEND HDR */\n \t\t\t\t\t !!(flags & NIX_TX_NEED_EXT_HDR) +\n", "prefixes": [ "v1", "2/3" ] }