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GET /api/patches/119690/?format=api
{ "id": 119690, "url": "http://patches.dpdk.org/api/patches/119690/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20221110020950.662431-1-rongweil@nvidia.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20221110020950.662431-1-rongweil@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20221110020950.662431-1-rongweil@nvidia.com", "date": "2022-11-10T02:09:49", "name": "[v1] net/mlx5: fix missing marks on received packets", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "55eb985668a1068c712f2092979edf8a96e2ca75", "submitter": { "id": 2223, "url": "http://patches.dpdk.org/api/people/2223/?format=api", "name": "rongwei liu", "email": "rongweil@nvidia.com" }, "delegate": { "id": 3268, "url": "http://patches.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20221110020950.662431-1-rongweil@nvidia.com/mbox/", "series": [ { "id": 25682, "url": "http://patches.dpdk.org/api/series/25682/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=25682", "date": "2022-11-10T02:09:49", "name": "[v1] net/mlx5: fix missing marks on received packets", "version": 1, "mbox": "http://patches.dpdk.org/series/25682/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/119690/comments/", "check": "fail", "checks": "http://patches.dpdk.org/api/patches/119690/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 6F748A04FD;\n\tThu, 10 Nov 2022 03:10:23 +0100 (CET)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 5610440156;\n\tThu, 10 Nov 2022 03:10:23 +0100 (CET)", "from NAM10-BN7-obe.outbound.protection.outlook.com\n (mail-bn7nam10on2089.outbound.protection.outlook.com [40.107.92.89])\n by mails.dpdk.org (Postfix) with ESMTP id 5CCF2400D4;\n Thu, 10 Nov 2022 03:10:22 +0100 (CET)", "from BN0PR04CA0161.namprd04.prod.outlook.com (2603:10b6:408:eb::16)\n by DM4PR12MB5988.namprd12.prod.outlook.com (2603:10b6:8:6b::20) with\n Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5791.27; 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helo=mail.nvidia.com; pr=C", "From": "Rongwei Liu <rongweil@nvidia.com>", "To": "<matan@nvidia.com>, <viacheslavo@nvidia.com>, <orika@nvidia.com>,\n <thomas@monjalon.net>, Suanming Mou <suanmingm@nvidia.com>", "CC": "<dev@dpdk.org>, <rasland@nvidia.com>, <stable@dpdk.org>", "Subject": "[PATCH v1] net/mlx5: fix missing marks on received packets", "Date": "Thu, 10 Nov 2022 04:09:49 +0200", "Message-ID": "<20221110020950.662431-1-rongweil@nvidia.com>", "X-Mailer": "git-send-email 2.27.0", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[10.126.230.35]", "X-ClientProxiedBy": "rnnvmail201.nvidia.com (10.129.68.8) To\n rnnvmail201.nvidia.com (10.129.68.8)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "BN8NAM11FT011:EE_|DM4PR12MB5988:EE_", "X-MS-Office365-Filtering-Correlation-Id": "0df0d16c-edb6-45f9-125a-08dac2c0b824", "X-LD-Processed": "43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n qgNFHsARHiH2PMdc6ZdrxcSOyz4dd9fYrcqoEU/A9e9/397vOOoPadAfohwrw7QK1GmoNTj2ucCSYKL6WABAEMBV9CLgYSalYPPdrrHzNO1dL4eLKNBYp69HH1ZpQeK6fj7XMF+7wKYVH5MEMq5PdE6skBPLk9yB140UOmt0p94GX9mbn4Qe1642y9ZLLG3e3SwIGx99JbnSOh6oSIo7LZ1xXADtfqCAE4MCnnkZACuqXUAYpG8sDjpaYpnGFsn9YWadrXEnUijnWSSENk6dJgTAGnoFrvv86TDrPWyLPipfL0wkWSzVWXbgBwcN/kCmr8ssKyPreBFdETSbDKKQm+2zemDw9zbYpn3PWPExxIJ2WSPpB5uRc8O0WOtTxSdTwP6yn/C6jpbsBT/SlS1lrO+XKIyxzXycqFRUPdQphbYjWMEFnz6H1cvKo9AQ35hawCNU7f15ULMLl8igMzrdWjaIfnE8baIfss6dv0RtTkR8p5yyxkeyFazSPDhJcgOH06+5OwhkKuu+bUUDA3/BC4n/xC6AJyn5vCvSqsMy13dGuB2wSqswIUygZ9q0SAAK4YW3Mnw2bSrQzuNfgczBiAcdaPxT6hQDdMxbBM11lRdRp68/iJbN0DiLkgZyVPse27dtMK1NrW6aSo4t0VtPAn938RIdzVnIVGCbgyT6k6ltgwTDHc9sEFkhtbZNicDiA/JVzt08ENAu5N46mq5wUUkNb9YmiYnrJGQPSurVWHg7fa50zcXL0AA8Yj+cCOsEsRQM2p8UUOIY6olHhZwCbw==", "X-Forefront-Antispam-Report": "CIP:216.228.117.161; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE;\n SFS:(13230022)(4636009)(376002)(39860400002)(136003)(396003)(346002)(451199015)(40470700004)(36840700001)(46966006)(110136005)(40480700001)(54906003)(6636002)(186003)(55016003)(316002)(47076005)(5660300002)(426003)(2906002)(2616005)(41300700001)(36756003)(336012)(70586007)(8936002)(6286002)(7696005)(70206006)(26005)(1076003)(16526019)(8676002)(4326008)(40460700003)(83380400001)(478600001)(356005)(82310400005)(7636003)(86362001)(36860700001)(6666004)(82740400003);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "10 Nov 2022 02:10:20.3196 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 0df0d16c-edb6-45f9-125a-08dac2c0b824", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n BN8NAM11FT011.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "DM4PR12MB5988", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "If HW Steering is enabled, Rx queues were configured to receive MARKs\nwhen a table with MARK actions was created. After stopping the port,\nRx queue configuration is released, but during starting the port\nthe mark flag was not updated in the Rx queue configuration.\n\nThis patch introduces a reference count on the MARK action and it\nincreases/decreases per template_table create/destroy.\n\nWhen the port is stopped, Rx queue configuration is not cleared if\nreference count is not zero.\n\nFixes: 3a2f674b6aa8 (\"net/mlx5: add queue and RSS HW steering action\")\nCc: stable@dpdk.org\nSigned-off-by: Rongwei Liu <rongweil@nvidia.com>\nAcked-by: Matan Azrad <matan@nvidia.com>\n---\n drivers/net/mlx5/mlx5.c | 3 ++-\n drivers/net/mlx5/mlx5.h | 1 +\n drivers/net/mlx5/mlx5_flow.c | 28 +++++++++++++++++++++++++++\n drivers/net/mlx5/mlx5_flow.h | 2 ++\n drivers/net/mlx5/mlx5_flow_hw.c | 34 ++++++---------------------------\n drivers/net/mlx5/mlx5_trigger.c | 7 ++++++-\n 6 files changed, 45 insertions(+), 30 deletions(-)", "diff": "diff --git a/drivers/net/mlx5/mlx5.c b/drivers/net/mlx5/mlx5.c\nindex 1cf6df6049..bef8e35b6d 100644\n--- a/drivers/net/mlx5/mlx5.c\n+++ b/drivers/net/mlx5/mlx5.c\n@@ -2010,7 +2010,8 @@ mlx5_dev_close(struct rte_eth_dev *dev)\n \t * If default mreg copy action is removed at the stop stage,\n \t * the search will return none and nothing will be done anymore.\n \t */\n-\tmlx5_flow_stop_default(dev);\n+\tif (priv->sh->config.dv_flow_en != 2)\n+\t\tmlx5_flow_stop_default(dev);\n \tmlx5_traffic_disable(dev);\n \t/*\n \t * If all the flows are already flushed in the device stop stage,\ndiff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h\nindex 7d82cb7c8f..02bee5808d 100644\n--- a/drivers/net/mlx5/mlx5.h\n+++ b/drivers/net/mlx5/mlx5.h\n@@ -1747,6 +1747,7 @@ struct mlx5_priv {\n \tuint32_t flex_item_map; /* Map of allocated flex item elements. */\n \tuint32_t nb_queue; /* HW steering queue number. */\n \tstruct mlx5_hws_cnt_pool *hws_cpool; /* HW steering's counter pool. */\n+\tuint32_t hws_mark_refcnt; /* HWS mark action reference counter. */\n #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)\n \t/* Item template list. */\n \tLIST_HEAD(flow_hw_itt, rte_flow_pattern_template) flow_hw_itt;\ndiff --git a/drivers/net/mlx5/mlx5_flow.c b/drivers/net/mlx5/mlx5_flow.c\nindex b3c1336ab8..a0cf677fb0 100644\n--- a/drivers/net/mlx5/mlx5_flow.c\n+++ b/drivers/net/mlx5/mlx5_flow.c\n@@ -7499,6 +7499,34 @@ mlx5_flow_stop_default(struct rte_eth_dev *dev)\n \tflow_rxq_flags_clear(dev);\n }\n \n+/**\n+ * Set rxq flag.\n+ *\n+ * @param[in] dev\n+ * Pointer to the rte_eth_dev structure.\n+ * @param[in] enable\n+ * Flag to enable or not.\n+ */\n+void\n+flow_hw_rxq_flag_set(struct rte_eth_dev *dev, bool enable)\n+{\n+\tstruct mlx5_priv *priv = dev->data->dev_private;\n+\tunsigned int i;\n+\n+\tif ((!priv->mark_enabled && !enable) ||\n+\t (priv->mark_enabled && enable))\n+\t\treturn;\n+\tfor (i = 0; i < priv->rxqs_n; ++i) {\n+\t\tstruct mlx5_rxq_ctrl *rxq_ctrl = mlx5_rxq_ctrl_get(dev, i);\n+\n+\t\t/* With RXQ start/stop feature, RXQ might be stopped. */\n+\t\tif (!rxq_ctrl)\n+\t\t\tcontinue;\n+\t\trxq_ctrl->rxq.mark = enable;\n+\t}\n+\tpriv->mark_enabled = enable;\n+}\n+\n /**\n * Start all default actions for flows.\n *\ndiff --git a/drivers/net/mlx5/mlx5_flow.h b/drivers/net/mlx5/mlx5_flow.h\nindex 187e9a23bf..955383dd07 100644\n--- a/drivers/net/mlx5/mlx5_flow.h\n+++ b/drivers/net/mlx5/mlx5_flow.h\n@@ -2516,6 +2516,8 @@ mlx5_get_tof(const struct rte_flow_item *items,\n \t enum mlx5_tof_rule_type *rule_type);\n void\n flow_hw_resource_release(struct rte_eth_dev *dev);\n+void\n+flow_hw_rxq_flag_set(struct rte_eth_dev *dev, bool enable);\n int flow_dv_action_validate(struct rte_eth_dev *dev,\n \t\t\t const struct rte_flow_indir_action_conf *conf,\n \t\t\t const struct rte_flow_action *action,\ndiff --git a/drivers/net/mlx5/mlx5_flow_hw.c b/drivers/net/mlx5/mlx5_flow_hw.c\nindex 7f1ae0fbb0..537bcf141d 100644\n--- a/drivers/net/mlx5/mlx5_flow_hw.c\n+++ b/drivers/net/mlx5/mlx5_flow_hw.c\n@@ -155,34 +155,6 @@ static const struct rte_flow_item_eth ctrl_rx_eth_bcast_spec = {\n \t.type = 0,\n };\n \n-/**\n- * Set rxq flag.\n- *\n- * @param[in] dev\n- * Pointer to the rte_eth_dev structure.\n- * @param[in] enable\n- * Flag to enable or not.\n- */\n-static void\n-flow_hw_rxq_flag_set(struct rte_eth_dev *dev, bool enable)\n-{\n-\tstruct mlx5_priv *priv = dev->data->dev_private;\n-\tunsigned int i;\n-\n-\tif ((!priv->mark_enabled && !enable) ||\n-\t (priv->mark_enabled && enable))\n-\t\treturn;\n-\tfor (i = 0; i < priv->rxqs_n; ++i) {\n-\t\tstruct mlx5_rxq_ctrl *rxq_ctrl = mlx5_rxq_ctrl_get(dev, i);\n-\n-\t\t/* With RXQ start/stop feature, RXQ might be stopped. */\n-\t\tif (!rxq_ctrl)\n-\t\t\tcontinue;\n-\t\trxq_ctrl->rxq.mark = enable;\n-\t}\n-\tpriv->mark_enabled = enable;\n-}\n-\n /**\n * Set the hash fields according to the @p rss_desc information.\n *\n@@ -462,6 +434,10 @@ __flow_hw_action_template_destroy(struct rte_eth_dev *dev,\n \t\tmlx5_ipool_free(priv->acts_ipool, data->idx);\n \t}\n \n+\tif (acts->mark)\n+\t\tif (!__atomic_sub_fetch(&priv->hws_mark_refcnt, 1, __ATOMIC_RELAXED))\n+\t\t\tflow_hw_rxq_flag_set(dev, false);\n+\n \tif (acts->jump) {\n \t\tstruct mlx5_flow_group *grp;\n \n@@ -484,6 +460,7 @@ __flow_hw_action_template_destroy(struct rte_eth_dev *dev,\n \t\tif (acts->mhdr->action)\n \t\t\tmlx5dr_action_destroy(acts->mhdr->action);\n \t\tmlx5_free(acts->mhdr);\n+\t\tacts->mhdr = NULL;\n \t}\n \tif (mlx5_hws_cnt_id_valid(acts->cnt_id)) {\n \t\tmlx5_hws_cnt_shared_put(priv->hws_cpool, &acts->cnt_id);\n@@ -1422,6 +1399,7 @@ __flow_hw_actions_translate(struct rte_eth_dev *dev,\n \t\t\t\tgoto err;\n \t\t\tacts->rule_acts[action_pos].action =\n \t\t\t\tpriv->hw_tag[!!attr->group];\n+\t\t\t__atomic_add_fetch(&priv->hws_mark_refcnt, 1, __ATOMIC_RELAXED);\n \t\t\tflow_hw_rxq_flag_set(dev, true);\n \t\t\tbreak;\n \t\tcase RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:\ndiff --git a/drivers/net/mlx5/mlx5_trigger.c b/drivers/net/mlx5/mlx5_trigger.c\nindex 4b821a1076..df7ebf4ee0 100644\n--- a/drivers/net/mlx5/mlx5_trigger.c\n+++ b/drivers/net/mlx5/mlx5_trigger.c\n@@ -1408,7 +1408,12 @@ mlx5_dev_stop(struct rte_eth_dev *dev)\n \tmlx5_mp_os_req_stop_rxtx(dev);\n \trte_delay_us_sleep(1000 * priv->rxqs_n);\n \tDRV_LOG(DEBUG, \"port %u stopping device\", dev->data->port_id);\n-\tmlx5_flow_stop_default(dev);\n+\tif (priv->sh->config.dv_flow_en == 2) {\n+\t\tif (!__atomic_load_n(&priv->hws_mark_refcnt, __ATOMIC_RELAXED))\n+\t\t\tflow_hw_rxq_flag_set(dev, false);\n+\t} else {\n+\t\tmlx5_flow_stop_default(dev);\n+\t}\n \t/* Control flows for default traffic can be removed firstly. */\n \tmlx5_traffic_disable(dev);\n \t/* All RX queue flags will be cleared in the flush interface. */\n", "prefixes": [ "v1" ] }